JPH01248533A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH01248533A
JPH01248533A JP63077118A JP7711888A JPH01248533A JP H01248533 A JPH01248533 A JP H01248533A JP 63077118 A JP63077118 A JP 63077118A JP 7711888 A JP7711888 A JP 7711888A JP H01248533 A JPH01248533 A JP H01248533A
Authority
JP
Japan
Prior art keywords
protective film
internal circuit
pad
uppermost protective
metal wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63077118A
Other languages
Japanese (ja)
Inventor
Hitoshi Mitani
三谷　仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63077118A priority Critical patent/JPH01248533A/en
Publication of JPH01248533A publication Critical patent/JPH01248533A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To efficiently use or reduce the chip surface area by superimposing a bonding pad provided on the uppermost protective film on an internal circuit region. CONSTITUTION:The uppermost protective film is provided on an internal circuit region 2 including an element region and a metal wire 4 on a semiconductor board 1. A bonding pad 3 is provided on the uppermost protective film over the internal circuit region 2. This pad 3 is connected to the metal wire 4 through a contact hole 7 provided on an interlayer insulating film including the uppermost protective film. An internal lead 6 of a case is connected to the pad 3 by a bonding wire 5. In this way, the pad 3 provided on the uppermost protective film can be formed by being superimposed on the internal circuit region 2, thereby efficiently using the chip surface area.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路に関し、特にボンディングパ
ッドを有する半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having bonding pads.

〔従来の技術〕[Conventional technology]

第２図は従来の半導体集積回路を説明するための模式的
平面図である。第２図において、１は半導体基板、２は
内部回路領域、３はボンディングパッド、４はボンディ
ングパッドと接続する金属配線、５はボンディング線、
６はケースの内部リード、７はコンタクトホール、８は
各種ケースの内部リードパターンに対応するためのダミ
ーパッドである。FIG. 2 is a schematic plan view for explaining a conventional semiconductor integrated circuit. In FIG. 2, 1 is a semiconductor substrate, 2 is an internal circuit area, 3 is a bonding pad, 4 is a metal wiring connected to the bonding pad, 5 is a bonding line,
6 is an internal lead of the case, 7 is a contact hole, and 8 is a dummy pad for corresponding to the internal lead pattern of various cases.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体集積回路は、ボンディングパッド
が隣接した内部回路領域の金属配線と同一層内に形成さ
れているので、隣接した素子領域又は、内部回路の配線
との間の短絡、浸食に対する余裕を有した距離を設けて
ボンディングパッドを形成しなければならない、この為
、積層技術が進歩した現在においてもボンディングパッ
ドの形成領域には、他の回路等を形成する事が困難であ
る。更に、従来の半導体集積回路の多くは、様々なケー
スに実装する事を目的として、複数種のケースの内部リ
ードパターンに対応できるボンディングパッドを同時に
設けるためダミーパッドを有している。In the conventional semiconductor integrated circuit described above, the bonding pad is formed in the same layer as the metal wiring in the adjacent internal circuit area, so there is no margin for short circuits and corrosion with the adjacent element area or internal circuit wiring. The bonding pads must be formed at a distance of . Therefore, even with advances in lamination technology, it is difficult to form other circuits in the area where the bonding pads are formed. Furthermore, many conventional semiconductor integrated circuits have dummy pads for simultaneously providing bonding pads that can accommodate internal lead patterns of multiple types of cases for the purpose of mounting in various cases.

このように、従来の半導体集積回路は、そのチップ上に
ボンディングパッドの効率的な配置が出来ないだけでな
く、様々なケースに対応する為に無用なダミーパッド領
域を設けなければならず、レイアウトの自由度及び面積
的に非効率的な欠点を有している。In this way, conventional semiconductor integrated circuits not only cannot efficiently arrange bonding pads on the chip, but also have to provide unnecessary dummy pad areas to accommodate various cases, making the layout difficult. It has the disadvantage of being inefficient in terms of freedom and area.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体集積回路は、半導体基板上に設けた素子
領域と、前記素子領域に接続された金属配線と、前記素
子領域及び前記金属配線を含む内部回路領域上に設けた
最上層保護膜と、少くとも前記最上層保護膜を含む眉間
絶縁膜に設けたコンタクトホールを介して前記金属配線
と接続し且つ前記内部回路領域の上の前記最上層保護膜
上に設けたボンディングパッドとを備えている。The semiconductor integrated circuit of the present invention includes an element region provided on a semiconductor substrate, a metal wiring connected to the element region, and a top layer protective film provided on an internal circuit area including the element region and the metal wiring. , a bonding pad connected to the metal wiring through a contact hole provided in a glabellar insulating film including at least the uppermost protective film, and provided on the uppermost protective film above the internal circuit area. There is.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例を説明するための模式的平面
図である。FIG. 1 is a schematic plan view for explaining one embodiment of the present invention.

第１図に示すように、半導体基板１の上に設けた素子領
域と、前記素子領域に接続された金属配線４と、前記素
子領域及び金属配線４を含む内部回路領域２上に設けた
最上層保護膜と、少くとも前記最上層保護膜を含む眉間
絶縁膜に設けたコンタクトホール７を介して金属配線４
と接続し且つ、内部回路領域２の上の前記最上層保護膜
上に設けたボンディングパッド３とを備え、ケースの内
部リード６とボンディングパッド３との間をボンディン
グ線５で接続する。As shown in FIG. 1, an element area provided on a semiconductor substrate 1, a metal wiring 4 connected to the element area, and an inner circuit area 2 provided on an internal circuit area 2 including the element area and the metal wiring 4. The metal wiring 4 is connected to the upper protective film through the contact hole 7 provided in the glabellar insulating film including at least the uppermost protective film.
and a bonding pad 3 provided on the uppermost protective film above the internal circuit area 2, and a bonding line 5 connects between the internal lead 6 of the case and the bonding pad 3.

本実施例によれば、最上層保護膜上に設けたボンディン
グパッド３を内部回路領域２と重ねて形成することが可
能となり、チップ面積を有効に利用することができると
いう効果を有する。According to this embodiment, it is possible to form the bonding pad 3 provided on the uppermost protective film so as to overlap the internal circuit region 2, and this has the effect that the chip area can be used effectively.

また、金属配線で互いに接続されたダミーパッド８及び
ボンディングパッド９を実装するケースの配線パターン
に対応して形成することが可能でチップ面積の増加を招
かない。Furthermore, the dummy pads 8 and bonding pads 9 connected to each other by metal wiring can be formed in accordance with the wiring pattern of the case in which they are mounted, so that the chip area does not increase.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、最上層保護膜上に設けた
ボンディングパッドを内部回路領域上に重ねて配置する
ことにより、チップ面積の有効活用又はチップ面積の縮
小化を実現でき、且つ種々のケースの内部リードパター
ンにも対応できる半導体集積回路が得られるという効果
がある。As explained above, the present invention makes it possible to effectively utilize the chip area or reduce the chip area by arranging the bonding pads provided on the top layer protective film so as to overlap the internal circuit area. This has the effect of providing a semiconductor integrated circuit that can also be used with the internal lead pattern of the case.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を説明するための模式的平面
図、第２図は従来の半導体集積回路を説明するための模
式的平面図である。 １・・・半導体基板、２・・・内部回路領域、３．９・
・・ボンディングパッド、４・・・金属配線、５・・・
ボンディング線、６・・・ケースの内部リード、７・・
・コンタクトホール、８・・・ダミーパッド。FIG. 1 is a schematic plan view for explaining an embodiment of the present invention, and FIG. 2 is a schematic plan view for explaining a conventional semiconductor integrated circuit. 1... Semiconductor substrate, 2... Internal circuit area, 3.9.
...Bonding pad, 4...Metal wiring, 5...
Bonding wire, 6... Case internal lead, 7...
・Contact hole, 8...dummy pad.

Claims (1)

【特許請求の範囲】[Claims] 　半導体基板上に設けた素子領域と、前記素子領域に接
続された金属配線と、前記素子領域及び前記金属配線を
含む内部回路領域上に設けた最上層保護膜と、少くとも
前記最上層保護膜を含む層間絶縁膜に設けたコンタクト
ホールを介して前記金属配線と接続し且つ前記内部回路
領域の上の前記最上層保護膜上に設けたボンディングパ
ッドとを備えたことを特徴とする半導体集積回路。An element region provided on a semiconductor substrate, a metal wiring connected to the element region, a top layer protective film provided on an internal circuit area including the device region and the metal wiring, and at least the top layer protective film. a bonding pad connected to the metal wiring via a contact hole provided in an interlayer insulating film containing the above, and provided on the uppermost protective film above the internal circuit area. .
JP63077118A 1988-03-29 1988-03-29 Semiconductor integrated circuit Pending JPH01248533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63077118A JPH01248533A (en) 1988-03-29 1988-03-29 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63077118A JPH01248533A (en) 1988-03-29 1988-03-29 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH01248533A true JPH01248533A (en) 1989-10-04

Family

ID=13624876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63077118A Pending JPH01248533A (en) 1988-03-29 1988-03-29 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH01248533A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474627B1 (en) * 2000-07-05 2005-03-08 샤프 가부시키가이샤 Flexible printed circuit board, integrated circuit chip mounting flexible printed circuit board, display apparatus incorporating, integrated circuit chip mounted structure, and bonding method of integrated circuit chip mounting flexible printed circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474627B1 (en) * 2000-07-05 2005-03-08 샤프 가부시키가이샤 Flexible printed circuit board, integrated circuit chip mounting flexible printed circuit board, display apparatus incorporating, integrated circuit chip mounted structure, and bonding method of integrated circuit chip mounting flexible printed circuit board

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