JPH012486A - High efficiency code decoding device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a high-efficiency code decoding method that decodes a high-efficiency code from an encoding device that compresses and transmits the amount of image data such as a digital video signal. Regarding equipment.

[Summary of the invention]

The present invention provides a high-efficiency code decoding device in which image data is compressed by subsampling, in which the sampling phase is sequentially shifted according to the subsampling rate. This method adaptively performs either temporal interpolation or spatial interpolation for pixels thinned out by subsampling, thereby preventing resolution discontinuities between still/moving blocks and producing high-quality restored images. This is what I did to get it.

[Conventional technology]

When transmitting a digital video signal, a known method for compressing the amount of data to be transmitted compared to the original amount of data is to thin out pixels by subsampling and lower the sampling frequency. In subsampling, for example, image data is thinned out to A method has been proposed that transmits a flag (indicating whether the However, in the case of simple subsampling, when the compression rate is increased, the deterioration of the image quality of the restored image becomes noticeable. Therefore,
An encoding device that combines subsampling and a high-efficiency code adapted to a dynamic range has been proposed.

That is, the applicant of the present application determined the dynamic range defined by the maximum and minimum values of a plurality of pixels included in a two-dimensional block, as described in Japanese Patent Application No. 59-266407, and We have proposed a high-efficiency encoding device that performs range-adaptive encoding. Furthermore, as described in Japanese Patent Application No. 60-232789, a high-efficiency encoding device performs encoding adapted to a dynamic range with respect to a three-dimensional block formed from pixels in areas included in each of a plurality of frames. is proposed.

Furthermore, as described in Japanese Patent Application No. 60-268817, there is a variable length encoding method in which the number of bits changes depending on the dynamic range so that the maximum distortion caused when quantization is constant. Proposed.

The encoding method adapted to these dynamic ranges is
All pixel data within a block was always encoded, regardless of the movement of the block's image.

However, when there is no movement in the image,
As described in the '840 specification, the compression ratio can be further increased by so-called drop-proof processing in which data in only one area within a block is encoded.

Furthermore, by using an encoding method that adapts to the dynamic range of the three-dimensional block described above and combining it with a high-efficiency encoding device that performs filtering according to the presence or absence of motion, the compression rate can be further increased and A patent application filed in 1986-17 was developed as a highly efficient encoding device that can restore images well.
What is described in the specification of No. 9483 has been proposed.

In the high-efficiency encoding device shown in this specification, when subsampling is used to reduce the sampling frequency, thinned out pixels in a still block can be interpolated favorably on the receiving side. , the subsampling phase is sequentially shifted. For example, the phase of subsampling is inverted between one and the other of two three-dimensional blocks occupying the same position, and the subsampling is performed so that a complementary relationship is established. On the receiving side, if both the current block and the previous block are determined to be stationary blocks by motion determination for each block, the pixels thinned out by subsampling are pixels that actually exist in the previous block. will be replaced by the data of Therefore, there is almost no deterioration in image quality in the still blocks.

Also, if at least one of the previous block and the current block is determined to be a motion block, the data of the previous block cannot be used.For example, if a field uses data from pixels in the same field. The inner sleeve is made. As the inner field spacing, the average value of two pixels located on the left and right sides of the pixel to be interpolated, or the average value of four pixels located on the upper, lower, left and right sides of the pixel to be interpolated is used.

[Problem that the invention seeks to solve]

However, in the above-mentioned high-efficiency encoding device,
When interpolating pixels thinned out by subsampling, different interpolation processing is performed adaptively for each block based on motion determination for each block, resulting in discontinuity in resolution between still blocks and moving blocks. That is, there is a problem in that the image quality of motion blocks is noticeably degraded due to the unbalanced difference in resolution.

Therefore, an object of the present invention is to provide a high-efficiency code decoding device that can prevent resolution discontinuity between still blocks and moving blocks and obtain better restored images.

[Means for solving problems]

In this invention, a digital image signal is divided into blocks each consisting of n areas belonging to each of n temporally consecutive frames, and the number of pixels in each block is set to (1/m),
In a high-efficiency code decoding device that encodes a digital image signal by subsampling so that the phase of subsampling is sequentially shifted for m blocks, the periphery of pixels thinned out by subsampling Means 32° 3B, 39 for determining motion for each pixel based on pixel data and forming a determination output
．． 41, and temporal interpolation means 23, 24 for extracting data of different sub-sampling phases that are temporally close to the thinned out pixels and located at the same position on the screen. -28, spatial interpolation means 44 to 53 that calculate interpolated values based on data of peripheral pixels of the thinned out pixel, and temporal interpolation means or spatial interpolation means according to the output of the motion determination means. A selection means 43 is provided for outputting either one of the outputs as interpolated data of the thinned out pixels.

[Effect]

In the motion adaptive interpolation circuit 16, the absolute value of the difference between pixels at the same position between two frames with the same subsampling phase is calculated, and the absolute value of the difference between the pixels obtained is calculated based on the interpolation point. Those corresponding to four pixels adjacent in the horizontal and vertical directions are extracted by a group of delay circuits, and the largest absolute value of the four obtained differences is selected.

The maximum absolute value of the difference is compared with a predetermined threshold,
If the maximum value is larger than the threshold value, it is determined to be a moving pixel, and if the maximum value is smaller than the threshold value, it is determined to be a stationary pixel, which corresponds to the t measurement result. output is formed. Based on this determination output, temporal interpolation is performed on pixels determined to be static pixels, and
The spatial interpolation force □(
For example, if the time direction interpolation is done 4, then
Pixel data of a previous frame at a different subsampling phase corresponding to the interpolation point on the screen is output as interpolation data. When intra-spatial interpolation is performed, for example, the average value of data of 4' horizontally and vertically adjacent pixels in the same field centered on the interpolation point is output as interpolated data.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. This description is given in the following order.
□ a. Configuration of the transmitting side, configuration of the receiving side. C6. Explanation of motion adaptive interpolation' processing. a. Configuration of the transmitting side. This is a conflict that shows the composition of the world as a whole.

In FIG. 2, 1 is an input terminal, and a predetermined sampling frequency f, for example, is applied to this input terminal 1.
A digital video signal sampled at s and quantized at 8 points is provided as an input signal. - the input digital video signal from the input terminal l is supplied to the blocking circuit 2;

The blocking circuit 2 rearranges the order of the sequentially supplied sample data and generates data units existing within a predetermined three-dimensional screen area, that is, a data string in the order of blocks, which is a processing unit for high-efficiency encoding. For example, in the blocking circuit 2, one three-dimensional block (for example, 4
line x 4 pixels x 2 frames = 32 pixels). The output of the blocking circuit 2 is the spatial sub-sampling circuit 3.
supplied to

The spatial sub-sampling circuit 3 has the original sampling frequency fs, for example, '7Qfs, which is the frequency of
The pixels of each block are sampled using a sampling pulse whose phase is inverted every two frames, and the amount of data is compressed to 〃. That is, in the spatial sub-sampling circuit 3, a quincunx-shaped sampling pattern is formed in which a complementary relationship is established between consecutive blocks forming the same screen area.

For example, FIG. 4 shows a quincunx-shaped sampling pattern formed in the spatial sub-sampling circuit 3 as a whole, and the pattern is divided into the same area on consecutive frames shown in FIG. It is shown using Furthermore, the fourth
In FIGS. A to D, ◯ indicates subsampled pixels, and × indicates thinned out pixels.

Further, one block N is formed from the screen area shown in FIG. 4A and the screen area shown in FIG. 4B, and one block N is formed from the screen area shown in FIG. 4C and the screen area shown in FIG. (
N+1) is formed. In FIG. 4, solid lines indicate the four lines of the odd field, and broken lines indicate the lines of the even field.

As shown in Fig. 4, the pixels subsampled every two frames (one block) have a difference of one pixel, and the pixels in block N and the pixels in block (N
+1) pixels, it is possible to synthesize a frame with the original number of pixels. Spatial subsample circuit 3
The output of is supplied to the motion adaptive drop protection circuit 4.

The motion adaptive detection circuit 4 calculates the difference between pixels at the same position between two frames in a block, and performs motion detection by comparing the maximum absolute value of the difference with a predetermined threshold. Based on the motion detection results, the blocks with little motion are subjected to drop prevention processing.

That is, the maximum value of the absolute value of the difference between pixels at the same position is compared with a predetermined threshold value, and if the maximum value of the absolute value of the difference is greater than the threshold value, it is determined that the block is a motion block. If the maximum absolute value of the difference is smaller than the threshold,
It is determined to be a stationary block. Regarding stationary blocks,
An average value is calculated between pixels at the same position in frames within a block, and this inter-frame average value is output as a substitute for the sub-sample data forming the block.

The output of the motion adaptive drop protection circuit 4 is supplied to the encoder circuit 5, and a determination code corresponding to the motion detection determination result generated in the process of motion adaptive drop protection processing is supplied to the encoder circuit 5 and the framing circuit 6. Ru.

The encoder circuit 5 performs encoding by varying the number of bits in a manner adapted to the dynamic range based on the dynamic range of each block. For example, encoder circuit 5
, the maximum and minimum values of the data in the sequentially supplied blocks are detected, and the minimum value is subtracted from the maximum value to calculate the dynamic range -0.
The minimum value is subtracted from the data value within the block, and the data after the minimum value has been removed is quantized with the number of bits depending on the dynamic range to form a code signal with a compressed number of bits. The dynamic range, minimum value, and code signal obtained by the processing of the encoder circuit 5 are each supplied to a framing circuit 6.

In the framing circuit 6, an error correction code is added to the data portion consisting of the motion detection determination code from the motion adaptive reduction circuit 4 and the dynamic range, minimum value, and code signal from the encoder circuit 5, and these are converted into serial data. The data is converted into transmission data, and this transmission data is taken out from the output terminal 7.

b. Configuration of the receiving side FIG. 3 shows the overall configuration of the receiving side (in the case of a video tape recorder, the reproducing side) of the present invention.

In FIG. 3, reference numeral 11 indicates an input terminal for receiving data.

The received data from the input terminal 11 is sent to the frame decomposition circuit 12.
supplied to In the frame decomposition circuit 12, error correction is performed on the received data, and a motion detection determination code, dynamic range, minimum value, and code signal are separated. The motion detection judgment code separated in the frame decomposition circuit 12 is transmitted to the decoder circuit 1.
3. The signal is supplied to each of the frame loss restoration circuits 14.

The decoder circuit 13 includes, in the frame decomposition circuit 12,
The code signal is decoded based on the separated dynamic range to form data from which the minimum value has been removed, and the minimum value is added to the value of the data from which the minimum value has been removed to restore the data. The output of the decoder circuit 13 is supplied to a frame loss restoration circuit 14.

In the frame drop restoration circuit 14, restoration processing is performed on a still block that has been subjected to frame dropping processing on the transmitting side.For example, restoration processing is performed on a static block based on a motion detection determination code, and the A block with the original number of pixels is restored by reading sub-sample data averaged between frames within the block twice at a predetermined timing. The output of the dropped frame restoration circuit 14 is supplied to the block decomposition circuit 15.

The block decomposition circuit 15 converts data in block order into a data string in scanning order. In other words, in the block decomposition circuit 15, the order of the sub-sample data is the same as that in the scanning of the television signal. The output of the block decomposition circuit 15 is supplied to a motion adaptive interpolation circuit 16.

The motion adaptive interpolation circuit 16 performs motion detection for each pixel, adaptively performs either temporal interpolation or spatial interpolation based on the motion detection determination result, and performs interpolation in the temporal direction or spatial interpolation based on the judgment result of the motion detection. The subtracted pixels are restored to reproduce a frame with the original number of pixels.

For example, the absolute value of the difference between pixels at the same position between two frames with the same subsampling phase is calculated, and the absolute value of the pixel difference obtained is calculated in the horizontal and vertical directions with the interpolation point as the center. Those corresponding to the four pixels adjacent to are extracted by the delay circuit group, and the maximum one among the four obtained absolute values of differences is selected, and the maximum absolute value of the L difference and a predetermined value are selected. Motion detection is performed by comparing the pixel with a threshold value. For example, if the maximum value is higher than the threshold value, it is determined to be a moving pixel, and if the maximum value is smaller than the threshold value, it is determined that the pixel is moving. , the pixel is determined to be a still pixel and an output corresponding to the determination result is generated.'1 Based on this determination output, temporal interpolation is performed on the pixel that can be determined to be a still pixel, and the pixel is determined to be a moving pixel. When interpolation in the t-space is performed on pixels in the 0-time direction, for example, pixel data of the previous frame at a different subsampling phase corresponding to the interpolation point on the screen is output as interpolated data. In addition, when spatial interpolation is performed, for example, the average value of data of four horizontally and vertically adjacent pixels in the same field centered on the interpolation point is output as interpolated data. .
' A data string for the original number of pixels is reproduced in the motion adaptive interpolation circuit 16, and the output of the motion adaptive interpolation circuit 16 is taken out from the output terminal 17. Therefore, a digital video signal sampled at a predetermined sampling frequency rS and quantized to 8 bits is obtained from the output terminal near 17.

C'', Description of Motion Adaptive Interpolation Processing FIG.
Sub-sample data from the block decomposition circuit 15 is supplied as an input signal to the terminal indicated by . Furthermore, the first
In the figure, 31.35.37,36 expressed in SD
, 44.47° 48.49 are each l sample period (
A sample delay circuit having a delay amount of 1/f3),
Each of the numbers 33, 34, 45, and 46 expressed in LD is 1
This is a line delay circuit having a horizontal period of delay.

An input digital signal from the input terminal 21 is supplied to three frame memories 22, 23, 24 connected in series, and also to one input terminal 26a of the switch circuit 26. Outputs delayed by one frame period in the frame memory 22 are supplied to a subtracter 29, a line delay circuit 45, and a sample delay circuit 44, respectively. Also, the frame memory 23 is delayed by two frame periods with respect to the input signal.
is supplied to the other input terminal 26b of the switch circuit 26, and one input terminal 26b of the switch circuit 28.
8a. Further, the output of the frame memory 24 delayed by three frame periods with respect to the input signal is supplied to the other input terminal 28b of the switch circuit 28.

The switch circuit 26 is supplied with a clock signal of two frame periods from the terminal 25, and the signal from the input terminal 21 is selected in the first half of one cycle, and the signal from the frame memory 23 is selected in the second half of one cycle. output is selected. The output of the switch circuit 26 is supplied to a subtracter 29. In the subtracter 29 , subtraction processing is performed between the output of the switch circuit 29 and the output of the frame memory 22 , and the subtracted output is supplied to the absolute value conversion circuit 30 . In the absolute value conversion circuit 30, the output of the subtracter 29 is converted into an absolute value. Therefore, the absolute value conversion circuit 30 sequentially outputs the absolute values of the differences between pixels at the same position between two frames whose subsampling phases match. This absolute value output is supplied to each of the sample delay circuit 31 and line delay circuit 33.

Further, the switch circuit 28 is supplied with a clock signal of two frame cycles from the terminal 27, and the output of the frame memory 23 is selected in the first half of one cycle, and the output of the frame memory 23 is selected in the first half of one cycle.
The output of the frame memory 24 is selected in the latter half of the cycle. Therefore, the switch circuit 28 outputs pixel data of the same frame twice every l frames.

The output of the switch circuit 28 is a delay circuit 42 for time adjustment.
The signal is supplied to one input terminal 43a of the switch 43 via.

The output of the absolute value conversion circuit 30 is supplied to one input terminal of the selection circuit 32 via a sample delay circuit 31, and is also supplied to the other input terminal of the selection circuit 32 via a line delay circuit 33. Further, the output of the absolute value conversion circuit 30 is output from the line delay circuit 33 and the sample delay circuit 35, 36.
is supplied to one input terminal of the selection circuit 38 via the line delay circuits 33 and 44 and the sample delay circuit 37 to the other input terminal of the selection circuit 38. That is, the selection circuits 32 and 38 are supplied with the absolute values of the differences corresponding to four pixels adjacent in the horizontal and vertical directions with the interpolation point as the center.

Each of the selection circuits 32, 38 and 39 is configured to compare the values of the supplied data and output the larger value, and each of the outputs of the selection circuits 32 and 38 is connected to the selection circuit 3.
9. In the selection circuit 39, the one that is larger is selected, and the data MAX which is the largest among the four absolute values is outputted from the selection circuit 39.
The output of is supplied to the comparison circuit 41.

The comparison circuit 41 is supplied with predetermined threshold data TH from the terminal 40, compares the threshold data TH with the maximum value data MAX, and sends the comparison output as a control signal to the control terminal of the switch circuit 43. Supplied. That is, by comparing the maximum absolute value of the difference with a predetermined threshold value, motion detection for the interpolation point is performed, and an output corresponding to the detection result is generated. For example, threshold data TH
If the maximum value data MAX is smaller, it is determined that the pixel is a still pixel and a low level output is generated.
When the maximum value data MAX is larger than the threshold data TH, it is determined that the pixel is a moving pixel, and a high level output is generated.

On the other hand, the output of the frame memory 22 is output to the sample delay circuit 4.
4 to the adder 50, and also to the adder 50 via the line delay circuit 45. Further, the output of the frame memory 22 is supplied to the adder 52 via the line delay circuit 45 and the sample delay circuit 47, 49, and is also supplied to the adder 52 via the line delay circuit 45, 46 and the sample delay circuit 48. be done. The output of adder 50 is supplied to adder 51, and the output of adder 52 is supplied to adder 51. The output of the adder 51 is sent to the A division circuit 5
3, and the output of the adder 51 is set to 2. Therefore, the A division circuit 53 outputs the average value of data of horizontally and vertically adjacent pixels in the same field centered on the interpolation point. The output of the A division circuit 53 is supplied to the other input terminal 43b of the switch circuit 43. Also,
The output of the frame memory 22 is supplied to the other input terminal 54b of the switch circuit 54 via a line delay circuit 45 and a sample delay circuit 47.

The switch circuit 43 selectively outputs one of the signals supplied to the input terminals 43a and 43b based on the control signal from the comparison circuit 41.

In other words, in the case of a still pixel for which the control signal from the comparator circuit 41 is at a low level, the input terminal 43a is selected and the data of the pixel of the previous frame with a different subsampling phase corresponding to the interpolation point is output. Ru. Furthermore, in the case of a moving pixel for which the control signal from the comparison circuit 41 is at a high level, the input terminal 43b is selected, and four pixels adjacent in the horizontal and vertical directions in the same field centered on the interpolation point are selected. The average value of the data is output. Switch times! a
The interpolated output from 43 is supplied to one input terminal 54 a &i of a switch circuit 54 .

The switch 54 receives the sampling frequency f from a terminal 55.
A sampling pulse of s is supplied as a clock signal. In the switch circuit 54, the signals supplied to the input terminals 54a and 54b are alternately selected every l sample period. In other words, data and interpolated data are alternately selected by the switch circuit 54. The output signal of switch circuit 54 is taken out from output terminal 56.

The operation of the motion adaptive interpolation circuit 16 described above will be explained in more detail with reference to FIG. The data of the screen area shown in FIG. 4A is stored in the frame memory 24, the data of the screen area wi shown in FIG. 4B is stored in the frame memory 23,
The data in the screen area shown in FIG. 4C is stored in the frame memory 22.
Assume that it is stored in . Also, in the fourth diagram, the value of one data of the pixel indicated by 65, 66, 67, 68 is a.

b, c, d, and in Figure 4 C? 5.76°77.
The data values of the pixel indicated by 78 are e and f.

Let them be g and h. □ □ At the timing when the thinned out pixels indicated by 61 in the fourth diagram are supplied to the input terminal 21, the frame memory 2
The data of pixel 63 (shown in FIG. 4B) is output from frame memory 24, and the data of pixel 64 (shown in FIG. 4A) is output from frame memory 24.
data is output.

At this time, since the switch circuit 26 is controlled to select the input terminal 26a side, the sample delay circuit 3
1 to 1a-el is output, the line delay circuit 33 outputs Ib-fl, and the sample delay circuit 36 outputs Ic.
-gl is output, and 1d-h is output from the sample delay circuit 31.
l is output.

Selection circuit 32.38. ．． 39, the absolute value 1a-a of the difference between pixels at the same position 1. l b-f I
.

The maximum value among Ic-gl and Id-hl is selected, and the selection circuit 39 outputs maximum value data MAX. In the comparison circuit 41, the threshold value data TH and the maximum value data MAX are compared, and motion detection is performed for the thinned out pixels 81 (shown in FIG. 4C) serving as interpolation points.

Also, at this time, the sample delay circuit 44 outputs the data e of the pixel 75, and the line delay circuit 45 outputs the data e of the pixel 75.
Data f of pixel 77 is output from the sample delay circuit 49, and data h of pixel 78 is output from the sample delay circuit 48. Therefore, from the × division circuit 53, ! 4 (e+f+g+h) is output.

Furthermore, at this time, since the switch circuit 28 is controlled to select the input terminal 28a side, the output of the frame memory 23 is supplied to the delay circuit 42, and from the delay circuit 42, the output of the pixel 73 (see FIG. The data shown in B) is output.

When the comparison circuit 41 determines that the pixel 81 is a still pixel (TH≧MAX), the switch circuit 43 is controlled to select the input terminal 43a side. Therefore, the switch circuit 43 outputs the data of the pixel 73 from the delay circuit 42 as interpolated data of the pixel 81. Also,
If the comparison circuit 41 determines that the pixel 81 is a moving pixel (TH<MAX), the switch circuit 43 is controlled to select the input terminal 43b. Therefore, the switch circuit 43 outputs the average value 'A ((e+f +g+h)) of the adjacent pixels from the A division circuit 53 as interpolated data of the pixel 81.

The switch circuit 54 is controlled by a clock signal from a terminal 55 so as to select one input terminal 54a at the timing when the pixel 61 is supplied to the input terminal 21, and receives the above-mentioned interpolated data from the switch circuit 43. is taken out from the output terminal 56. Therefore, the interpolated data is inserted between the sub-sample data and output, and the original sample data sequence is restored.

Further, at the timing when the pixel indicated by 62 in the fourth diagram located next to the pixel 61 is supplied to the input terminal 21, the switch circuit 54 is connected to the other input terminal 54b.
Since the output from the sample delay circuit 47 is controlled by the clock signal from the terminal 55 to select the
That is, the data of the pixel 76 (shown in FIG. 4C) is output from the switch circuit 54.

Furthermore, after one frame period has elapsed from the timing at which the above-mentioned pixel 61 is supplied to the input terminal 21, the data of the screen area shown in FIG. 4B is stored in the frame memory 24, and the data shown in FIG. 4C is stored in the frame memory 24. The data of the screen area is stored in the frame memory 23, and the data of the screen area shown in the fourth diagram is stored in the frame memory 22.

1 from the timing when the pixel 61 is supplied to the input terminal 21
At the timing when one frame period has elapsed, the data of the pixel 63 (shown in FIG. 4B) is output from the frame memory 24.

At this time, since the switch circuit 26 is controlled to select the input terminal 26b side, the absolute value of the difference between the pixels having the same relationship as in the case described above is obtained, and the sample delay circuit 31 selects the input terminal 1a-el. is output and the line delay circuit 3
1b-fl is output from sample delay circuit 36! c-gl is output, and l is output from the sample delay circuit 31.
d-hl is output. In the selection circuits 32, 38, and 39, the absolute values of pixel differences 1a-el, 1br-r
The maximum value among I, IC-gl, and Id-hl is selected, and the selection circuit 39 outputs maximum value data MAX. In the comparison circuit 41, the threshold value data TH and the maximum value data MAX are compared, and motion detection is performed for the thinned out pixels 91 (shown in the fourth diagram) serving as interpolation points.

Also, at this time, the sample delay circuit 44 outputs the data a of the pixel 65, and the line delay circuit 45 outputs the data a of the pixel 66.
data b of pixel 67 is output from the sample delay circuit 49, and data d of pixel 68 is output from the sample delay circuit 48. Therefore, the A division circuit 53 outputs χ(a+b+c+d).

Furthermore, at this time, since the switch circuit 28 is controlled to select the input terminal 28b side, the output of the frame memory 24 is supplied to the delay circuit 42.
The data of pixel 73 (shown in FIG. 4B) is outputted from pixel 73 (shown in FIG. 4B).

When the comparison circuit 41 determines that the pixel 91 is a still pixel (TH≧MAX), the switch circuit 43 is controlled to select the input terminal 43a side. Therefore, the switch circuit 43 outputs the data of the pixel 73 from the delay circuit 42 as interpolated data of the pixel 91. Also,
In the comparison circuit 4, when the pixel 91 is determined to be a moving pixel (TH<MAX), the switch circuit 43 is controlled to select the input terminal 43b side. Therefore, the switch circuit 43 outputs the average value of the adjacent pixels from the divide-by-2 circuit 53 /, (a+b+c+d) as interpolated data of the pixel 91.

The switch circuit 55 switches one input terminal 54 at a timing one frame period after the timing when the pixel 61 is supplied to the input terminal 21, as in the case described above.
It is controlled by a clock signal from a terminal 55 to select a, and the interpolated data from the switch circuit 43 is taken out from an output terminal 56. Therefore, the interpolated data is inserted between the sub-sample data and output, and the original sample data sequence is restored.

〔Effect of the invention〕

In this invention, in the motion adaptive interpolation circuit, the absolute value of the difference between pixels at the same level between two frames with the same subsampling phase is determined, and the absolute value of the difference between the pixels obtained is interpolated. Corresponding pixels of four pixels adjacent in the horizontal and vertical directions around the point are extracted by a group of delay circuits, and the largest absolute value of the obtained four differences is selected. The maximum value of the absolute value of the difference is compared with a predetermined threshold value, and if the maximum value is larger than the threshold value, it is determined that it is a moving pixel, and a certain company determines that the maximum value is smaller than the threshold value. In this case, it is determined that the pixel is a still pixel, and an output corresponding to the determination result is generated. 'Based on this determination output, time-direction interpolation is performed for pixels determined to be static pixels, and 0-time direction interpolation is performed for pixels determined to be moving pixels by spatial interpolation. In this case, for example, pixel data of a previous frame at a different subsampling phase corresponding to the interpolation point on the screen is output as interpolation data. Further, when intra-spatial interpolation is performed, for example, the average value of data of one pixel adjacent in the horizontal and vertical directions in the same field centered on the interpolation point is output as interpolation data.

Therefore, according to the present invention, it is possible to perform motion detection on a pixel-by-pixel basis and to adaptively perform interpolation processing for each interpolation point based on the detection results. This prevents the discontinuity in resolution that has occurred between the two images, making it possible to obtain a good restored image.

[Brief explanation of drawings]

1K' is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of the transmission δ side of a high-efficiency encoding device to which this invention is applied, and FIG. 3 is a block diagram of a high-efficiency encoder to which this invention is applied. FIG. 4 is a block diagram of the receiving side of the encoding device.
It is a route map used to explain the operation of the example. Explanation of main symbols in the drawings 21: Sub-sample data supply terminal, 22゜23.
247 frame memory, 26.2B, 43.54:
Switch circuit, 29: Subtractor, 30: Absolute value conversion circuit, 31, 35.37.36°44.47.48.4
9: Sample delay circuit, 32.38.39: Selection circuit,
41; Comparison circuit, 33. 34, 45, 46: Line delay circuit, 42: Delay circuit for time direction interpolation, 50, 5
1゜52: Adder, 53: A division circuit, 56: Output terminal. Agent Patent Attorney Masaaki Sugiura Diagram 2 Receiving System Diagram 3

Claims (1)

[Scope of Claims] A digital image signal is divided into blocks each consisting of n areas belonging to each of n temporally consecutive frames, and the number of pixels in each block is (1/m), and m In a high-efficiency code decoding device that encodes the digital image signal by subsampling so that the phase of subsampling is sequentially shifted for each block, pixels surrounding the pixels thinned out by the subsampling A means for determining motion for each pixel based on the data of the pixel and forming a determination output; and a means for determining the motion of each pixel based on the data of temporal interpolation means for extracting; spatial interpolation means for calculating an interpolation value based on data of surrounding pixels of the thinned out pixel; 1. A high-efficiency code decoding device comprising: selection means for outputting either one of the outputs of the spatial interpolation means as interpolated data of the thinned out pixels.