JPH01258457A - Semiconductor integrated circuit package structure and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable the establishment of a multiplicity of external leadout connections by a method wherein a silicon package substrate useful for the construction of a multiple chip module is penetrated through by wirings from the main surface to the rear surface. CONSTITUTION:On the main surface of a silicon package substrate 1, single layer or multiple layer wirings are mounted, built of conductor or superconductor. A multiplicity of bumps 12 formed on a semiconductor integrated circuit chip 13 is connected to the mounted wirings, establishing connection for circuits in the chip 13 or for circuits between chips 13. A wiring 10a on the main surface penetrates through the silicon package substrate 1, and reaches the rear side. On the rear side, a rear side wiring 10b is provided for connection between embedded metals 9. This enables the establishment of external leadout connections on the rear side of the silicon package substrate 1. In this way, a large number of external leadout connections may be established.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to mounting of a semiconductor integrated circuit and a method of manufacturing the same, and particularly relates to a mounting structure useful for a high-speed semiconductor integrated circuit system and a method of manufacturing the same. .

[Conventional technology]

Conventionally, this type of mounting technology has been reported by AT&T Bell Labs. A technique is known in which a chip is connected to a multilayer wiring made of polyimide and a Cu thin film on the main surface of a silicon mounting board using solder bumps. In that case, wire bonding from the silicon mounting board to the outside is used from the periphery of the silicon mounting board (87Isscc Dig Technicl Pa.
pers, PP, 224-225°H, J, Levi
Stein et al., “Muliti-
chip Packaging Technology
for VLS I-Based System")a [Problems to be Solved by the Invention] In the conventional mounting technology described above, when drawing out the wiring of the silicon mounting board to the outside, connections are only provided at the peripheral part of the silicon mounting board. , it has the following drawbacks.

(1) Even though the wiring on the silicon mounting board uses Cu, which has high conductivity, it is a thin film with a thickness of about 2 μm, so even if the wiring width is as wide as 10 μm, the peripheral The resistance of wiring to the terminal is large, which is inconvenient for power supply in high-speed applications.

(2) In addition, in order to provide all connections on the periphery of the silicon mounting board, power supply wiring and signal wiring are placed in parallel.
Because of the unavoidable placement, parasitic phenomena such as delta-one noise between wirings are likely to occur.

Furthermore, this kind of trouble becomes more noticeable as the speed increases, and overcoming it will become an increasingly important technical issue in the future.

[Means to solve the problem]

The mounting structure according to the present invention has low-resistance wiring that penetrates the main surface side and the back side of the silicon mounting board, and can be drawn out from the silicon mounting board only from the peripheral part on the main surface side. Rather, it has a structure in which it can also be taken out from the back side via the above-mentioned penetrating low-resistance wiring. As one useful embodiment of the mounting structure according to the present invention, connection terminals on the periphery of the silicon mounting board are used as input/output signal terminals, and connection terminals provided on the back side are used as power supply terminals. There is. According to this, since the signal wiring is parallel to the main surface, and the power supply wiring is perpendicular to the main surface, interference between the two systems is significantly reduced, and troubles due to parasitic phenomena between the wirings are eliminated. Significantly improved.

The present invention has wiring that penetrates between the main surface side and the back side of a silicon mounting board, and using the through wiring, a part of the wiring is taken out to the back side of the silicon mounting board, and a part of the wiring is taken out to the back side of the silicon mounting board. It is possible to connect between wires with . Furthermore, it is possible to provide terminals for external connection on the wiring on the back side.

〔Example〕

The present invention will be described below based on Examples.

FIG. 1 is a sectional view showing a mounting structure according to an embodiment of the present invention, and FIGS. 2(a) to 2(g) are sectional views showing a manufacturing method thereof.

Figure 1 shows the following points. Thickness 200~400μ
An interlayer insulating film 11 with a thickness of 1 to 5 μm and a conductor with a thickness of 0.5 to 3 μm, or
The wiring 10a made of superconductor constitutes a single-layer or multilayer mounting wiring, and a plurality of bumps 12 formed on the semiconductor integrated circuit chip 13 are connected to the mounting wiring, and the bumps 12 formed on the semiconductor integrated circuit chip 13 are connected to each other between circuits within the chip or between the chips. Connects the circuit electrically. The wiring 10a on the main surface side is partially routed to the back surface by a buried metal 9 formed by the manufacturing method according to the present invention, which penetrates the silicon mounting substrate 1 from the main surface to the back surface. Backside wiring 10b for interconnecting the embedded metals 9 is provided on the backside.

FIG. 2 shows a manufacturing method for manufacturing the mounting structure shown in FIG. 1 as follows.

First, in the cross-sectional view shown in FIG. 2(a), a silicon mounting substrate 1 is a silicon single crystal product with a thickness of 200 to 400 μm and the main surface is the (110) plane, and a mask material 2 is applied to the main surface and back surface. This shows that a pattern has been formed on the mask material 2 on the main surface.

Specifically, as the mask material 2, a 5in2 film with a thickness of 0.5 to 2 μm formed by a thermal oxidation method was used.

The pattern on the main surface side was formed using a photolithography method (the back side was protected), and the pattern was a square or rectangle with a side of 10 μm to 100 μm, and the direction was determined taking into account the crystal axis. It is formed by

In FIG. 2(b), a hole 3 penetrating the silicon mounting substrate 1 is formed by anisotropic etching using a KOH solution, a hydrazine solution, or the like as an etching solution. The penetrating hole 3 has a square or rectangular shape depending on the pattern formed in the mask material 2. The ratio of the depth of the hole to the side (in the case of a rectangle, the short side) can easily be about 1:20 or more by optimizing the etching solution composition, temperature, and mask material.

Therefore, even if the silicon mounting board 1 has a thickness of 400 μm, processing is possible as long as the side size of the through hole 301 is 20 μm or more. Further, the penetrating hole 3 is a hole perpendicular to the main surface, which is unique to anisotropic etching. In the embodiment, the number of holes to be formed is 1,000 to 3,000.

FIG. 2(c) shows a state in which after the mask material 2 is removed, an insulating film 4 is newly formed on the silicon mounting substrate 1. Specifically, the insulating film 4 has a thickness of 1 to 1 by thermal oxidation method.
It is a 5iOz film with a thickness of 2 μm, and is also formed on the side surface of the hole 3 passing through it. The insulating film 4 formed on the side surface of the penetrating hole 3 is used to insulate and separate the buried metal 9 from the silicon mounting substrate 1 when the buried metal 9 is formed in the penetrating hole 3 later. Provided for.

FIG. 2(d) next shows a state in which the plating electrode 5 is adhered to the main surface side. An insulating protective film 6 is formed on the opposite side of the plating electrode 5 to prevent plating current from flowing. In the case of the example, specifically, a copper electrode with a thickness of 1 to 5 mm was used as the plating electrode 5, and a Teflon coat film was used as the insulating protective film 6. The size of the plating electrode 5 was slightly larger than that of the silicon mounting board 1, and in this example, the plating electrode 5 was bonded to the silicon mounting board 1 using electron wax. The bonding method is not limited to the method described in the embodiments, and for example, it may be bonded by chucking on a machine using a jig or by chemical bonding with a thin film formed on the main surface of the silicon mounting substrate 1. Adhesion may also be performed using a reaction.

A conductive thin film 7. and a conductive thin film 8 are formed. In the case of this embodiment, the conductive thin film 7 is a 0Cr vapor-deposited film with a thickness of about 1000, and the conductive thin film 8 is 5[)0 to 10
A Ni vapor-deposited film of 00 people was used. The main role of the conductive thin film 7 and the conductive thin film 8 is to provide the through hole 3 as described later.
Second, after the embedded metal 9 is formed by plating, an interface with weak adhesion is formed so that it can be easily peeled off when the plating electrode 5 is removed. Of course, there is no need to stick to the one of this embodiment as long as it is suitable for the purpose. For example, a solder layer such as Sn and PB may be formed, softened by raising the temperature, and then peeled off.

Furthermore, it is known that if metal oxide is formed between two films, both films tend to peel off, but this property may be actively used.

FIG. 2(e) shows a state in which an embedded metal 9 is formed in the penetrating hole 3 (not shown in the figure) by a plating method. In this example, the embedded metal 9 was formed by a copper plating method. The embedded metal 9 need not be limited to copper as in this embodiment, but may be a single layer metal such as gold or nickel, or may be a multilayer metal combining these metals.

FIG. 2(f) shows a state in which the main surface side and the back surface side are finished flat after the plating electrode 5 is removed.

In the case of the example, the flattening process was performed by a polishing method. In this case as well, the flattening process is not limited to the example described, and other methods such as an etch-back method may be used. In addition, if the insulating film 4 on the main surface side or the back side is damaged in the planarization process, the insulating film 4 should be re-formed at a low temperature by plasma CVD, photo-CVD, etc., or Alternatively, an insulating resin film such as polyimide may be formed.

FIG. 2(g) shows that after forming wiring 10a and wiring 10b for mounting on the main surface side and back side of the silicon mounting board 1, a semiconductor integrated circuit is formed using bumps 12 by the phase-down bonding method. The chip 13 is connected and the completed state is shown. In the case of this embodiment, the mounting wiring 1
0a and 10b have a thickness of 1 to 3 μm and a width of 5 to 30 μm.
Although a three-layer wiring (main surface) using a polyimide film was used as the interlayer insulating film 11 for the copper wiring of m and the interlayer insulating film 11, any wiring used in the above embodiment may be used as long as it is suitable for the purpose as wiring for mounting. It is not limited to cases. In other words, the conductor may be aluminum wiring, and the interlayer insulating film may also be CV
An insulating film formed by the D method or other plastic resin thin film may be used. Furthermore, it is also possible to use superconducting materials for the wiring, taking advantage of the property that the resistance decreases significantly at low temperatures.

In the case of this embodiment, the semiconductor integrated circuit chip 13 is 15
A VLSI chip with a size of 15 mm x 15 mm was used, and the bumps 12 were 5n-Pb solder bumps. The size of the bump 12 is approximately 100 μmφ, and the number of bumps is:
The number is 500 to 1000. It is clear from the gist of the invention that these points are not limited to this embodiment as long as they suit the purpose.

FIG. 3 is a sectional view showing another embodiment of the mounting structure according to the present invention, and FIGS. 4(a) to 4(d) are sectional views showing a manufacturing method thereof. FIG. 5 is a cross-sectional view for explaining mounting manufacturing according to the present invention.

The sectional view of FIG. 3 shows the following points. That is,
As in FIG. 1, a multilayer wiring layer consisting of wiring 10a made of a conductor or superconductor and an interlayer insulating film 11 is formed on the main surface side of the silicon mounting board l, and bumps 12 are formed on the main surface side of the silicon mounting substrate l.
As a result, the semiconductor integrated circuit chips 13 are connected, and the intra-chip circuits and inter-chip circuits are electrically connected. A portion of the wiring 10a is connected to the back surface side by a buried metal 9 that penetrates the silicon mounting board 1 from the main surface to the back surface. A connection bump 14 is provided to electrically connect to the wiring 10b on the back side and is drawn out to the outside. Furthermore, wiring 1 is also provided in the peripheral area of the silicon mounting board 1.
A peripheral connection terminal 17 is provided for electrical connection to 0a, and is also led out from there.

There is one very useful use of the implementation structure of FIG. That is, power is supplied to the semiconductor integrated circuit chip 13 from the connection bumps 14 on the back side of the silicon mounting board 1, and signals are input and output through the peripheral connection terminals 17 on the main surface. In high-speed applications, apart from the cooling aspect, it can be said that the speed performance is determined by the power supply capacity.

Compared to the conventional technique in which power is supplied from the periphery of the silicon mounting substrate 1, the power supply in the mounting structure according to the present invention is advantageous in the following respects. First, the cross-sectional area of the power supply conductor is typically 50 μm in length x 50 μm in width, and the typical thickness is 2 μm.

It is approximately 50 times larger than the width of 20 μm, and the length of the power supply conductor is approximately equal to the thickness of the silicon mounting board 1, and is uniform and typically about 0.3fi, whereas power is supplied from the periphery. If so, the length of the power supply conductor varies, and the longest length is the distance from the periphery to the center of the silicon mounting board l, which is typically about 30 mm. Although the conductivity of the conductor varies depending on the material used and the manufacturing method, it is thought that there is not much difference in the conductivity between the wiring 10a and the embedded metal 9. From this comparison, it is clear that
The embedded metal 9 has extremely low resistance and is extremely useful for power supply applications. Further, as a use of the mounting structure according to the present invention, input/output signals may be separated from the power supply system and transmitted from the peripheral connection terminal 17 on the main surface. According to this method, it is possible to reduce the influence of inter-wire noise from the power supply system, which is far away from the power supply terminal and causes problems in high-speed regions.

The mounting structure shown in FIG. 3 is manufactured by the manufacturing method shown in FIGS. 4(a) to 4(ig). First, Figure 4(a)-(
c) is the same as explained in FIGS. 2(a) to (e). FIG. 4(f) shows a state in which, unlike the case shown in FIG. 2, the back surface side has been flattened while the plating electrode 5 remains adhered. In this example, the flattening process was performed using a polishing method, but the method is not limited to this example, and other methods such as an etch-back method can also be used as long as it suits the purpose. The state in which the bumper 4 for use is formed is shown.
The plating here may be performed using the same metal as the embedded metal 9, or may be performed using a different metal. Further, the entire connection bump 14 does not need to be formed of the same metal, and may have a multilayer metal structure, for example, with copper plating up to the middle and gold plating at the end. In this example, gold plating was performed as additional plating, and gold bumps with a height of 5 to 15 μm were formed as connection bumps 4.

FIG. 4(f) shows that after removing the plating electrode 5 adhered to the main surface side and flattening the main surface side, the conductor or
A multilayer wiring is formed by a superconductor wiring 10a and an interlayer insulating film 11, and then, as in the case of FIG.
A semiconductor integrated circuit chip 13 is connected to a silicon mounting board 1 with bumps 12 by a face-down bonding method, and the silicon mounting board 1 is formed on a board 16 by a printing method or the like using the connection bumps 14 on the back side. It shows that it is completed by connecting to metal 15. here,
The above-described method for connecting the connection bumps 14 on the back surface to the outside is described as an example; the state after the plating electrode 5 is removed and the main surface is flattened is shown. As shown in FIG. 5, a large number of embedded metals 9 are provided, typically in the form of lattice points.

〔Effect of the invention〕

As explained above, the present invention provides wiring that penetrates the main surface side and the back side of a silicon mounting board useful for multi-chip module applications, thereby allowing external extraction and connection to the back side of the silicon mounting board. is possible. For this purpose, a large number of external connection connections are possible. For example, by forming the above-mentioned through-hole wiring on a silicon mounting board as in the example, the cross-sectional area ratio is increased approximately 50 times, and the wiring length ratio is increased by approximately 50 times compared to the conventional wiring parallel to the main surface side. It is reduced to about 1/100. The worst conductivity is about 50
%, but even in that case, the wiring resistance is reduced to about 1/2500 of that of the conventional method. It is extremely useful to supply power to a semiconductor integrated circuit chip connected to the main surface side of a silicon-mounted substrate using this through wiring having a low and uniform resistance.

In addition, the input/output signals can be transmitted from the periphery of the main surface as in the past, but unlike the conventional technology,
By using the through wiring, the power supply wiring can be prevented from being routed to the periphery of the silicon mounting board, so the noise level is low and good transmission is possible.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an embodiment of the mounting structure according to the present invention, FIGS. 2(a) to (g) are cross-sectional views showing an example of the manufacturing method according to the present invention, and FIG. FIG. 4 (a) to (#,) are sectional views showing other embodiments of the manufacturing method of the present invention, and FIG. 5 is a cross-sectional view showing another embodiment of the mounting structure. FIG. 1... Silicon mounting board, 2... Mask film, 3... Penetrating hole, 4... Insulating film, 5... Plating electrode, 6... Insulating protective film, 7... Conductive thin film, 8... Conductive thin film, 9... Embedded metal, 10... ...
・Wiring (conductor or superconductor) (10a...
Main surface side, 10b... Back side), 11...
...Interlayer insulating film, 12...Bump, 13...
...Semiconductor integrated circuit chip, 14...Connection bump (back side), 15...Metal, 16...
... Board, 17 ... Peripheral connection terminal. Agent Patent Attorney Susumu Uchihara $2 2nd floor 4th concave M4 figure, Izumi 4th figure

Claims (5)

[Claims] (1) In a mounting structure in which a plurality of bumps are formed on a semiconductor integrated circuit chip and connected to wiring formed of a conductor or superconductor on a silicon mounting board by a face-down method, the wiring on the silicon mounting board side is A mounting structure for a semiconductor integrated circuit, characterized in that one part is formed through the silicon mounting substrate to the back side of the substrate. (2) Provide connection terminals on the back side of the silicon mounting board and use them as power supply terminals, and provide external connection terminals drawn out with wires around the main surface side of the silicon mounting board and connect them. The semiconductor integrated circuit mounting structure according to claim 1, wherein the semiconductor integrated circuit mounting structure is used as an output signal terminal. (3) A semiconductor integrated circuit mounting structure according to claim 2, characterized in that external connection bumps are formed in the penetrating portion of the wiring that penetrates the back side of the silicon mounting board. (4) A step of forming a hole penetrating the substrate by an anisotropic etching method using a silicon single crystal with a (110) plane as a main surface as a silicon mounting board material, and a step of thermally oxidizing the silicon single crystal. 2. The method of manufacturing a semiconductor integrated circuit mounting structure according to claim 1, further comprising the steps of: covering the through hole with an insulating film; and filling the through hole with metal. (5) a step of adhering a plating electrode with insulation protection on the main surface side of the silicon mounting board, and a step of filling the through hole with metal using a plating method; 3. The method of manufacturing a semiconductor integrated circuit mounting structure according to claim 2, further comprising the step of adding plating to the back side of the semiconductor integrated circuit to form bumps.