JPH0126100B2 - - Google Patents
Info
- Publication number
- JPH0126100B2 JPH0126100B2 JP58126528A JP12652883A JPH0126100B2 JP H0126100 B2 JPH0126100 B2 JP H0126100B2 JP 58126528 A JP58126528 A JP 58126528A JP 12652883 A JP12652883 A JP 12652883A JP H0126100 B2 JPH0126100 B2 JP H0126100B2
- Authority
- JP
- Japan
- Prior art keywords
- permutation
- data
- order
- input data
- memories
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Image Input (AREA)
- Image Processing (AREA)
- Memory System (AREA)
Claims (1)
のデータと2l+1・i−j番目のデータを入れ換え
る置換P2l、相異なる置換P2lを引続き行なつて得
られる合成の置換をPn及びデータの入れ換えを
行なわない恒等置換をP0とした時に得られる総
ての置換Pkを要素としてP0から順に並べたP0、
P1、P2、………、P2o-1に対して前記手法の置換
Pkの一つを施して各置換の順番を定め、順番が
定められた置換と、2n×2nビツトで構成されたブ
ロツク内における行方向及び列方向の2nビツトの
入力データのブロツク内での行あるいは列番号と
を順に対応させて入力データの並び換えを行なう
手段と、前記並び換えを行なつた入力データを記
憶する独立に動作可能な2n個のメモリm1、m2、
………、m2oを有し、前記2n個の各メモリのアド
レス入力a0、a1、………ao-1のn本に関しては、
メモリm2l+1 1 2 A permutation P 2l that swaps the 2 l+1・i−2 l −jth data with the 2 l+1・i−j th data of all n data, and the different permutation P 2l is continued . When the resulting composite permutation is P n and the identity permutation that does not exchange data is P 0 , all the permutations P k obtained as elements are arranged in order from P 0 , P 0 ,
Substitution of the above method for P 1 , P 2 , ......, P 2o-1
One of P k is applied to determine the order of each permutation, and the permutation with the determined order and the block of input data of 2 n bits in the row direction and column direction in a block composed of 2 n × 2 n bits are performed. a means for rearranging input data by sequentially corresponding row or column numbers within the data, and 2n independently operable memories m 1 , m 2 for storing the rearranged input data. ,
......, m 2o , and for n address inputs a 0 , a 1 , ......a o-1 of each of the 2 n memories,
memory m 2l+1
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58126528A JPS6019254A (en) | 1983-07-12 | 1983-07-12 | data storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58126528A JPS6019254A (en) | 1983-07-12 | 1983-07-12 | data storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6019254A JPS6019254A (en) | 1985-01-31 |
| JPH0126100B2 true JPH0126100B2 (en) | 1989-05-22 |
Family
ID=14937430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58126528A Granted JPS6019254A (en) | 1983-07-12 | 1983-07-12 | data storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6019254A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62145382A (en) * | 1985-12-20 | 1987-06-29 | Fujitsu Ltd | Image data output device |
| JP2669311B2 (en) * | 1993-12-02 | 1997-10-27 | 日本電気株式会社 | Bitmap file access system |
-
1983
- 1983-07-12 JP JP58126528A patent/JPS6019254A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6019254A (en) | 1985-01-31 |
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