JPH01264010A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To obtain an oscillation output subject to temperature compensation by providing a reference voltage generating circuit generating a forward voltage of a diode as a reference voltage. CONSTITUTION:The reference voltage generating circuit 27 generating a forward voltage of a diode as a reference voltage is provided. The reference voltage generating circuit 27 to give a reference voltage V2 to a comparator circuit 26 consists of a PNP transistor(TR) Q36, an NPN TR Q37, a resistor 28 and a diode 29. Thus, a temperature coefficient of a forward voltage of the diode of the reference voltage generating circuit 27 is applied as a negative element of the temperature coefficient of the oscillation period to apply temperature compensation of the oscillated period. Thus, the oscillation output whose oscillation period is subject to temperature compensation is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an oscillation circuit including a charging/discharging circuit for charging and discharging a capacitor.

Prior Art No. 212I is a circuit diagram showing an example of a conventional oscillation circuit. In FIG. 1, a constant current output circuit 1 for generating a constant current 11 is a PNP transistor Ql.

Q2. Q3 and NPN) transistor Q4. It consists of Q5 and resistor 2.3. Two PNP transistors Ql, Q whose bases are connected to form a current mirror.
The emitters of these PNPs are connected to the power supply Vcc.
) - The emitter and base of PNP transistor Q3 are
PNP) - connected to the base of transistor Ql, Q2 and PNP) - collector of transistor Q2, respectively, P
NP) The collector of transistor Q3 is grounded.

Furthermore, the collector of the PNP transistor Q1 is connected to the collector of the diode-connected NPN transistor Q4, the collector of the PNP transistor Q2 is connected to the collector of the NPN transistor Q5, and the collector of the two NPN transistors Q4. The bases of Q5 are connected together. N
PN) The emitter of transistor Q4 is grounded, and NPN)
The emitter of transistor Q5 is connected to one end of resistor 3,
The other end of this resistor 3 is grounded.

N P N +- transistor Q4. There is an NPN between the base of Q5 and the power supply Vcc when the power supply Vce is turned on.
l-transistor Q4. A resistor 2 is inserted to supply a base voltage to Q5. NPN)-transistor Q5 has an emitter area ten times larger than NPN)-transistor Q4. 4 is a charging/discharging circuit for charging and discharging the capacitor 5, and includes a PNP transistor Q6. Q7 and N P N l helangistor Q8゜Q9. It consists of QIO. Two PNP transistors Q6, . Q
The emitter of 7 is connected to the power supply Vcc.

The collector of the P N P l-transistor Q6 is connected to the collector of the diode-connected NPNI-transistor Q9, and the collector of the PNPt-transistor Q7 is connected to the NPN
1 to the collectors of transistors Q10. 2
one NPNt-transistor Q9. The QIO's bases are connected to each other to form a current mirror, and their emitters are both grounded. NPN) - transistor Q
10 has an emitter area twice that of N F-' N + transistor Q9. Further, the collector of the N P N +- transistor Q8 is connected to the collector of the NPNI- transistor Q9, and the emitter of the N P N +- transistor Q8 is grounded. NPN l-transistor Q1
．． The collector of 0 is connected to one terminal of the capacitor 5, and the other terminal of the capacitor 5 is grounded.

Reference numeral 6 denotes a comparison circuit for comparing the terminal voltage of the capacitor 5 with the reference voltage (1), which includes a P N P l-transistor Ql1. Q12. Q13 and NPN transistor Q1
4. It consists of Q15. The base is a PNP transistor Q
This PNPI-transistor Q2 is connected to the base of Q2.
and PNP constituting a current mirror) - transistor Ql
The emitter of l is connected to the power supply VCC, and its collector is connected to two P N P l-transistors Q12. Each is connected to the emitter of Q13. The base of the PNPI transistor Q 12 is connected to one terminal of the capacitor 5, the collector is connected to the collector of the diode-connected NPN transistor Q 14, and the P N P l
-The collector of transistor Q13 is NPN) transistor Q
It is connected to 15 collectors. 2 NPN l-
Ransistor Q14. Q15 connect their bases to each other to form a current mirror, and their emitters are both grounded. 9 7 is a base i < 1 for providing the reference voltage 1 to the comparator circuit 6.
A voltage generation circuit, comprising a P N P ) transistor Q1
6, an NPNI transistor Q17, and a resistor 8.9. Base f! : Connect to the base of PNPh transistor Q2, and connect this PNPh transistor Q2 and Karen 1 to
r-'NP)-transistor Q1 that constitutes a mirror
The emitter of 6 is connected to the power supply Vcc, the collector is connected to one terminal of the resistor 8, and the connection point is PN
P) connected to the base of transistor Q1.3.

The other terminal of the resistor 8 is connected to one terminal of the resistor 9,
The other terminal of the resistor 9 is grounded. The collector of an NPN transistor Q17 is connected to the connection point between the two resistors 8.9, and its emitter is grounded.

10 is an output circuit for generating an oscillation output as the capacitor 5 is charged and discharged, and includes an N P N +- transistor Q18. Q19. Q20 and resistance 1].

It consists of 12.13.14.15. One terminal of resistor 1 is connected to the power supply Vcc, and the other terminal is NPN
It is connected to the collector of transistor Q18, whose collector is connected to the base of NPN l-transistor Q17, and whose emitter is grounded. One terminal of the resistor 12 is connected to the power supply Vcc, and the other terminal is connected to N F' N
+- is connected to the collector of transistor Q19, and its connection point is connected to N P N +- transistor Q through resistor 13.
], connected to the base of 8.

The base of NPN + helangistor Q19 is N P N +
- It is connected to the collector of transistor Q15, and the emitter of NPN transistor Q19 is grounded.

In addition, the connection point between the resistor 182 and the NPNI transistor Q19 is connected to the resistor 14 via the resistor 14.
is connected to the base of NP through a resistor 15.
N) Connected to the base of transistor Q20. NP
N) The collector of transistor Q20 is connected to output terminal 16, and the emitter is grounded.

The operation of the oscillation circuit described above is performed as follows.

Two PNP transistors Ql, Q of constant current output circuit 1
2 constitute Karen 1 to mirror, so PNPI-transistor Q1. The same amount of constant current ■1 is generated in Q2 as the collector current, and each of these constant currents ■1 is an NPN
Transistor Q4. It flows as the collector current of Q5.

Here, if the voltage between the base and emitter of the NPN transistor Q4 is 14, the voltage between the base and emitter of the NPN transistor Q5 is V, 15, and the resistance value of the resistor 3 is R2, then the following relationship holds true, as mentioned earlier. , NPN transistor Q5 has an emitter area 10 times that of NPN transistor Q4, so VM g 4 + V B □ are respectively where k: Boltzmann constant q: electron charge T: absolute temperature Is: NPN) Saturation of transistor Q4 Expressed as electric current.

Substituting the second and third equations into the first equation, we get The relationship holds true.

On the other hand, PNP) transistor Q6. Q7. Ql 1゜Q
16 also constitute a current mirror with the PNP transistor Q2, so a constant current 11 flows as their collector current.

In the comparator circuit 6, when the base voltage of the PNP) transistor Q13 is higher than the base voltage of the PNP) transistor Q12, that is, when the reference voltage V1 is higher than the terminal voltage of the capacitor 5, PNP)
The collector current is larger than that of transistor Q13 (PNP)
The current flows through transistor Q12, and the current flows as a collector current of NPN transistor Q14.

Two N l) N transistors Q14. Q15 mutually constitute a current 1~mirror, and the NPN transistor Q15 attempts to flow the same amount of collector current as the NPN)-transistor Q14, but the insufficient current at this time is
PN) - cannot be supplied from the base of transistor Q19, i.e. at this time NPN) transistor Q19 is in the off state, therefore N P N l - transistor Q8 is on, NPN) transistor Q18 is on, NPN
) Transistor Q17 is in the off state. Therefore, the reference voltage V1 at this time is vl=Lx (Re+R*)
...(5) However, R8: resistance value of resistor 8 R9 becomes the resistance value of two resistors 9. In the charge/discharge circuit 4, two NPN) transistors Q9. QIO form a current mirror with each other, but since NPN transistor Q8 is in the on state at this time, these two NPN transistors Q9 . Ql
O are both in the off state, PNP ) transistor Q
All of the constant current 1 supplied from 7 flows into the capacitor 5. That is, when the reference voltage V1 of the comparator circuit 6 is the value of the fifth equation, the capacitor 5 is charged by the constant current generator.

When the above charging operation progresses and the terminal voltage of the capacitor 5, that is, the base voltage of the PNP transistor Q12 exceeds the reference voltage 1 given by the fifth equation, the comparator circuit 6
NP) - transistor Q than PNP) - transistor Q12
The collector current of No. 13 is larger. NPN) - transistor Q14. Since the collector current of the same amount as that of the PNP) transistor Q12 flows through Q15, the difference between the collector currents of the PNP) transistor Q12 and Q13 flows as the base current of the NPN) transistor Q19.
PNI-transistor Q19 switches from off to on. Regarding this, the NPN transistor Q8 is off, and the NPN transistor Q8 is turned off.
N) transistor Q18 is turned off, NPN) - transistor Q17 is switched on. At this time, ′jM quasi-voltage V1
is V+=I +XRa,
= (6). In the charge/discharge circuit 4, at this time, NPN
) transistor Q8 is in the off state, and as mentioned earlier N
Since the PNI transistor Q10 has an emitter area twice that of the NPN transistor Q9, the NPN transistor QIO has a current that is twice as large as the current flowing through the NPN transistor Q9.
11 times the current flows.

That is, when the reference voltage (2) of the comparator circuit 6 is the value of the sixth equation, the capacitor 15 is discharged with a constant current FRI + through the NPN transistor QIO.

When the above-mentioned discharging operation progresses and the terminal voltage of the capacitor 5 drops to the reference voltage 1 given by the sixth formula, in the comparator circuit 6, the collector currents of the PNP transistors Q12 and Q13 become equal, and the NPN +- transistor Q19 Since no base current is supplied to the transistor Q19, the NPN transistor Q19 switches from on to off. Along with this, N
PN transistor Q8 is on, NPN) - transistor Q
18 is on, NPN transistor Q17 is switched off, and when the value reference voltage V of the fifth equation is set, the charging operation is switched to the above-mentioned charging operation.

By repeating the above operation, the N of the output circuit 10 is
PN transistor Q20 is NPN) transistor Q19
turns on during off-charging operation, and turns off during discharging operation when NPN) transistor Q19 turns on, and the third
In contrast to the charging/discharging waveform of the terminal voltage of the capacitor 5 (not shown in FIG. 3(a)), a rectangular wave oscillation output as shown in FIG. 3(b) is taken out from the output terminal 16. If the capacitance of the capacitor 5 is C1, and the change in the terminal voltage of the capacitor 5 due to charging and discharging is Δ■, then the oscillation period T of the oscillation output described above is
1 is expressed as. Δ■ is the reference voltage ■1 given by the fifth equation
The difference between
・Since it is (8), by substituting the 8th equation into the 7th equation, the oscillation period T1 is "2 Cs X Rs
...It is expressed as (9). Also, the 9th
From the equation, the temperature coefficient of the oscillation period T is expressed as follows.

Problems to be Solved by the Invention In the conventional oscillation circuit described above, the temperature coefficient of the oscillation period T1 is given as the sum of the temperature coefficient of the capacitor 5 and the temperature coefficient of the resistor 9, as shown in equation 10. The value will differ depending on the type of resistor 9 and the type of resistor 9.

In other words, the temperature coefficient of the capacitor 5 differs depending on whether it is an external aluminum electrolytic capacitor, a ceramic capacitor, or a junction capacitance formed within the semiconductor device, and the resistor 9 has a different temperature coefficient depending on whether it is an ion implanted resistor or a base diffusion capacitor. The temperature coefficient varies depending on the resistance.

In addition, the field of resistor 9 has a different temperature coefficient depending on its sheet resistance.

For example, in the case of ion implantation resistance, if the sheet resistance changes within the range of IKΩ/min to 5 IguΩ/min (Ω/min is the resistance value per unit surface), its temperature coefficient is 3400 Flpm/℃~5500 Pr-m
/'Ck varies over the range. In addition, for the thirst of the base diffusion resistance, the sheet resistance is 160Ω/'~310Ω/
Varying in the mouth range, its temperature coefficient is 180.0 p
p m / "C ~ 3100 p p m, -'
“Varies over a range of C.

Therefore, for example, if an aluminum electrolytic capacitor of external (=f) is used as the capacitor 5, and an ion-implanted resistor of Ω/mm is used for the sheet resistance 5 as the resistor 9, the temperature coefficient of the capacitor 5 is the temperature coefficient of the resistor 9. Therefore, the temperature of the oscillation period T1 (the number of threads is = +6700
There was a problem in that the value was very large, p pm/°C, and the error due to temperature became large.

Therefore, an object of the present invention is to set the oscillation period to the temperature i+[i
An object of the present invention is to provide an oscillation circuit that can obtain compensated oscillation output.

Problems and Means for Solving the Problems The present invention includes a charging/discharging circuit that charges and discharges a capacitor, and when the terminal voltage of the capacitor reaches an upper limit reference voltage, the operation of the charging/discharging circuit is switched to discharging, so that the terminal voltage of the capacitor increases. Lower limit M: In an oscillation circuit that switches the operation of the charging/discharging circuit to charging when the quasi-voltage is reached, and obtains an oscillation output whose oscillation period is the sum of the charging time and the discharging time, 11. ! This oscillation circuit is characterized in that it includes a base I(e) voltage generation circuit that generates a forward voltage of a diode as a quasi-voltage.

Effects According to the present invention, if the temperature is 1]°C, the temperature coefficient of the forward voltage of the diode of the reference voltage generating circuit is added as a negative element to the temperature coefficient of the oscillation period, so that temperature compensation of the oscillation period is performed.

Embodiment FIG. 1 is a circuit diagram showing the configuration of embodiments of the oscillation circuit of the present invention. In FIG.
21. Q22. Q23 and NPNI-transistor Q24
．． It consists of Q25 and resistor 22°23. Two PNs that connect their bases to form a current mirror
P transistor Q21. The emitter of Q22 is TL flow Vc
Q21.c, these PNP) transistors Q21. Q2
In order to draw out the base current of transistor Q23, the emitter and base of transistor Q23 are
l-transistor Q21. Base of Q22 and P N
P) - connected to the collector of transistor Q22, P
NP! - The collector of transistor Q23 is grounded.

Also, the collector of the PNP l transistor Q21 is connected to the collector of the diode-connected NPN transistor Q211, and the collector of the two NPNI transistors Q24.
The bases of Q25 are connected together. The emitter of NPNh transistor Q24 is grounded and N l” N l
- The emitter of transistor Q25 is connected to one end of a resistor 23, and the other end of this resistor 23 is grounded. NPNI
・Ran resistor Q24. Q25 base and electric A V c
When the power supply VcC rises, an NPN) transistor Q24. A resistor 22 for supplying pressure to the base is inserted in Q25. NPNI-transistor Q2
5 has an emitter area ten times that of the NPN transistor Q24.

24 is a charger 1' for charging and discharging the capacitor 25.
T:, circuit, PNPt-transistor Q26゜(
Q27, and an NPN transistor Q28. Q29゜Q30
It consists of. By connecting the base to the base of PNP transistor Q22, this P N P' h transistor Q2
2 and two PN F' l configuring the current mirror.
Ransistor Q26. The emitter of Q27 is connected to power supply VCC.

The collector of PNP transistor Q26 is connected to the collector of diode-connected NPN transistor Q29, and the collector of PNP transistor Q27 is connected to NPN transistor Q29.
+- Connected to the collector of transistor Q30. 2
Two NPN transistors Q29 and Q30 have their bases connected to each other to form a current mirror, and their emitters are both grounded. NPN transistor Q3
0 has an emitter area twice that of NPNI transistor Q29.

In addition, the collector of the NPN transistor Q28 is NPN)
Connected to the collector of transistor Q29, N P N
The emitter of I-transistor Q28 is grounded. N
The collector of the PN transistor Q30 is connected to one terminal of the capacitor 25, and the opposite terminal of the capacitor 25 is grounded. 26 is the terminal voltage t! of the capacitor 25!
- a comparison circuit for comparing with a reference voltage V2, comprising:
NP transistor Q31. Q32. Q33 and NPN)
Ransistor Q34. It consists of Q35. PNP base
) - connected to the base of transistor Q22 to connect this PNP
PNP forming a current mirror with transistor Q22
The emitter of transistor Q31 is connected to the power supply Vcc, and its collector is connected to two PNP transistors Q32. Q
33 emitters, respectively.

PNPI - The base of transistor Q32 is capacitor 25
The collector is connected to the collector of a diode-connected NPN transistor Q34,
Further, the collector of PNP transistor Q33 is connected to the collector of NPN transistor Q35. two N's
P N )--transistor Q34. Q35's bases are connected to each other to form a current mirror, and their emitters are both grounded.

27 is a base t for providing the reference voltage 2 to the comparator circuit 26.
JAT is a pressure generating circuit and is PNP! - transistor Q36 and NPN) consists of a transistor Q37, a resistor 28, and two diodes. The base is a PNP transistor Q2
This PNP transistor Q22 is connected to the base of Q22.
and PNP constituting a current mirror) - transistor Q3
The emitter of 6 is connected to the power supply Vcc, its collector is connected to one terminal of the resistor 28, and the connection point is connected to P.
Connected to the base of NP transistor Q33.

The other terminal of the resistor 28 is connected to the anodes of two diodes, and the cathodes of the two diodes are grounded. The collector of an NPN transistor Q37 is connected to the connection point between the resistor 28 and the diode 29, and its emitter is grounded.

30 is an output circuit for extracting oscillation output as the capacitor 25 is charged and discharged, and includes an NPN transistor Q3.
8. Q39. Q40 and resistance 31°32.33,34.
It consists of 35. One terminal of the resistor 31 is connected to the power supply Vcc, and the other terminal is connected to the NPN transistor Q38.
The collector is connected to the base of the NPN transistor Q37, and the emitter is grounded. One terminal of the resistor 32 is connected to the power supply Vcc, the other terminal is connected to the collector of the NPNI transistor Q39, and the connection point is connected to the NPNI transistor Q39 through the resistor 33.
Connected to the base of N transistor Q38.

NPN) - The base of transistor Q39 is NPN)
It is connected to the collector of transistor Q35, and the emitter of NPN transistor Q39 is grounded.

In addition, the connection point 50 between the resistor 32 and the NPN) transistor Q39 is connected via the resistors 3 and 1 to the NPN) transistor Q2.
8 and is connected to the base of N
It is connected to the base of P, N transistor Q40.

The collector of NPN transistor Q40 is connected to output terminal 36, and the emitter is grounded.

The above-described oscillation circuit operates in substantially the same manner as the conventional oscillation circuit described above.

That is, in the constant current output circuit 21, PNP)-transistor Q21. The same amount of constant current ■2 is generated as the collector current in Q22, and each of these constant currents I2 is NPN
l-transistor Q24. It flows as the collector current of Q25. Letting the resistance value of the resistor 23 be RB, this constant current I2 is expressed as in the fourth equation above.

In the comparison circuit 26, the terminal voltage of the capacitor 25 and the reference voltage V2 are compared, and the terminal voltage of the capacitor 25 is compared with the reference voltage V2.
In the charging operation in which the constant TL current I2 flows into the capacitor 25 from
...(5n) However, R2, : resistance value of the resistor 28, : forward voltage of two diodes. In addition, the constant current (2) does not flow from the capacitor 25 through the NPN)-Run' transistor Q30, and the discharge current (at Y, the NPN transistor Q37 is turned on,
Reference voltage ■2 is V2=I 2×R2#
・= (6a) When the terminal voltage of the capacitor 25 drops to the reference voltage ■2 given by Equation 6a, the charging operation is switched, and the terminal voltage of the capacitor 25 decreases to the reference voltage ■2 given by Equation 5a. When the voltage rises to 2, the operation switches to the discharging operation, and by repeating the above operation, a rectangular wave oscillation output corresponding to the charging and discharging of the capacitor 25 is extracted from the output terminal 36 of the output circuit 30.

If the capacitance of the capacitor 25 is C2S, and the change in the terminal voltage of the capacitor 25 due to charging and discharging is ΔV, then the oscillation period T of the oscillation output described above is expressed as. Δ■ is the difference between the reference voltage ■2 given by formula 5a and the reference voltage ■2 given by formula 6a, that is, ΔV=V, ...(8
a), by substituting equation 8a into equation 7, the oscillation period T2 becomes, and by substituting equation 4a into equation 9a, (l
It is expressed as R, ko. From Equation 9b, the temperature coefficient of the oscillation period T2 is expressed as follows. Now, for example, as capacitor 25,
・If an ion-implanted resistor with a sheet resistance of 5 and a resistance of 5 Ω/hole is used as the resistor 23 for an aluminum electrolytic capacitor of 100 m, the respective temperature coefficients on the right side of Equation 10a are as follows, and when these are substituted into Equation 10a, Oscillation period T
The temperature coefficient of 2 is equal to 11 ppm/"C L:, 0. In other words, it is possible to obtain an oscillation output whose oscillation period T2 is temperature compensated. If another type of capacitor 25 is used, , the temperature coefficient of the capacitor 25 will change, but in this case, the oscillation can be suppressed by changing the resistor 23 from an ion implanted resistor to a base diffusion resistor, or by appropriately setting the sheet resistance of the resistor 23. The temperature coefficient of period T2 can be set to a value close to zero.

Effects of the Invention As described above, according to the oscillation circuit of the present invention, the temperature coefficient of the forward voltage of the diode of the reference voltage generation circuit is added as a negative element to the temperature coefficient of the oscillation cycle. Compensated oscillation output can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an oscillation circuit according to an embodiment of the present invention, Fig. 2 (21 is a circuit diagram showing an oscillation circuit according to b'C), and Fig. 3 is a circuit diagram showing an oscillation circuit according to an embodiment of the present invention.
12I (a>, (b) are waveform diagrams showing the capacitor terminal voltage and oscillation output of the oscillation circuit, respectively. 21. Constant current output circuit, 24. Charge/discharge circuit, 25.
... Capacitor, 26 ... Comparison circuit, 27 ... Reference voltage generation circuit, 30 ... Output circuit Agent Patent attorney Keiichi Nishikyo

Claims (1)

[Claims] A charging/discharging circuit that charges and discharges a capacitor is included, and when the terminal voltage of the capacitor reaches an upper limit reference voltage, the operation of the charging/discharging circuit is switched to discharging, and the terminal voltage of the capacitor reaches the lower limit reference voltage. In the oscillation circuit, the operation of the charging/discharging circuit is switched to charging when the voltage reaches the threshold, and an oscillation output whose oscillation period is the sum of the charging time and the discharging time is obtained. An oscillation circuit characterized by being provided with a voltage generation circuit.