JPH0126561B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a pattern of a high-frequency, high-power transistor, particularly a pattern of a two-row transistor unit with improved high-frequency characteristics and a wire bonding method, and a chip of a high-frequency, high-power transistor. Regarding the arrangement of the bonding pads (electrodes) above.

(2) Background of the Technology A high-frequency, high-output transistor shown in Fig. 1 is known. In the figure, 1 is a transistor chip, 2 is a transistor unit formed in the chip 1, and 3 is an internal matching MOS transistor. C, 4 is the input terminal (connected to the base electrode), 5 is the output terminal (connected to the collector electrode), 6 is the short bridge (the wiring to the collector electrode is placed below this), and 7 is the ground The flange also serves as a heat dissipation flange (the emitter of the illustrated transistor is grounded), 8 is a grounding wire, and 9 is an input wire.

(3) Prior art and problems There are several problems with high frequency, high power transistors. There is no special transistor called a high-frequency, high-output transistor, but instead a large number of high-frequency, small-signal transistors (called a transistor unit) are collected, arranged in parallel, and operated to obtain high-frequency, high-output transistors. One of the problems is
From such a unit, how can 1+1=2, 2+
The question is whether to obtain the output as follows: 2=4...
Although many such high frequency small signal transistors operate, they do not all operate uniformly due to variations within the wafer when they are manufactured and variations during assembly. How to make them work uniformly has an important meaning in obtaining excellent high-frequency, high-output transistors. One solution to this problem is the pattern of the ground terminal. That is, in a high-frequency, high-output transistor, in order to achieve high output, a long emitter circumference, a large-area collector for accommodating the emitter, and a large-area semiconductor chip are used.
On the other hand, in order to uniformly operate emitters arranged over a large area at high frequencies or groups of transistor units with appropriate emitter circumferences, and to reduce the inductance of ultra-thin wires (bonding wires) connected to external leads, It is necessary to install the book bonding wires evenly.

In the conventional high-frequency, high-output transistor shown in FIG. 1, wire bonding as shown in the figure has been performed for the pattern of the transistor unit as shown in the figure. As can be understood from the figure, an input terminal 4 is placed on the lower side, an output terminal 5 is placed on the upper side, and a transistor chip 1 is placed between them.
is mounted and connected to external leads by wire bonding. Note that MOS-C is an element of an internal matching circuit installed in a package to increase input impedance and facilitate impedance matching with an external circuit, and is a MOS capacitor formed on a semiconductor substrate. Furthermore, the second
The figure is a side sectional view of the apparatus of FIG. 1, and in FIGS. 1 and 2, ,,,, indicate bonding wires.

As shown in FIG. 1, grounding wires are stretched on both sides of the chip to improve high frequency and high output characteristics. This comes from the following requirements.

A: I want to connect the ground points on the input side and output side with the shortest possible distance so that they have the same potential at high frequencies as much as possible.

B I want to reduce the composite self-grounding inductance by using multiple wires, and also reduce the mutual inductance by stretching them 180 degrees in opposite directions.

Furthermore, in order to achieve high output, it is necessary to further increase the circumference of the emitter as described above. For this reason, if a design is adopted in which the number of transistor units of the transistor chip shown in FIG. 1 is increased and added in the horizontal direction, the transistor chip becomes too long in the horizontal direction, and there is a limit. That is, there are problems with the container that houses the transistor, and problems with the chip becoming larger and cracking due to thermal expansion.

On the other hand, there are limits to increasing the emitter circumference by increasing the size of one transistor unit, due to the uniformity of high-frequency current within the transistor unit, limitations on the current capacity of the wire, and increased self-inductance. be.

Therefore, in order to increase the output, it is necessary to arrange the transistor units in two horizontal rows within the chip, but if the transistor units are arranged in two rows, the following two problems arise.

With a two-row arrangement, it is difficult to match the lengths of the ground and input wires. There is also the problem that the wires come into contact with each other, making it impossible to bond them with wire bonding.

Because of the geometric distance between the two rows of transistor units, it is difficult for their high-frequency grounds to be at the same potential.

(4) Purpose of the invention The present invention improves the above conventional problems,
Furthermore, it is an object of the present invention to provide an arrangement of bonding pads for high-frequency, high-output transistors arranged in two rows in a pattern that also meets the requirements A and B, and wire bonding to such bonding pads.

(5) Structure of the Invention According to the present invention, this object is to provide an input terminal and an output terminal arranged to face each other, and an internal matching capacitor disposed between the input terminal and the output terminal. a rectangular transistor chip provided between the output terminal and the internal matching capacitor, the long sides of which are parallel to the input terminal and the output terminal; In a transistor arranged parallel to the long side and consisting of a first column and a second column of transistor unit groups each consisting of a plurality of transistor units, between the first column of transistor unit groups and the second column of transistor unit groups. One end is connected to a first transistor unit constituting a first column transistor unit group, and the other end is connected to a second transistor constituting a second column transistor unit group closest to the first transistor. Each of the first transistor units has a strip-shaped grounding bonding pad connected to the unit, and an input pad connected to a surface of each of the transistor units to which the bonding pad is not connected, and each of the first transistor units includes: This is achieved by providing a transistor characterized in that it is disposed corresponding to a central position between the second transistor units.

(6) Examples of the invention Embodiments of the present invention will be explained in detail below with reference to the drawings.

The present invention solves the above-mentioned problems as much as possible, and also satisfies requests A and B. The present invention provides an arrangement of bonding pads for high-frequency, high-output transistors in which transistor units are arranged in two rows in a pattern, and a bonding pad arrangement for bonding pads for high-frequency, high-power transistors in which transistor units are arranged in two rows. This was done regarding wire bonding.

3 and 4 show the arrangement of the transistor unit and bonding pads. That is, input,
The short side of the chip 11 is placed in the direction of the output external terminal (vertical direction), the long side of the chip is placed in the direction perpendicular thereto (horizontal direction), and two rows of transistor units 12 are placed in the horizontal direction. In addition, in Figures 3 and 4,
Reference numeral 13 indicates an input pad, and 14 indicates a grounding bonding pad.

Alternatively, the transistor may have one or two patterns each having a band-like base shape that is not divided into individual parts as shown in FIG. The key is how to arrange the grounding bonding pads. In addition, in FIG. 5, 21 is a chip,
22 is a transistor active part, 23 is an input pad, and 24 is a ground bonding pad.

Returning to FIG. 4, ground bonding pads 14 are arranged in horizontal rows in the center of the chip. Moreover, the grounding bonding pads of at least the two closest transistor units, upper and lower, are formed of band-shaped metal patterns with low resistance and low inductance. Input pads 13 are arranged in two horizontal rows above and below the grounding pad rows. Furthermore, the horizontal positions of the top and bottom rows are placed in the middle of each other.

6 and 7 are a top view and a side view showing the wire bonding pad arrangement and wire bonding rows for the chip according to the present invention, and the same parts as in FIG. 3 are denoted by the same reference numerals. terminal, 16
17 indicates an output terminal, and 17 indicates a grounding/heat dissipation flange.

In Fig. 6, the chip 11 has dimensions of 1.5 mm x 4.5 mm, and the width w (Fig. 3) of the input pad is
The wire was set to 70 μm and the length l (FIG. 3) was 100 μm, and a gold wire with a diameter of 25 μm to 50 μm was bonded using a bonding machine. The bonding wire may be aluminum (Al). In the figure, bonding wires are indicated with the symbols , , .

As explained above, in order to make the lengths of the grounding wires 8 the same, one common grounding bonding pad 14 is arranged between the upper and lower two transistor units 12. The lengths of the transistor units in the upper and lower two rows are equal.

On the other hand, in order to equalize the lengths of the input wires 9, as shown in FIGS. 6 and 7, adjust the wire bonding positions to the input internal matching MOS-C3 so that they correspond to the In the example,
Wire bonding from the MOS-C 3 to the input terminal 13 was performed from the middle position of each transistor unit 12.

Further referring to FIG. 6, for example, the input wire 9 connecting the input bonding pad 13 of the rightmost transistor unit 12 in the lower row and the MOS-C3 and the second transistor unit from the right in the upper row are connected. 12 input bonding pads 13
Comparing the input wire 9 that connects the input wire 9 and the MOS-C3, the latter input wire 9 is bonded at a position higher than the first input wire 9 in the MOS-C3, thereby making it possible to connect the first and second input wires 9. The lengths of the input wires 9 are made equal.

(7) Effects of the Invention As explained in detail above, according to the present invention, the above-mentioned problems are solved and a high-frequency transistor with high gain and high output is obtained.

[Brief explanation of drawings]

1 and 2 are a plan view and a sectional view of a conventional high-frequency high-output transistor, FIGS. 3 and 4 are a schematic plan view and a diagram showing the bonding pad arrangement of an embodiment of the present invention, and FIG. 5 is a schematic plan view of another embodiment,
6 and 7 are a plan view and a side view showing the wire bonding of the embodiment of FIG. 3. FIG. 11...Natsupu, 12...Unit, 13...
Bonding pad for input, 14... Bonding pad for grounding, 15... Input terminal, 16... Output terminal, 17... Flange for grounding and heat radiation,
,,...bonding wire.

Claims (1)

[Claims] 1. An input terminal and an output terminal arranged to face each other, an internal matching capacitor disposed between the input terminal and the output terminal, and the output terminal and the internal matching capacitor. a rectangular transistor chip provided between matching capacitors and having long sides parallel to the input terminal and the output terminal; and a rectangular transistor chip provided on the chip parallel to the long sides;
In a transistor consisting of a first column and a second column of transistor unit groups each consisting of a plurality of transistor units, one end is connected to the transistor of the first column between the first column of transistor unit groups and the second column of transistor unit groups. A band-shaped grounding transistor unit connected to a first transistor unit constituting a unit group, and the other end connected to a second transistor unit constituting a second column transistor unit group closest to the first transistor. a bonding pad; and an input pad connected to a surface of each of the transistor units to which the bonding pad is not connected, and each of the first transistor units has a connection between the second transistor units. A transistor characterized in that it is arranged corresponding to the center position of the space separating it.