JPH0126566B2 - - Google Patents
Info
- Publication number
- JPH0126566B2 JPH0126566B2 JP58248488A JP24848883A JPH0126566B2 JP H0126566 B2 JPH0126566 B2 JP H0126566B2 JP 58248488 A JP58248488 A JP 58248488A JP 24848883 A JP24848883 A JP 24848883A JP H0126566 B2 JPH0126566 B2 JP H0126566B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- time
- power supply
- circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/52—Input signal integrated with linear return to datum
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Description
【発明の詳細な説明】
本発明は、例えばひずみゲージ式変換器等の検
出回路に接続されるA−D変換装置に関する。こ
の種の装置として、先に本出願人は第1図示の回
路から成る三重積分型変換装置を提案した。第1
図において、aはひずみゲージを含む抵抗体によ
つて構成されるブリツジ回路で、該回路aの一対
の対角点はスイツチbを介してブリツジ電源cに
接続し、他の一対の対角点は増幅器dを介して極
性反転器eに接続した。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an A/D converter connected to a detection circuit such as a strain gauge transducer. As a device of this type, the present applicant previously proposed a triple integral type conversion device consisting of the circuit shown in the first diagram. 1st
In the figure, a is a bridge circuit constituted by a resistor including a strain gauge, a pair of diagonal points of the circuit a are connected to a bridge power source c via a switch b, and a pair of diagonal points of the circuit a are connected to a bridge power source c via a switch b. was connected to the polarity inverter e via an amplifier d.
fは切換スイツチ、gは基準電源、hは積分
器、iは積分器hの出力が零になつたときカウン
タjによるクロツク発振器kのクロツクパルスの
計数を止めるコンパレータ、lはスイツチb、切
換スイツチf及びカウンタjの作動を制御する
CPUである。 f is a changeover switch, g is a reference power supply, h is an integrator, i is a comparator that stops counter j from counting the clock pulses of clock oscillator k when the output of integrator h becomes zero, l is switch b, changeover switch f and controls the operation of counter j
It is the CPU.
このものは、先ず、スイツチbが開かれ、切換
スイツチfが固定接点aに接続されて、第2図
A,Bに示すように、時間T1の間、増幅器dの
零点移動や熱起電力などの不要電圧E0を積分器
hにより逆極性に積分し、次にスイツチbが閉じ
られ、切換スイツチfが固定接点bに接続されて
時間T2(=T1)の間ブリツジ回路aの出力Eiと不
要電圧E0との和を正極性に積分する。以上の動
作で不要電圧E0は消去され、出力Eiだけが積分
されたことになる。次にスイツチbが開かれ、切
換スイツチfが固定接点cに接続され時間T3の
間基準電源電圧ERを逆極性に積分し、積分器h
の出力電圧が零となつたところで積分が停止さ
れ、間T3の開始からCPUlの指令でクロツクパル
スの計数を開始したカウンタjは計数を停止す
る。時間T3は出力Eiに比例するので、カウンタ
jの計数結果から出力Eiがデイジタル値となる。 First, switch b is opened, changeover switch f is connected to fixed contact a, and as shown in FIG . The unnecessary voltage E 0 such as Integrate the sum of the output Ei and the unnecessary voltage E 0 to positive polarity. With the above operation, the unnecessary voltage E 0 is erased, and only the output Ei is integrated. Next, switch b is opened, changeover switch f is connected to fixed contact c, and the reference power supply voltage E R is integrated with the opposite polarity for a time T 3 , and the integrator h
The integration is stopped when the output voltage of becomes zero, and the counter j, which started counting clock pulses from the start of interval T3 by the CPU1 command, stops counting. Since the time T3 is proportional to the output Ei, the output Ei becomes a digital value from the count result of the counter j.
以上のように3重積分が行なわれることにより
不要電圧E0の影響を受けることなくブリツジ回
路aの出力をデイジタル値に変換できるが、その
動作時間はT1+T2+T3であり例えば60ミリ秒程
度となつて高速化できない不都合が存した。本発
明は、かかる不都合のないA−D変換装置を提供
することをその目的としたものであつて、極性反
転回路、積分器、基準電源、回路切換手段及び計
数手段を備え、該積分器において、電源に接続さ
れた検出回路の出力電圧Eiを所定時間T1の間積
分することと、該積分電圧と等しい電圧になるま
での時間T2の間、電源電圧が加わらない検出回
路の出力電圧の前記極性反転回路による反転電圧
−E0と負極性の基準電源電圧ERの和を積分する
ことと、前記反転電圧−E0を時間T1−T2の間積
分することと、該積分電圧と等しい電圧になるま
での時間T4の間正極性の基準電源電圧ERを積分
することとを前記回路切換手段の作動により順次
行なわせ、前記計数手段により前間時間T2と時
間T4との差を計数するようにしたことを特徴と
する。 By performing the triple integration as described above, the output of the bridge circuit a can be converted into a digital value without being affected by the unnecessary voltage E0 , but the operating time is T1 + T2 + T3 , which is, for example, 60 millimeters. There was an inconvenience that the speed could not be increased because it took about seconds. An object of the present invention is to provide an A-D converter free from such inconveniences, which comprises a polarity reversing circuit, an integrator, a reference power source, a circuit switching means, and a counting means, and is equipped with a polarity inverting circuit, an integrator, a reference power source, a circuit switching means, and a counting means. , the output voltage Ei of the detection circuit connected to the power supply is integrated for a predetermined time T1 , and the output voltage of the detection circuit to which the power supply voltage is not applied during the time T2 until the voltage becomes equal to the integrated voltage. integrating the sum of the inverted voltage -E 0 by the polarity inverting circuit and the reference power supply voltage E R of negative polarity; integrating the inverted voltage -E 0 over time T 1 -T 2 ; The operation of the circuit switching means sequentially integrates the positive reference power supply voltage E R during the time T 4 until the voltage becomes equal to the voltage, and the counting means integrates the previous time T 2 and the time T It is characterized by counting the difference from 4 .
以下本発明の実施例を図面につき説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第3図は本発明の一実施例のブロツク図を示
す。第3図において、1はひずみゲージを含む抵
抗体によつて構成されるブリツジ回路で、該回路
1の一対の対角点はスイツチ2を介してブリツジ
電源3に接続し、他の一対の対角点は増幅器4を
介して極性反転回路5に接続した。6は切換スイ
ツチで、その固定接点aは増幅器4に、固定接点
bは極性反転回路5に各接続した。7も切換スイ
ツチで、その固定接点a,bはそれぞれ基準電源
8の+、−端子に接続した。9は積分器、10は
積分器9の積分電圧が零になつた時その出力でカ
ウンタ11のクロツク発振器12からのクロツク
パルスの計数を停止するコンパレータ、13は、
スイツチ2、切換スイツチ6,7を下記に説明す
るような過程で制御すると共にカウンタ11のア
ツプカウント又はダウンカウントを開始させる
CPUである。 FIG. 3 shows a block diagram of one embodiment of the present invention. In FIG. 3, reference numeral 1 denotes a bridge circuit constituted by a resistor including a strain gauge. A pair of diagonal points of this circuit 1 are connected to a bridge power supply 3 via a switch 2, and the other pair of diagonal points are connected to a bridge power supply 3 via a switch 2. The corner points were connected to a polarity inversion circuit 5 via an amplifier 4. Reference numeral 6 denotes a changeover switch, the fixed contact a of which is connected to the amplifier 4 and the fixed contact b connected to the polarity inverting circuit 5. 7 is also a changeover switch, and its fixed contacts a and b are connected to the + and - terminals of a reference power source 8, respectively. 9 is an integrator; 10 is a comparator which uses its output to stop counting clock pulses from the clock oscillator 12 of the counter 11 when the integrated voltage of the integrator 9 becomes zero; 13,
The switch 2 and changeover switches 6 and 7 are controlled in the process described below, and the counter 11 starts counting up or down.
It is the CPU.
次にその作動を説明する。 Next, its operation will be explained.
先ず、CPU13によりスイツチ2が閉じられ
切換スイツチ6は固定接点aに、切換スイツチ7
は固定接点cに各接続されて、第4図A,Bに示
すように時間T1の間、ブリツジ回路1の出力電
圧Ei及び増幅器4などからの不要電圧E0の和が
積分器9で積分される。時間T1経過するとCPU
13によりスイツチ2が開始され、切換スイツチ
6が固定接点bに、切換スイツチ7が固定接点b
に各接続されて、負極性となつた不要電圧−E0
と負極性の基準電源電圧−ERの和が時間T2の間
積分器9で積分される。この時間T2の開始と同
時にCPU13からの指令でクロツク発振器12
の出力するクロツクパルスのアツプカウントを開
始したカウンタ11は、積分器9の出力が零にな
つた時間T2の経過時点におけるコンパレータ1
0の出力により計数を停止する。次にこの時点
で、コンパレータ10の出力に基づいてCPU1
3により切換スイツチ7のみが固定接点cに切換
えて接続されるので、時間T2との合計時間が時
間T1と等しくなる時間T3の間、負極性の不要の
不要電圧−E0が積分される。 First, the switch 2 is closed by the CPU 13, the changeover switch 6 becomes the fixed contact a, and the changeover switch 7 becomes the fixed contact a.
are connected to the fixed contacts c , and as shown in FIG . It is integrated. After time T 1 elapses, CPU
13, switch 2 is started, changeover switch 6 is set to fixed contact b, changeover switch 7 is set to fixed contact b
-E 0
The sum of the negative polarity reference power supply voltage -E R is integrated by the integrator 9 for a time T 2 . At the same time as the start of this time T2 , the clock oscillator 12 is activated by a command from the CPU 13.
The counter 11 that started counting up the clock pulses output by the comparator 1 at the time T2 when the output of the integrator 9 became zero
Counting is stopped by outputting 0. Next, at this point, based on the output of the comparator 10, the CPU 1
3, only the changeover switch 7 is switched to and connected to the fixed contact c, so during the time T3 when the total time with the time T2 is equal to the time T1 , the unnecessary voltage of negative polarity -E0 is integrated. be done.
この時間T3の経過した時点では不要電圧E0は
消去されたことになるが、時間T3の間の積分電
圧の分だけ負極性の電圧−ERを多く積分したこ
とになるので、時間T2は出力電圧Eiに対応した
時間より長くなる。そこでこの分を減算するため
に以下の操作を続行する。 When this time T 3 has elapsed, the unnecessary voltage E 0 has been erased, but since the negative polarity voltage −E R has been integrated as much as the integrated voltage during the time T 3 , T 2 is longer than the time corresponding to the output voltage Ei. Therefore, in order to subtract this amount, continue the following operation.
時間T3の経過した時点でスイツチ2は開成の
まゝで、CPU13により切換スイツチ6は固定
接点cに、切換スイツチ7は固定接点aに各接続
され、積分器9の出力が零になるまでの時間T4
の間今度は正極性の基準電圧ERが積分される。
CPU13は時間T4の開始時点でコンパレータ1
0の出力の極性に基づきカウンタ11にダウンカ
ウントの指令信号を加えるので、カウンタ11
は、時間T2におけるカウント値からダウンカウ
ントを行い、時間T4の経過した時点でコンパレ
ータ11の出力により計数を停止する。カウンタ
11の計数結果は時間T2−T4に対応し、この間
は出力電圧Eiに対応するので、カウンタ11はEi
のデイジタル量を出力する。 When time T3 has elapsed, switch 2 remains open, and the CPU 13 connects changeover switch 6 to fixed contact c and changeover switch 7 to fixed contact a, until the output of integrator 9 becomes zero. Time of T 4
During this time, the positive reference voltage E R is integrated.
CPU 13 outputs comparator 1 at the beginning of time T 4 .
Since a down-count command signal is applied to the counter 11 based on the polarity of the output of 0, the counter 11
performs down counting from the count value at time T2 , and stops counting by the output of the comparator 11 when time T4 has elapsed. The counting result of the counter 11 corresponds to time T 2 - T 4 , and since this period corresponds to the output voltage Ei, the counter 11 counts Ei
Outputs a digital quantity.
以上の関係を数式で示すと次のようになる。 The above relationship can be expressed mathematically as follows.
時間T1では E1=1/RC∫T1 0(E0+Ei)dt=1/RC(E0+Ei)T1 ……(1) 時間T2では −E1=1/RC∫T2 0(-ER-E0)dt=−1/RC(ER+E0)T2 ……(2) 時間T3では −E2=1/RC∫T3 0(-E0)dt=−1/RCE0・T3 ……(3) 時間T4では E2=1/RC∫T4 0ERdt=1/RCER・T4 ……(4) であるから、これ等の式から Ei=ERT2−T4/T1 ……(5) がえられる。 At time T 1 , E 1 = 1/RC∫ T1 0 (E 0 +Ei)dt=1/RC(E 0 +Ei)T 1 ……(1) At time T 2 , −E 1 = 1/RC∫ T2 0 (-E R -E 0 )dt=-1/RC(E R +E 0 )T 2 ...(2) At time T 3 , -E 2 =1/RC∫ T3 0 (-E 0 )dt= -1/RCE 0・T 3 ...(3) At time T 4 , E 2 = 1/RC∫ T4 0 E R dt=1/RCE R・T 4 ...(4) Therefore, these equations From this, we get Ei=E R T 2 −T 4 /T 1 ……(5).
この式から明らかなように、出力電圧Eiは、基
準電源電圧ER、時間T1は既知であるから、(T2−
T4)に比例する。したがつて時間(T2−T4)に
対応するパルス数をカウンタ11で計数すれば出
力電圧Eiをデイジタル量に変換することができ
る。 As is clear from this equation, since the reference power supply voltage E R and the time T 1 are known, the output voltage Ei is (T 2 −
T 4 ). Therefore, if the counter 11 counts the number of pulses corresponding to the time (T 2 -T 4 ), the output voltage Ei can be converted into a digital quantity.
前記不要電圧E0は前述のように増幅器4のオ
フセツト電圧や接続部の熱起電力であり、ブリツ
ジ回路1の出力電圧のフルスケール値に対して実
際上ほゞ1/100以下である。したがつて積分時間
T4は時間T1を20ミリ秒とすれば、0.2ミリ秒以下
となりT1をさきに提案のものと同じく20ミリ秒
とすると、全体の変換時間T1+T2+T3+T4は
40.2ミリ秒となり、短時間となる。 As mentioned above, the unnecessary voltage E 0 is the offset voltage of the amplifier 4 or the thermal electromotive force of the connection part, and is actually less than 1/100 of the full scale value of the output voltage of the bridge circuit 1. Therefore the integration time
If T 1 is 20 ms, then T 4 is less than 0.2 ms, and if T 1 is 20 ms as in the previous proposal, the total conversion time T 1 + T 2 + T 3 + T 4 is
It takes 40.2 milliseconds, which is a short time.
尚、前記実施例では、スイツチ2を開成してブ
リツジ回路1に加える電源電圧を除去したが、ブ
リツジ電源3の電圧が零になるように該電源3を
CPU13で制御してもよい。 In the above embodiment, the switch 2 was opened to remove the power supply voltage applied to the bridge circuit 1, but the power supply 3 was turned off so that the voltage of the bridge power supply 3 became zero.
It may also be controlled by the CPU 13.
また、スイツチ2、切換スイツチ6及び7並び
にカウンタ11の制御をCPU13の代りにタイ
マその他の素子を組合せた制御回路を用いること
ができる。 Further, for controlling the switch 2, the changeover switches 6 and 7, and the counter 11, a control circuit combining a timer and other elements can be used instead of the CPU 13.
このように本発明によるときは、極性反転回
路、積分器、基準電源、回路切換手段及び計数手
段を備え、該積分器において電源に接続された検
出回路の出力電圧Eiを所定時間T1の間積分する
ことと、該積分電圧と等しい電圧になるまでの時
間T2の間電源電圧が加わらない検出回路の出力
電圧の前記極性反転回路による反転電圧−E0と
負極性の基準電源電圧ERの和を積分することと、
前記反転電圧−E0を時間T1−T2の間積分するこ
とと、該積分電圧と等しい電圧になるまでの時間
T4の間正極性の基準電源電圧ERを積分すること
とを前記回路切換手段の作動により順次行なわ
せ、前記計数手段により前記時間T2と時間T4の
差を計数するようにしたので、先に提案したもの
と同様増幅器の零点移動などによる不要電圧を除
去して検出回路の出力電圧をA−D変換できると
共に、従来の二重積分型と同等程度に高速に変換
できる等の効果を有する。 As described above, the present invention includes a polarity inverting circuit, an integrator, a reference power source, a circuit switching means, and a counting means, and in the integrator, the output voltage Ei of the detection circuit connected to the power source is maintained for a predetermined time T1 . Integration and the inversion voltage by the polarity inverting circuit of the output voltage of the detection circuit during which no power supply voltage is applied during the time T 2 until the voltage becomes equal to the integrated voltage -E 0 and the negative reference power supply voltage E R and integrating the sum of
Integrating the inverted voltage −E 0 for a time T 1 −T 2 and the time required to reach a voltage equal to the integrated voltage.
The circuit switching means is operated to sequentially integrate the reference power supply voltage E R of positive polarity during T4 , and the counting means counts the difference between the time T2 and the time T4 . , similar to the previously proposed method, the output voltage of the detection circuit can be converted from A to D by removing unnecessary voltage due to the shift of the zero point of the amplifier, etc., and the conversion can be performed at a high speed comparable to that of the conventional double integration type. has.
第1図は本出願人の提案に係る三重積分型A−
D変換装置のブロツク図、第2図は、その積分器
の入力電圧及び出力電圧の各波形を示す図、第3
図は本発明の一実施例のブロツク図、第4図はそ
の積分器の入力電圧及び出力電圧の各波形を示す
図である。
1……ブリツジ回路、2……スイツチ、3……
ブリツジ電源、5……極性反転回路、6,7……
切換スイツチ、8……基準電源、9……積分器、
10……コンパレータ、11……カウンタ、12
……クロツク発振器、13……CPU。
Figure 1 shows the triple integral type A- according to the applicant's proposal.
A block diagram of the D converter, Fig. 2 is a diagram showing each waveform of the input voltage and output voltage of the integrator, and Fig. 3 is a block diagram of the D converter.
This figure is a block diagram of one embodiment of the present invention, and FIG. 4 is a diagram showing each waveform of the input voltage and output voltage of the integrator. 1... bridge circuit, 2... switch, 3...
Bridge power supply, 5... Polarity inversion circuit, 6, 7...
Changeover switch, 8...Reference power supply, 9...Integrator,
10... Comparator, 11... Counter, 12
...Clock oscillator, 13...CPU.
Claims (1)
手段及び計数手段を備え、該積分器において、電
源に接続された検出回路の出力電圧Eiを所定時間
T1の間積分することと、該積分電圧と等しい電
圧になるまでの時間T2の間、電源電圧が加わら
ない検出回路の出力電圧の前記極性反転回路によ
る反転電圧−E0と負極性の基準電源電圧ERの和
を積分することと、前記反転電圧−E0を時間T1
−T2の間積分することと、該積分電圧と等しい
電圧になるまでの時間T4の間正極性の基準電源
電圧ERを積分することとを前記回路切換手段の
作動により順次行なわせ、前記計数手段により前
記時間T2と時間T4との差を計数するようにした
ことを特徴とするA−D変換装置。1 Equipped with a polarity inversion circuit, an integrator, a reference power supply, a circuit switching means, and a counting means, in which the output voltage Ei of the detection circuit connected to the power supply is controlled for a predetermined period of time.
During the integration period T 1 and the time T 2 until the voltage becomes equal to the integrated voltage, the inversion voltage −E 0 by the polarity inversion circuit of the output voltage of the detection circuit to which no power supply voltage is applied and the negative polarity Integrating the sum of the reference power supply voltage E R and the inversion voltage −E 0 at time T 1
−T2 and integrating the positive reference power supply voltage E R for a time T4 until the voltage becomes equal to the integrated voltage are sequentially performed by operating the circuit switching means; An A/D conversion device characterized in that the counting means counts the difference between the time T2 and the time T4 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24848883A JPS60143026A (en) | 1983-12-29 | 1983-12-29 | A-d converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24848883A JPS60143026A (en) | 1983-12-29 | 1983-12-29 | A-d converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60143026A JPS60143026A (en) | 1985-07-29 |
| JPH0126566B2 true JPH0126566B2 (en) | 1989-05-24 |
Family
ID=17178904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24848883A Granted JPS60143026A (en) | 1983-12-29 | 1983-12-29 | A-d converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60143026A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013140582A1 (en) * | 2012-03-22 | 2013-09-26 | パイオニア株式会社 | Detection device and method |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4647124B2 (en) * | 2001-03-22 | 2011-03-09 | 株式会社東京測器研究所 | A / D converter |
| DE102006051365B4 (en) * | 2006-10-27 | 2011-04-21 | Sartorius Ag | Measuring amplification device and method |
| JPWO2013140582A1 (en) * | 2012-03-22 | 2015-08-03 | パイオニア株式会社 | Detection apparatus and method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55120223A (en) * | 1979-03-08 | 1980-09-16 | Yokogawa Hokushin Electric Corp | Double integration type ad converter |
-
1983
- 1983-12-29 JP JP24848883A patent/JPS60143026A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013140582A1 (en) * | 2012-03-22 | 2013-09-26 | パイオニア株式会社 | Detection device and method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60143026A (en) | 1985-07-29 |
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| EXPY | Cancellation because of completion of term |