JPH01268158A - Ceramic board for semiconductor device - Google Patents
Ceramic board for semiconductor deviceInfo
- Publication number
- JPH01268158A JPH01268158A JP63097581A JP9758188A JPH01268158A JP H01268158 A JPH01268158 A JP H01268158A JP 63097581 A JP63097581 A JP 63097581A JP 9758188 A JP9758188 A JP 9758188A JP H01268158 A JPH01268158 A JP H01268158A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- heat sink
- semiconductor device
- peripheral edge
- substrate body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置用セラミックス基板に関し、特に放
熱板に半田付けされる裏面メタライズ部の構造に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a ceramic substrate for a semiconductor device, and particularly to the structure of a backside metallized portion soldered to a heat sink.
従来、半導体装置用セラミックス基板は第５図に示すよ
うに概ね構成されている。第５図は従来のセラミックス
基板が放熱板上に半田付けされた状態を示す側断面図で
、同図において１はセラミックス基板本体、２は半導体
素子（図示せず）や外部電極（図示せず）等が半田付け
される表面ノくターン、３は前記セラきツクス基板本体
１の裏面に形成された裏面パターンで、これら表、裏面
パターン２，３は、セラミックス基板本体１にＭ。Conventionally, a ceramic substrate for a semiconductor device has a general structure as shown in FIG. Figure 5 is a side sectional view showing a conventional ceramic substrate soldered onto a heat sink. In the figure, 1 is the ceramic substrate body, 2 is a semiconductor element (not shown) and an external electrode (not shown) ), etc. are soldered, and 3 is a back pattern formed on the back surface of the ceramic substrate body 1. These front and back patterns 2 and 3 are M on the ceramic substrate body 1.
−Ｍｎから々るメタライズ層を焼付けた後、Ｎｉメツキ
することによって形成されている。４は放熱板で、銅等
の熱伝導性の良い金属によって形成されている。なお５
は前記放熱板４と裏面パターン３とを接合させる半田で
ある。- It is formed by baking a metallized layer made of Mn and then plating it with Ni. 4 is a heat sink, which is made of a metal with good thermal conductivity such as copper. Note 5
is solder that joins the heat dissipation plate 4 and the back pattern 3 together.
また、前記セラミックス基板を製造するには、先ず第６
図に示すように焼成前のアルミナを主成分とするセラミ
ックス材料を、一般にグリーン７−トと呼ばれるシート
状に加工する。そしてこのグリーンシートに切断用スナ
ップライン６を設け、焼成させる。なお、このスナップ
２イン６は第７図に示すように側面視路Ｖ字状に形成さ
れたものが多い。しかる後前記スナップライン６に沿っ
てグリーンシートを破砕させることによって、第８図に
示すようにセラミックス基板本体１が得られる。次いで
、とのナラミックス基板本体１０表裏両面にメタライズ
層を形成し、表、襄両パターン２．３を形成するととに
よってセラミックス基板が形成されることに々る。In addition, in order to manufacture the ceramic substrate, first, the sixth
As shown in the figure, a ceramic material whose main component is alumina before firing is processed into a sheet shape generally called a green sheet. Then, a cutting snap line 6 is provided on this green sheet, and the green sheet is fired. Incidentally, many of these snap 2-in-6s are formed in a V-shape when viewed from the side, as shown in FIG. Thereafter, by crushing the green sheet along the snap lines 6, a ceramic substrate body 1 as shown in FIG. 8 is obtained. Next, a metallized layer is formed on both the front and back surfaces of the Naramix substrate main body 10, and patterns 2.3 are formed on both the front and sleeve sides, thereby forming a ceramic substrate.
］７かるに、このように構成さノ１だセラミックス基板
においては、セラミックス基板本体１はグリーンシート
を破砕させるｌ−とによって形成さ力、るため、第８図
に示すようにセラミックス基板本体１の破砕分割面１ａ
にマイクロクラック７が発イトしやすい。さらに、この
セラミックス基板を半田５を介１〜て放熱板４に接合さ
ぜ、表面パターン２」二に半導体素子あるいは外部電極
等を半田付けすると、放熱板４とセラミックス基板本体
１との熱膨張係数の差により、加熱、冷却に応じてセラ
ミックス基板本体１に引張り応力および圧縮応力が繰り
返１〜加えられることになる。このため、セラミックス
基板は、その裏面全面にわ／こり形成された裏面パター
ン３と放熱板４とが崖田付けさＪ上、セラミックス基板
の端部まで半ＥＢ ５によって拘束され〃−状態で放熱
板４ （Ｆ、弾筒ｉ／（接合さ〕′１でいるから、前記
マイクロクラック７に応力が集中す２）（＝とになり、
第９し１に示−す１″）にクラック８が４［じ、半導体
装置の絶縁耐性が劣化）るという問題７５ｓ凌）つた。] 7 However, in the ceramic substrate constructed in this way, the ceramic substrate body 1 is subjected to the force generated by the l− that crushes the green sheet, so that the ceramic substrate body 1 is damaged as shown in FIG. fracture dividing surface 1a of
Micro cracks 7 are likely to occur. Furthermore, when this ceramic substrate is bonded to the heat sink 4 through the solder 5 and a semiconductor element or an external electrode is soldered to the surface pattern 2, thermal expansion of the heat sink 4 and the ceramic substrate body 1 occurs. Due to the difference in coefficients, tensile stress and compressive stress are repeatedly applied to the ceramic substrate body 1 in response to heating and cooling. For this reason, the ceramic substrate radiates heat in a state in which the back pattern 3, which is formed with wrinkles/stiffness on the entire back surface, and the heat sink 4 are attached to a cliff, and are restrained by the half EB 5 up to the end of the ceramic substrate. Since the plate 4 (F, bullet i/(joined)'1), stress concentrates on the micro-crack 72) (=,
The problem of deterioration of the insulation resistance of the semiconductor device (75s) was exceeded by the crack 8 in 1'') shown in No. 9-1.
本発明に係る半導体装置用セラミックス基板は、裏面の
メタライズ部を、セラミックス基板本体における裏面の
周縁部を除く部位に形成ｊ〜、周縁部に未接合部を設り
−たものである。In the ceramic substrate for a semiconductor device according to the present invention, a metallized portion on the back surface is formed at a portion of the ceramic substrate body other than the peripheral edge portion of the back surface, and an unbonded portion is provided at the peripheral edge portion.
〔作用Ｊ
セラミックス基板本体における裏面の周縁部が放熱板に
接合されカいので、この周縁部においては半田付けＫよ
る熱応力の発生が阻止されることになる。[Function J] Since the peripheral edge of the back surface of the ceramic substrate body is bonded to the heat sink, generation of thermal stress due to soldering K is prevented in this peripheral edge.
以下、その構成等を図に示す実施例により詳細に説明す
る。Hereinafter, its configuration and the like will be explained in detail with reference to embodiments shown in the drawings.
第１図は本発明に係るセラミックス基板を示ノー斜視図
、第２図は第１図中ｒｉ−ｎ線断面図、第３図は本発明
に係るセラミックス基板が放熱板上に半田伺けされた状
態を示す側断面図、第４図は未接合部の寸法とクラック
発生率の関係を示すグラフである。これらの図において
第５図ないし第９図で説明しｋものと同一も１−＜は同
等部材については同 符号を付シ１４、ここにｊ、−い
て詳細な説明は省略する。これらの図において、１】は
本発明に係るセラミックス基板で、このセラミックス基
板１１はセラミックス基板本体ｌと、表面パターン２と
、裏面パターン３とから構成されており、とノ裏面パタ
ーン３をセラミックス基板本体１における裏面の周縁部
を除く部位に形成するととによって、との周縁部に未接
合部１２が設けられている。すなわち、とのセラミック
ス基板１１を半Ｆｆ１５を介し〜こ放熱板４に半田付け
すると、第３図に示すように半［（］５は裏面・くター
ン３［：Ｊ、外の部分には接合し７ないため、未接合部
１２と半田５との間に間隙１３が生じるこ７！−になる
。また、前記未接合部１２０幅寸法Ａは、銅からなる放
熱板Ｋ Ａ ＝ｉ法の異方るセラばツクス基板を半［Ｈ
付けし−だザンブルを複数製作し、急激に加熱、冷却さ
せてテストした結果、第４図に示すように、０．５．、
以−ヒであればクランクの発生率が激減されることが判
明した。Fig. 1 is a perspective view showing a ceramic substrate according to the present invention, Fig. 2 is a sectional view taken along the line RI-N in Fig. 1, and Fig. 3 is a ceramic substrate according to the present invention soldered onto a heat sink. FIG. 4 is a side cross-sectional view showing a state in which the bonded portion is joined, and FIG. 4 is a graph showing the relationship between the dimensions of the unbonded portion and the crack occurrence rate. In these drawings, the same reference numerals are given to the same parts as those explained in FIGS. 5 to 9, and the detailed description thereof will be omitted. In these figures, 1] is a ceramic substrate according to the present invention, and this ceramic substrate 11 is composed of a ceramic substrate body 1, a front surface pattern 2, and a back surface pattern 3. By forming the main body 1 at a portion other than the peripheral edge of the back surface, an unjoined portion 12 is provided at the peripheral edge of the main body 1 . That is, when the ceramic substrate 11 is soldered to the heat sink 4 through the half Ff15, as shown in FIG. As a result, a gap 13 is created between the unbonded part 12 and the solder 5. Furthermore, the width dimension A of the unbonded part 120 is determined by the heat dissipation plate K A =i method made of copper. The anisotropic ceramic substrate is semi-[H
As a result of making a number of attached zambles and testing them by rapidly heating and cooling them, as shown in Fig. 4, 0.5. ,
It has been found that the incidence of cranking can be drastically reduced if this is done.
したがって、セラミックス基板１１における裏面の周縁
部が放熱板４に接合されないので、この周縁部において
は半田付けによる熱応力の発生が阻止されることにカる
。Therefore, since the peripheral edge of the back surface of the ceramic substrate 11 is not bonded to the heat sink 4, generation of thermal stress due to soldering is prevented in this peripheral edge.
また、セラミックス基板本体１を焼成前のグリーンシー
ト状態で全周を金型（図示せず）により拐ち抜くζ、と
によって成形すれば、破砕分割させる必要がなくｉるた
め、マイクロクラックの発生を防止することができる。Furthermore, if the entire circumference of the ceramic substrate body 1 is formed in a green sheet state before firing with a mold (not shown), there is no need to crush and divide the ceramic substrate body 1, thereby causing micro-cracks. can be prevented.
このようにして成形されたセラミックス基板本体１を使
用して本発明の−）−ラミックス基板を製作すると、ク
ラックの発生率がより低く々す、信頼性の高い半導体装
置を得ることができる。When the ceramic substrate body 1 molded in this manner is used to manufacture the -)-RAMICS substrate of the present invention, a highly reliable semiconductor device with a lower incidence of cracks can be obtained.
々お本実施例では、セラミックス基板本体１にＭＯ−Ｍ
ｎから々るメタライズ層が形成されたセラミックス基板
について説明１−２だが、メタライズ層の種類はどのよ
うなものでも同等の効果が得られ、また、セラミックス
基板本体１の表面に電極を直接接合する型式のセラミッ
クス基板であってもよく、同等の効果が得られる。In this embodiment, MO-M is mounted on the ceramic substrate body 1.
Explanation 1-2 describes the ceramic substrate on which a metallized layer of various types is formed, but the same effect can be obtained with any type of metallized layer, and electrodes can be bonded directly to the surface of the ceramic substrate body 1. A type of ceramic substrate may also be used, and the same effect can be obtained.
以上説明したように本発明の半導体装置用セラミックス
基板は、裏面のメタライズ部をセラミックス基板本体に
おける裏面の周縁部を除く部位に形成し、周縁部に未接
合部を設けたため、セラミックス基板本体における裏面
の周縁部が放熱板に接合されないので、この周縁部にお
いては半田付けによる熱応力の発生が阻止されることに
なる。As explained above, in the ceramic substrate for a semiconductor device of the present invention, the metallized portion on the back surface is formed in a portion of the ceramic substrate body other than the peripheral edge portion of the back surface, and an unbonded portion is provided in the peripheral edge portion. Since the peripheral edge portion of the heat sink is not joined to the heat sink, generation of thermal stress due to soldering is prevented at this peripheral edge portion.
したがって、セラミックス基板本体の周縁部からクラッ
クの発生が減少されることになシ、絶縁耐性が高く信頼
性の高い半導体装置が得られる。Therefore, the occurrence of cracks from the peripheral edge of the ceramic substrate body is reduced, and a semiconductor device with high insulation resistance and high reliability can be obtained.
第１図は本発明に係るセラミックス基板を示す斜視図、
第２図は第１図中■−■線断面図、第３図は本発明に係
るセラミックス基板が放熱板上に半田付けされた状態を
示す側断面図、第４図は未接合部の寸法とクラック発生
率の関係を示すグラフ、第５図は従来のセラミックス基
板が放熱板上に半田付けされた状態を示す側断面図、第
６図は従来のセラミックス基板を成形するためのグリー
ンシートを示す平面図、第７図は第６図中■−■線断面
図、第８図は従来のセラミックス基板本体を示す平面図
、第９図は従来のセラミックス基板が放熱板上に半田付
けされた状態を示す平面図である。
１・・・・セラミックス基板本体、３・・・・裏面パタ
ーン、４・・・・放熱板、５・・・・半田、１１・・・
・セラミックス基板、１２・・・・未接合部。FIG. 1 is a perspective view showing a ceramic substrate according to the present invention;
Fig. 2 is a sectional view taken along the line ■-■ in Fig. 1, Fig. 3 is a side sectional view showing a ceramic substrate according to the present invention soldered onto a heat sink, and Fig. 4 is a dimension of the unbonded part. Figure 5 is a side cross-sectional view showing a state in which a conventional ceramic substrate is soldered onto a heat sink, and Figure 6 is a graph showing the relationship between the conventional ceramic substrate and the crack occurrence rate. 7 is a cross-sectional view taken along the line ■-■ in FIG. 6, FIG. 8 is a plan view showing a conventional ceramic substrate body, and FIG. 9 is a conventional ceramic substrate soldered onto a heat sink. It is a top view showing a state. 1... Ceramic substrate body, 3... Back pattern, 4... Heat sink, 5... Solder, 11...
-Ceramics substrate, 12...Unbonded part.
Claims (1)
装置用セラミックス基板において、前記メタライズ部を
、セラミックス基板本体における裏面の周縁部を除く部
位に形成し、周縁部に未接合部を設けたことを特徴とす
る半導体装置用セラミックス基板。In a ceramic substrate for a semiconductor device in which a metallized portion on the back surface is soldered to a heat sink, the metallized portion is formed in a portion of the ceramic substrate body other than the peripheral edge of the back surface, and an unbonded portion is provided at the peripheral edge. Features of ceramic substrates for semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63097581A JPH0766948B2 (en) | 1988-04-20 | 1988-04-20 | Ceramic substrate for semiconductor device and semiconductor device provided with this ceramic substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63097581A JPH0766948B2 (en) | 1988-04-20 | 1988-04-20 | Ceramic substrate for semiconductor device and semiconductor device provided with this ceramic substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01268158A true JPH01268158A (en) | 1989-10-25 |
| JPH0766948B2 JPH0766948B2 (en) | 1995-07-19 |
Family
ID=14196211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63097581A Expired - Lifetime JPH0766948B2 (en) | 1988-04-20 | 1988-04-20 | Ceramic substrate for semiconductor device and semiconductor device provided with this ceramic substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0766948B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62103266U (en) * | 1985-12-19 | 1987-07-01 |
-
1988
- 1988-04-20 JP JP63097581A patent/JPH0766948B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62103266U (en) * | 1985-12-19 | 1987-07-01 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0766948B2 (en) | 1995-07-19 |
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