JPH01268381A - Teletext signal sampling circuit - Google Patents

Abstract

PURPOSE:To constantly sample correct data with the clock of an optimum phase by holding a sampling clock coinciding with a broadcasting normalization and obtaining the delay time of sampling data based on its own TELETEXT signal. CONSTITUTION:The sampling clock for separating the one block of a CRI(Clock Run ln) is separated into 16 phases, for instance is formed by a sampling clock forming circuit and the exclusive OR of the data obtained by inverting the data sampled by the first half of the eight phases and the data sampled by the latter half of the eight phases is taken by a decoder 8. In an optimum data selecting circuit 11, the data by the sampling clock of the phase corresponding to the vector value of the decoder 8 is selected as optimum data. When the output of the exclusive OR is not stable, the sampling clock of the phase corresponding to the vector value of either one data is selected as the optimum phase. Further, the data of a plurality of the blocks of the CRI averaged by an average circuit 14, thereby, a malfunction due to noise is reduced as much as possible.

Description

[Detailed Description of the Invention] "Industrial Application Field" The present invention is for extracting teletext data from a received video signal by sampling the teletext data precisely in phase with one teletext data. This invention relates to a teletext signal extraction circuit.

``Prior art'' In conventional teletext signal extraction circuits, the sampling clock for extracting teletext data from the received video signal is created by multiplying 3.58M& of color burst by 875 or by doubling CRI. The phase of this sampling clock was shifted according to the input data.

"Problem to be Solved by the Invention" For this reason, the waveform of the received video signal is distorted due to ghosts, group delay noise, etc., resulting in CRI (C1ock RunIn
), or if color bursts cannot be extracted stably, the problem is that teletext data contains errors.

The present invention enables even if a phase shift occurs between the sampling clock and the character signal due to ghosts, group delay, noise, etc.
The purpose is to extract teletext data using a correct sampling clock that matches the teletext signal.

"Means for Solving the Problem" The present invention provides a circuit for extracting teletext data from a received video signal as binary data using a sampling clock. A sampling clock forming circuit generates a sampling clock conforming to a fixed broadcasting standard and sequentially delays the phase by a predetermined angle to form n-phase sampling clocks, and each sampling clock of this sampling clock forming circuit is used to generate the received video. a sampling circuit that samples binary data obtained by slicing a signal and delays the data according to the phase of a sampling clock, and the first half of the n phases.
A decoder that generates an optimal vector by inverting one of the /2n phase binary data and the latter half 1/2n phase binary data and sequentially performing an exclusive OR; The decoder includes an exclusive OR circuit and a selection circuit that selects optimal data for the sampling circuit, and when the outputs of the exclusive OR circuit all match, the decoder determines that the vector is undefined and selects either the first or second half of the data. A circuit for determining the undefined vector to be selected; an averaging circuit for averaging the data selected by the undefined vector determining circuit over multiple CRI sections to prevent operational instability due to noise; and an averaging circuit for determining the optimum phase using the averaged data. and an optimal vector output circuit for determining the optimum vector output circuit.

"Operation" On the other hand, the received teletext signal is sliced by a slicing circuit and converted into binary data. On the other hand, a sampling clock forming circuit forms a sampling clock in which one section of the CRI is separated into, for example, 16 phases. That is, assuming that one section of the CRI is 175×2 nsec and the period of the basic sampling clock is 175 nsee, sampling clocks sequentially delayed by 175/8 and 22 nsee from the basic clock are formed. Then, the decoder performs an exclusive OR operation between the inverted data of the data sampled using the first 8-phase clocks and the data sampled using the latter 8-phase clocks. The selection circuit selects the data sampled by the sampling clock whose phase corresponds to the vector value of this decoder as the optimum data. When the exclusive OR output is indeterminate, the values of the first and second halves are exactly the same, so the sampling clock whose phase corresponds to the vector value of one of the data is selected as the optimum phase.

Furthermore, by averaging the data of multiple CRI sections using an averaging circuit, malfunctions due to noise are reduced as much as possible.

"Example" Hereinafter, one embodiment of the present invention will be described based on the drawings.

In Figure 1, (1) is the input terminal for the teletext signal;
2) is a slice reference signal input terminal.

These input terminals (1) (2) are coupled to a slicing circuit (3) which slices the teletext signal into binary data. (4) is a sampling clock forming circuit, and this sampling clock forming circuit (4) uses a basic clock with a period Tc and sequentially Tc/8 from this basic clock.
An 8-phase clock with a delayed clock is formed. Note that the Tc is a period of 5.73 MHz, which is 815 times the color burst period number of 3.58 MHz, and is approximately 1750 Se.
It is e. Therefore, the phase difference between each phase is 175/8 22n see. These slice circuit (3) and sampling clock forming circuit (4) are coupled to a sampling circuit (5) and a first latch circuit (6).

This first latch circuit (6) is connected to a second inverting latch circuit (7), an exclusive OR circuit (9) of the decoder (8), and a second
memory (10) and a selection circuit (11).

The exclusive OR circuit (9) connects the first memory (12) of the decoder (8) and the Bertol indefinite determination circuit (13).
The output of the vector indefinite determination circuit (13) selects either the first memory (12) or the second memory (10). These first and second memories (12) (
10) is an averaging circuit (14) and an optimal vector output circuit (
The selection circuit (11) selects the optimum data via
), and this selection circuit (11) is coupled to a data output terminal (16).

The operation of the above configuration will be explained. When a teletext signal as shown in Fig. 2 (a) and its enlarged view (d) is input from the input terminal (1) to the slicing circuit (3) and sliced using the reference signal input to the input terminal (2), , second
The cycle of the single teletext signal that is converted into binary data of 1 and O as shown in Figure (e) is 2Tc, and the sampling clock generation circuit (4) outputs the sampling clock (1) with cycle Tc and Tc Sampling clocks (2) to (8) whose phases are shifted by /g are output. Note that Tc is
5 which is 815 times the color burst frequency of 3.58In
, 73M1 (about 175n ssc in the period of z, therefore, the phase difference between each clock (1) to (8) is 175n ssc)
/8 valve 22n see.

Further, the interval of CRI (CLock Run In) is 2Tc, and the intervals are sequentially 1st interval, 2nd interval, 3rd interval, and 4th interval as shown in FIG. 2(e). As a result, one section is separated into 16 phase sampling clocks. Slice data of a teletext signal is sampled using the first 8 phase clocks among 16 phase sampling clocks. If the teletext data is as shown by the solid lines in FIGS. 3(a) and 3(b), the first eight phases are ooo.

It becomes 0011. This is reversed by the second inversion latch circuit (7) via the first latch circuit (6) and becomes 11111100.
becomes. When sampling the latter 8 phases in the same way, it becomes 11111100, and the first and second latch circuits (
6) The output of (7) is exclusive-ORed for each phase, and oo
oo.

It becomes 011. Similarly, the outputs for the four sections are averaged by the averaging circuit (14), and thereby the optimal vector is outputted by the optimal vector output circuit (15).

For example, if this optimal vector is 2, the 1 selection circuit (11
), data based on the second sampling pulse (2) is outputted to the output terminal (16) as optimal data.

Next, the teletext signal and the sliced binary data are
In the case shown by the dotted lines in Figures (a) and (b), the first 8 phases are 11
It becomes 111111, and it is reversed to become oooooooo. The latter eight phases are ooooooooo. Therefore, the vector undefined determination circuit (13) outputs a vector undefined signal. Then, one of the memories, for example the second
The output of the memory (10) is sent to the averaging circuit (14), and in the same manner, the optimum vector is obtained by averaging four times and the optimum data is selected.

In the embodiment, the first, second, .
Although the third and fourth sections are averaged, the invention is not limited to this. For example, the fifth, sixth, and seventh sections with a 180 degree phase delay may be set and averaged seven times. You can.

"Effects of the Invention" As described above, the present invention is configured to hold a sampling clock that conforms to the broadcasting standard and to obtain the delay time of sampling data based on the teletext signal itself.
Horizontal synchronization signal, color burst signal, CRI due to jitter etc.
Even if signal distortion occurs, accurate data can always be extracted using a clock with the optimal phase. In addition, the averaging circuit
By averaging multiple sections, malfunctions due to noise can be reduced and an accurate phase can be determined.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a teletext signal extracting circuit according to the present invention, and FIGS. 2 and 3 are waveform diagrams of various parts. (1)... Teletext signal input terminal, (2)... Reference signal input terminal, (3)... Slice circuit, (4)...
・Sampling clock formation circuit, (5)...sampling circuit, (6)...first latch circuit, (7)...
・Second inverting latch circuit, (8)...decoder, (9)
...Exclusive OR circuit, (1,0)...Second memory, (11)...Optimum data selection circuit, (12)...
First memory, (13)...Vector indefinite determination circuit, (
14) . . . Multiplication circuit, (15) . . . Optimal vector output circuit, (16) . . . Output terminal. Applicant: Fujitsu General Ltd., District 2, Figure 3

Claims (1)

[Claims] (1) In a circuit that extracts teletext data from a received video signal as binary data using a sampling clock, a sampling clock forming circuit that sequentially delays the phase of the sampling clock by a predetermined angle to form n-phase sampling clocks. and sampling binary data obtained by slicing the received video signal with each sampling clock of this sampling clock forming circuit,
a sampling circuit that takes out delayed data of n phases; and a sampling circuit that inverts one of the binary data of the first 1/2n phase and the binary data of the latter 1/2n phase among the n phases. The decoder includes a decoder that sequentially performs exclusive OR to generate an optimal vector, and a selection circuit that selects optimal phase data of the sampling circuit based on the output of the decoder, and the decoder includes an exclusive OR circuit and A vector undefined determination circuit determines that the vector is undefined when all outputs of the OR circuit match, and selects either the first or second half of the data. 1. A teletext signal sampling circuit comprising: an averaging circuit for averaging a plurality of CRI sections; and an optimum vector output circuit for determining an optimum phase based on the averaged data.