JPH01276263A - Bus communicating device - Google Patents

Abstract

PURPOSE:To cause the other device to use a bus until a data return from a bus slave is executed by causing a bus master to release the bus without waiting for the data return from the bus slave when a read request from the bus master is executed. CONSTITUTION:In the period of L1-L2, for example, a bus master Ma sends a data request to a bus slave Sa, the using right of the bus is released without waiting for the response of the bus slave Sa, thereby, the data request to a bus slave Sb can be continuously sent from another bus master Mb in the period of L3-L4, and the using efficiency of the bus is improved. Even when plural bus masters Ma and Mb are made into a response waiting condition from the bus slaves Sa and Sb, by an identification number, the bus master can distinguish the bus slave whose response is the data which it requests itself. Thus, the responses from the bus slaves Sa and Sb returned in periods L5-L6 and L7-L8 can be correctly fetched.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Field of Application) The present invention provides a system in which a plurality of bus masters communicate with a plurality of bus slaves via a common bus based on a predetermined arbitration operation. The present invention relates to a bus communication device.

(Prior Art) For example, the VME-BUS system is known as a bus communication system in which a plurality of bus masters requesting data reading/writing and bus slaves performing data reading/writing communicate via a common bus. It is being In such a bus communication system, since information cannot be sent from multiple bus masters and bus slaves to one bus at the same time, bus usage rights are arbitrated between multiple bus masters when reading data. The bus master that acquired the bus monopolized the bus and did not release the right to use the bus until data was returned from the bus slave.

However, according to this method, no other bus master can acquire the right to use the bus after the bus master requests data from the bus slave until the data is read. A data request is sent to one block Sa from which data is read. M2
The transmission of the data request is completed, but since there is no data return from the bus slave Sa, the bus is not released. M
Data is returned from the bus slave Ma from 3 to M4, and when this is completed, the bus master Ma releases the bus. Bus master Mb waits for the bus to be released by bus master Ma, acquires the right to use the bus at M5, and issues a data request to bus slave sb. Although the transmission of the data request is completed in M6, the bus is not released because no data is returned from the bus slave sb. In this way, the bus masters Ma and Mb are respectively M1-M4 and M5-
It occupies the bus during M9.

However, if the bus is released without waiting for data to be returned from the bus slave, there may be multiple bus masters waiting for data to be returned from the bus slave at the same time. The problem is that it cannot be identified.

After sending a communication request, the bus master occupies the bus until it receives a response from the bus slave, so systems with bus slaves that respond slowly have the problem of not being able to use the bus efficiently. there were.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus communication device that can efficiently use a bus even when a bus slave responds slowly to a communication request from a bus master.

[Structure of the Invention] (Means for Solving the Problems) The present invention does not wait for the data return from the bus slave when there is a read request from the bus master. One identification number is assigned to a pair of communications consisting of. This identification number requests data from the bus master stub,
When transmitting the identification number, the bus master acquires the right to use the bus through arbitration. After completing the data request and sending the identification number, the bus master releases the bus. When the bus slave receives a data request, it stores the identification number sent at that time and begins a read operation.

When the bus slave completes the read operation, it acquires the right to use the bus through an arbitration operation, and when it acquires the right to use the bus, it sends the requested data to the bus along with the stored identification number. The bus slave then releases the bus. When the bus slave sends an identification number on the bus that is the same as the identification number sent with the data request, the bus master takes in the data on the bus as the requested data.

(Operation) According to the present invention, when a bus master issues a data request to a bus slave, by acquiring the right to use the bus,
Data requests and identification numbers are never illegally transmitted to bus slaves. During bus thread operation, other bus masters can issue data requests to other bus slaves, and other bus slaves can send data back to other bus masters.

When the bus slave sends back data, the bus slave acquires the right to use the bus, so that the data sent by the bus slave onto the bus will not be invalid.

The bus slave acquires the right to use the bus, sends the stored identification number sent along with the data request by the bus master, and sends out the stored identification number along with the data return to notify that the data is requested by the bus master.

The bus slave then releases the right to use the bus, thereby completing the reading of the pair of data.

As a result, as shown in FIG. 9, for example, bus master Ma can send a data request to bus slave Sa during the L1 to L20 period and release the right to use the bus without waiting for a response from bus slave Sa. , data requests can be continuously sent from other bus masters Mb to bus slave sb during periods L3 to L4, improving bus usage efficiency.

Since it is possible to distinguish whether the responses from the bus slaves are the data requested by the bus slave, the responses from the bus slaves Sa and Sb sent back during the periods L5 to L6 and L7 to L8 can be accurately captured.

(Example) Hereinafter, an example of the present invention will be described based on the drawings.

FIG. 1 is a diagram showing the configuration of a bus communication system according to an embodiment of the present invention. This system uses a well-known daisy chain as an arbitration mechanism for bus usage rights, with a bus master LA.

1b and bus slaves 2a and 2b (hereinafter collectively referred to as "devices") are connected to a common bus 3, and these devices are connected to a bus request signal (BREQ) signal line 4 for bus arbitration and a bus acknowledge signal. (BGRT)
They are connected in a chain via a signal line 5. The common bus 3 includes an address (ADI?S) bus 3a, a data (DATA) bus 3b, an address strobe (As) signal line 3c indicating that the address bus is valid, and an address strobe (As) signal line 3c indicating that the data bus data is valid. Data acknowledgment (DACK) signal line 3d, read/write (R/W) signal line 3 indicating data read or write operation
Consists of e. The priority order of devices during bus arbitration is bus master las 1b, bus slave 2 a
The order is s and 2b. For this reason, Bl? to ensure the use of common bus 3? The EQ signal line 4 is connected from the bus request output (BRO) terminal of the device with low priority (left side in the figure) to the bus request input (Bl?I) of the device with high priority (right side in the figure).
) terminal to approve the request.
Conversely, the signal line 5 is connected from the bus grant output (BGO) terminal of the high priority device to the bus grant input (BGI) terminal of the low priority device. Further, the bus busy signal (BBLISY) is a signal that is transmitted to all devices when any device occupies the common bus 3.

In this system, when a device acquires the right to use the bus, it enables the BRO terminal and waits for the BGRT signal to return, provided the BBUSY signal is disabled. At this time, the value of the terminal is not communicated. Furthermore, each device transmits the value of the BGI terminal to the '-BGO terminal when there is no request to use the bus, but when there is a request to use the bus, the value of the BGI terminal is transmitted to the BGO terminal.
The value of the terminal is always enabled and BGI is set to BGO terminal.
Does not convey terminal values.

Therefore, if BREQ signals are sent from multiple devices at the same time, only the device with the highest priority (on the right side in the figure) receives the BCRT signal. If the BGI terminal of the device that sent the BREQ signal is enabled, the right to use the bus has been acquired, and BBUSY is enabled. An arbitration mechanism is constructed by such a method.

FIG. 2 shows the configuration of bus masters la and lb.

The bus slave address sent from CPU II is
It is output to the address bus 3a via the address buffer 12, and is also stored in the ID register 3 as an identification number. Further, input/output between the CPU 1 and the data bus 3b is performed via the data latch buffer 14. I'll let 1'6 know. The arbitration synchronization control circuit 16 performs the above-mentioned bus arbitration control, and the bus slave includes a memory 21 for reading and writing data in response to requests from the bus master, for example. The masked slave determines whether the address on the address bus 3a is its own address using the address decoder 22, and if the address is addressed to itself, the arbitration synchronization control circuit 23
Under the control of
Incorporate into. Data is output between the memory 21 and the data bus 3b via the data buffer 26. When this bus slave returns data to the bus master, it uses the identification number stored in the ID register 25 as an ID.
The right to use the bus is granted by data operation via the buffer 24.
When acquired at O, the BBUSY signal is enabled. The bus master raises the As signal at N1 to inform the bus slave that the address is valid, and stores the address in the internal ID register 12 as an identification number. At N1, the bus slave stores the contents of the address bus 3a in the ID register 25 as an identification number. After the Tm time has elapsed, the bus master disables the address, As signal, and BBUSY signal at N2 to release the bus.

When the bus slave finishes reading the data, it acquires the right to use the bus at N3 through an arbitration operation, and registers the ID register 25.
The identification number stored in the memory 21 is sent to the address bus 3a, and the data read from the memory 21 is sent to the data bus 3b.

Then, raise the As signal and DACK signal at N4,
Notify the bus master that the identification number and data are valid. Thereafter, after the Ts time has elapsed, the address, data, As signal, and DACK signal are disabled at N5 to release the bus.

can be released.

FIG. 5 shows the configuration of a bus communication system according to another embodiment of the present invention. This system uses an identification number that is separate from the address of the bus slave.

Also, like the above embodiment, this system also includes a daisy chain arbitration mechanism. In this system, bus masters 41a, 41b and bus slaves 42
a.

As a common bus 43 to which 42b are commonly connected, an address/data bus 3f which shares an address bus and a data bus is used instead of providing them independently, and an ID bus 3g for transmitting an identification number and its IDA indicating validity/invalidity
A cK signal bus 3h is provided.

FIG. 6 shows bus masters 41a and 41 in the above system.
The configuration of b is shown. The bus slave address and data sent from the CPU 51 are output to the address/data bus 3f via the address/data/latch buffer 52. The arbitration controller 55, together with the decoder,
When an identification number is sent from the bus master onto the ID bus 3g, a corresponding flag is set, and when an identification number is sent back from the bus slave onto the ID bus 3g, the corresponding flag is reset. Priority encoder 5
6 is when the bus master sends a bus use request,
The smallest identification number among the reset flags in the identification number flags 54 is selected and outputted to the identification number register 57. This identification number is stored in the identification number register 57 and sent to the ID bus 3g via the buffer 58. At this time, the comparator compares the identification number on the ID bus 3g with the identification number stored in the identification number register 57, and if the two match, it notifies the CPU 51 via the arbitration synchronization control circuit 53. Thereby, the data on the address/data bus 3f is read via the CPU 51 and the address/data latch buffer 52.

If so, under the control of the arbitration synchronization control circuit 62, the ID
The identification number on the ID bus 3g is stored in the register 63. Then, the address is supplied to the memory 65 via the address/data latch buffer 64, and the read data is transferred via the address/data latch buffer 64 to the address/data bus 3.
Send to f. At this time, the identification number stored in the ID register 63 is transferred to the buffer 66. When the bus master making a return request via the ID bus 3g obtains bus usability at PO through an arbitration operation, the BBUSY signal becomes enabled. The bus master is the AS signal and IDAC at Pl.
The K signal is raised to notify the bus slave that the address and identification number are valid, and the identification number is stored in the internal identification number register 12. The bus slave uses Pl to store the contents of the ID bus 3g as an identification number in the ID register 63-=. After the time Tm has elapsed, the bus master disables the address, AS signal, IDAcK signal, and BBtlSY signal at 1 stroke < 1 \ 1 = -P2 and releases the bus.

When the bus slave finishes reading the data, it acquires the right to use the bus at P3 through an arbitration operation, and registers 63
The identification number stored in the memory 65 is sent to the ID bus 3a, and the data read from the memory 65 is sent to the address/data bus 3f. Then, at P4, the IDAcK signal and the DACK signal are raised to notify the bus master that the identification number and data have become valid. After that, T
After m hours have elapsed, the ID bus, data, and IDAC are
Disable the K and DACK signals to release the bus.

In this way, according to this embodiment, even in a bus configuration where the data bus and address bus are shared in a time-sharing manner, by providing the ID bus, the bus master can easily send data back from the bus slave. You can release the bus without waiting.

Note that the present invention is effective in systems where the time between data request from the bus master and data return from the bus slave is slower than the arbitration time. By applying the method of the present invention to memory access, the effects of the present invention can be fully exhibited.

It goes without saying that the present invention is also applicable to systems in which bus arbitration is performed using other arbitration mechanisms, rather than the daisy-chain arbitration mechanism described above.

[Effects of the Invention] As described above, according to the present invention, when there is a read request from the bus master, the bus master releases the bus without waiting for data to be returned from the bus slave. Other devices can use the bus until this happens. Therefore, bus usage efficiency is improved and processing speed can be increased.

4. Brief explanation of the drawings Figures 1 to 4 show a bus according to an embodiment of the present invention.
These are diagrams to explain the communication system. Figure 1 is an overall block diagram of the system, and Figure 2 is a diagram showing the system.
Figure 9 is a timing diagram showing the operation of the system; Figure 9 is a timing diagram for explaining the communication method of the present invention;
Figure 0 is for explaining the conventional communication system. 3.43...shared bus, 3a...address bus, 3b...data bus, 3c...address strobe band line, 3d...data acknowledgment Signal line, e...Read/write signal line, 3f...Address/-tabus, 3g...I
D bus, 3h...ID acknowledgment signal line.

Applicant: Director of the Agency of Industrial Science and Technology Kozo Iizuka

Claims (1)

[Claims] Consists of a plurality of bus masters that request read/write data, a bus slave that performs the read/write requested by the bus masters, a bus that connects these in common, and a bus arbitration device that arbitrates the right to use this bus. In the bus communication device, the bus master secures the right to use the bus when requesting data, generates and outputs an identification number that identifies the transaction, stores it internally, and releases the right to use the bus. , when the output identification number is sent back onto the bus, the data on the bus at that time is read, and the bus slave stores the identification number sent in conjunction with the data request specifying itself. Then, after securing the right to use the bus when returning the data and returning the data along with the memorized identification number on the bus,
A bus communication device characterized in that it releases a bus.