JPH01278073A - Mis type transistor and its manufacture - Google Patents

Abstract

PURPOSE:To increase breakdown voltage, and improve the life of an element by arranging the gate electrode of an MIS type transistor on also the upper part of a comparatively low concentration region turning to a part of a source and a drain. CONSTITUTION:The layer 12 of a semiconductor film operating as a part of a gate electrode B is arranged on also regions 4, 5 doped with comparatively low concentration of inverse conductivity type with respect to a source 2 side and drain 3 side semiconductor substrate. Thereby, the electric field of drain 3 of an MIS type transistor is relieved, and the breakdown voltage is increased. In addition, the current driving capability in the triode region and the prentode region of transistor is not decreased, and the life of an element can be improved by reducing the deterioration of drain characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a MIS type transistor and its manufacturing method.

[Conventional technology]

Figure 6 is based on IEEE Transa by TSANG etc.
cti.

n Electron Devices VOL, ED
-291982, a Lightly Doped drain (
1 is a sectional view showing the structure of a MOS transistor (hereinafter abbreviated as LDD).

In FIG. 6, an N+ source region 2 and an N+ drain region 3, which are deeply N-doped, are formed in the main surface of a P- semiconductor substrate 1, which is lightly doped P-type. Adjacent to the N+ source region 2 and the N+ drain region 3, respectively,
Impurity concentration from 1017/cm to 1018/Cm3
N-type shallowly doped N” diffusion region of the order of 4.5
is formed.

Further, the vicinity of the main surface of the P- semiconductor substrate 1 between the N- diffusion regions 4.5 is defined as a channel region 6.

A gate electrode 8 made of polysilicon is provided above channel region 6 with gate oxide film 7 in between. A sidewall 9 formed of an oxide film continuing from the gate oxide film 7 is provided in contact with the sidewall of the gate electrode 8. N-
The end of the diffusion region 144.5 on the channel region 6 side is located at a distance δ from just below the end of the gate electrode 8, about several hundred people inside the channel region 6, respectively.

FIG. 7 is a process sectional view showing a method of manufacturing the conventional N-channel LDDMOS transistor shown in FIG. In FIG. 7(a), an oxide film and polysilicon are sequentially laminated on the main surface of a P- semiconductor substrate 1, and then a gate oxide film 7 and a gate electrode 8 are formed by anisotropic etching. Next, in FIG. 7(b), ions of an N-type impurity such as phosphorus or phosphorus are implanted into the P-semiconductor substrate 1 using the gate electrode 8 as a mask at a dose of 1013/C112 order.

Next, Fig. 7 (C) 4: #l+'%T, CV D (Ch
An oxide film 10 is formed by a chemical vapor deposition method. Then, in FIG. 7(d), the oxide film 10 is anisotropically etched to leave only the sidewall portion of the gate electrode 8 as the sidewall 9, and remove the other portions.

Thereafter, using the gate electrode 8 and the sidewall 9 as a mask, N-type impurities with a height of 1111 are implanted into the P- semiconductor substrate 1. Next, in FIG. 7(e), the N-type impurity ions implanted in FIGS. 7(b) and 7(d) are diffused by heat treatment to finally obtain the structure shown in the figure.

Next, the principle of the LDD structure will be explained. Figure 8 (a
) and (b) are configuration diagrams showing the operating states of the DDMOS transistor in the pentode region and triode region, respectively. P− semiconductor substrate 1 and N+ source region 2 are connected to GND
Grounded to potential (Ov). N1 drain area 1a3
A power supply voltage, for example 5V, is applied to. Further, a gate voltage V is applied to the gate electrode 8. is given.

Further, a depletion layer 11 exists in the PN junction.

The width W of the depletion layer is given by the following equation (1).

...(1) In formula (1), NA is the acceptor concentration, No is the donor concentration, v8 is the reverse bias voltage, VD is the diffusion potential of the PN junction, ε8 is the dielectric constant of the semiconductor, and q is the electric current. It's i4 listening.

In equation (1), if the N-type impurity concentration N is significantly higher than the P-type impurity concentration NA, then N, and if the N-type impurity concentration N and the P-type impurity concentration NA are almost equal, then N. The following approximate formula (3) is obtained as ND〒NA.

When the drain is composed of only N+drain region 143,
The width W of the depletion layer at the drain end of the channel region 6 is expressed by the formula (2
) is given by Furthermore, when an N-diffusion region 5 is provided as in an LDD type MOS transistor, the width W of the depletion layer is calculated by the formula (
3) is given by If the reverse bias voltage ■8 is the same, N
- The LDD type MoS transistor provided with the diffusion region 5 has a larger width W, and the electric field applied to that portion is smaller. Therefore, breakdown due to the high electric field occurring between the drain and channel regions is less likely to occur.

In this way, the problem of a decrease in drain breakdown voltage due to miniaturization is solved by the LDD structure.

Next, the operation will be explained. Drain voltage■.

When V is larger than the gate voltage v6, the transistor operates in the triode region as shown in FIG. 8(a). In the triode region, in addition to the inversion layer formed in the channel region 6 (the shaded area in the figure), a high-resistance depletion layer appears on the drain side of the channel region 6. In addition to this depletion layer, N- diffusion regions ti! on the source side and drain side! 4.5 becomes a parasitic resistance other than the channel region 6, which causes a decrease in drain current.

Further, when the drain voltage VD is sufficiently lower than the gate voltage VG, the transistor operates in the triode region as shown in FIG. 8(b). In the triode region, an inversion layer (shaded area in the figure) is formed in the channel region 6 in an almost - shape, and the resistance in the channel region 6 is small, but the N- diffusion regions 4°5 on the source side and the drain side have a parasitic resistance. This also lowers the drain current and lowers the current driving ability of the transistor.

[Problem to be solved by the invention]

Since the conventional LDDMO8+- transistor is configured as described above, it is structurally composed of an N- diffusion region 1ii! 4.5 degrees becomes a parasitic resistance, which causes a problem in that the drain current decreases and the current driving ability of the transistor deteriorates.

Further, the electric field near the drain generates hot carriers having energy greater than that in a thermal equilibrium state. These hot carriers are generated near the N- diffusion region 5 on the drain side, and some of them are injected into the lower part of the sidewall 9 on the drain side. Due to the electric field caused by the carriers trapped in the energy level in the oxide film below the sidewall 9, the vicinity of the surface of the N- diffusion region 5 is depleted. As a result, the threshold value becomes high, and even in the operating state, the conductance becomes small due to the high resistance part of this N- diffusion region 5, which deteriorates the drain characteristics roughly and shortens the life of the device that can withstand practical use. There was a problem with reliability.

This invention was made to solve the above-mentioned problems, and as in the case of conventional transistors, the purpose is to reduce the drain electric field of the MIS type transistor and increase the withstand voltage.

Can be used as well as a transistor triode.

It is an object of the present invention to provide a MIS type transistor and a method for manufacturing the same, which can significantly improve the life of the element by not reducing the current driving ability in the triode region and by reducing the deterioration of drain characteristics.

[Means to solve the problem]

This MIS type transistor for sale includes a semiconductor substrate of a first conductivity type, and first and second semiconductor substrates of a conductivity type opposite to that of the semiconductor substrate, which are formed at a predetermined interval in the main surface of the semiconductor substrate. a region within the main surface of the semiconductor substrate;
and third and fourth regions formed adjacent to and between the second region and having a lower impurity concentration and the same conductivity type as the first and second regions; a fourth region and an insulating film formed on the main surface of the semiconductor substrate therebetween; A fourth region and a gate electrode formed on the upper side of the main surface of the semiconductor substrate between the fourth region and the insulating film are provided.

Further, the method for manufacturing an MIS transistor according to the present invention includes the steps of forming a first insulating film on the main surface of a semiconductor substrate of a first conductivity type, and forming a first insulating film on the first insulating film to become a gate electrode. forming a second insulating film on the first semiconductor film, further applying a resist thereon and patterning it, and masking the patterned resist. etching the second insulating film and the first semiconductor film to leave only the resist portion; and etching the semiconductor substrate at a relatively low concentration using the pattern formed by the etching as a mask. a step of introducing an impurity of a conductivity type opposite to that of the first semiconductor film; a step of removing the resist and forming a second semiconductor film on the entire surface; a step of performing anisotropic etching to remove the remaining portions; and a step of etching the semiconductor substrate with the second insulating film, the first semiconductor film, and the second semiconductor film on the side wall portion thereof as a mask. This method includes a step of introducing an impurity of a conductivity type opposite to that of the semiconductor substrate.

[Effect]

Since the gate electrode of the MIS type transistor according to the present invention is also provided above the relatively lightly doped region that becomes part of the source and drain, the resistance of this relatively lightly doped portion is reduced during operation. Also absolutely l1jl
The electric field due to the hot carriers injected into it is also relaxed.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a sectional view showing the structure of an LDDMOS transistor which is an embodiment of the present invention.

The upper side of the N- diffusion region 4.5 is completely covered with a sidewall 12 made of polysilicon via a gate oxide 11i7. Since this sidewall 12 is made of polysilicon, it operates as a part of the gate electrode 8. Further, an oxide film 13 is formed on the upper part of the gate electrode 8, and an oxide film 14 is further formed on the entire surface.

N+ source region [
A source electrode 15 is formed in contact with the N+ drain region 2, and a drain electrode 16 is formed in contact with the N+ drain region 3. The rest of the structure is similar to the conventional LDDMOS transistor shown in FIG.

FIG. 2 is a process sectional view showing a method of manufacturing the N-channel 100 MOS transistor, which is an embodiment of the present invention shown in FIG. First, in FIG. 2(a), oxidized m7. 81 layers of polysilicon layer 8 (shaded area in the figure) and oxide film 3 are sequentially formed. Next, Figure 2 (b
), after a resist 17 is applied and a pattern is formed, unnecessary portions of the oxide film 13 and polysilicon 18 are removed by anisotropic etching. This step leaves the polysilicon layer 8 of the gate electrode portion covered with the patterned resist 17 and the oxide film 13 above it.

Subsequently, in FIG. 2(C), the resist 172M film 13. of the gate electrode portion is removed. Using the polysilicon layer 8 as a mask,
Dosing N-type impurities such as phosphorus or hiso ffi 101
Ion implantation is performed on the order of 3/c++3. Note that the resist 17 may be removed first, and the ion implantation may be performed by lowering the implantation energy.

Next, in FIG. 2(d), the resist 17 is removed, and the oxide film 7 and the polysilicon layer 8 of the gate electrode portion are oxidized 1.
A second polysilicon layer 18 is formed on 113 (shaded area in the figure).
form. Then, in FIG. 2(e), the second polysilicon layer 18 is removed by anisotropic etching, leaving a portion that will become the sidewall 12. Thereafter, using the polysilicon layer 8 of the gate electrode portion, the oxide film 13, and the sidewall 12 as masks, high-a degree N-type impurities are ion-implanted into the P- semiconductor substrate 1. Next, in Figure 2 m,
Thermal diffusion of impurities is performed in the N source region 2. N+ drain region 3. and N- diffusion regions 4 and 5 are formed. Further, an oxide film 14 is formed to cover the surface. A contact hole is provided in the oxide film 14 to form an N+ source region 2. N+ drain region 3
The source electrode 15. is in contact with the source electrode 15. Drain electrodes 16 are provided respectively.

Finally, you will get the configuration shown in the figure.

In the above example, a method for manufacturing an N-channel 100MOS transistor was explained, but by reversing the conductivity type of the substrate and the impurity to be implanted, it can be made into a P-channel and ODM.
An OS transistor can also be made in a similar manner.

Next, the operation will be explained. In the pentode region where the drain voltage (1) is higher than the gate voltage (v6), an inversion layer is formed mainly on the source side. Therefore, near the gate oxidation 1!17 of the N- diffusion region 4 on the source side, a charge storage layer is formed due to the electric field from the side wall 12 on the source side formed of polysilicon, and the parasitic resistance in this portion is reduced.

Also, the drain voltage V is the gate voltage ■. In the sufficiently smaller triode region, inversion layers are formed on both the source and drain sides.

Therefore, the sidewalls on the source and drain sides are
Due to the electric field from the gate electrode 12, a charge storage layer is formed near the gate oxide film 7 of each of the N- diffusion regions 4.5 on the source side and the drain side, and the parasitic resistance of each is reduced.

FIG. 3 is a graph showing an example of carrier distribution and impurity concentration in the source side surface channel direction in the triode region of the DDMOS transistor of the present invention. The curve is carrier distribution 1 curve L2 is N-type impurity concentration 1 curve L3 is P
Indicates type impurity concentration.

Moreover, the measurement conditions are as follows.

Thickness T of gate oxide film 7. X...100m diffusion area 4
Ion implantation dose ff1D...5×1012C
2 Drain voltage V,...5 ■ Gate voltage V. ...5V N- Since a charge storage layer is formed by the electric field from the sidewall 12 made of polysilicon during the length W of the N-diffusion region 4, the carrier distribution and 1 are lower than the N-type impurity concentration L2. It's more than an order of magnitude higher. Therefore, the parasitic resistance in this part is reduced, and the current driving capability of this transistor in the triode region is improved compared to a conventional 100MOS transistor. Note that in the triode region, the reduction in parasitic resistance due to this charge storage layer occurs in the N- diffusion regions 4.5 on the source side and drain side, so that the current driving ability is improved as well.

FIGS. 4(a) and 4(b) are graphs showing the drain characteristics of the conventional 100MOS transistor and the present invention, respectively. The horizontal axis is the drain voltage VD1, the vertical axis is the drain current I, and the 1 parameter is the gate voltage vG. The drain current of the 100MOS transistor of the present invention shown in FIG. 4(b) is higher! .

It is clear that it has superior driving ability.

FIGS. 5(a) and 5(b) show 1 at the drain part of the 100MOS transistor according to the conventional method and the present invention, respectively.
FIG. 3 is a diagram showing hot carrier generation concentration per second. The carriers flowing from the source to the drain generate new carriers near the drain due to impact ionization. The distribution is shown by a constant production rate line. Figure 5(a)
In the conventional 100MOS transistor, some of the hot carriers generated near the drain are injected into the lower part of the sidewall 9 formed of an oxide film. The electric field of the injected carriers depletes the surface of the N- diffusion region 5, increasing the parasitic resistance. In FIG. 5(b), in the DDMOS transistor of the present invention, the electric field due to the injected carriers into the gate oxide film 7 under the sidewall 12 is caused by the electric field caused by the injected carriers into the gate oxide film 7 under the sidewall 12. It is relaxed by the electric field of the sidewall 12 made of silicon. Therefore, N-
Depletion of the diffusion region 5 is alleviated, and device deterioration such as threshold fluctuation and increase in parasitic resistance is reduced.

In the above embodiment, a MOS transistor was described, but the same applies to other MIS type transistors.

〔Effect of the invention〕

As described above, according to the present invention, in a MIS transistor such as a 100MOS transistor, the gate electrode is also placed above the region doped with a relatively low concentration of conductivity type opposite to that of the semiconductor substrate on the source side and drain side. Since we provided a layer of semiconductor film that operates as a
It is possible to reduce the drain electric field of IS type transistors and increase the withstand voltage, and also to extend the life of the element by not reducing the current driving ability in the triode region of the transistor and by reducing the deterioration of the drain characteristics. It is also possible to obtain a MIS type transistor and its manufacturing method that can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of a 100 MOS transistor according to an embodiment of the present invention, FIGS. 2(a) to (f) are process cross-sectional views showing a method for manufacturing the 100 MOS transistor shown in FIG. 1, and FIG. FIG. 4(a) is a graph showing the carrier distribution and impurity concentration on the source side of the 100MOS transistor shown in FIG. 1. (b) is the conventional LDDMOS and the present invention, respectively.
A graph showing the drain characteristics of a transistor, Figure 5 (a
), (b) are 100% of the conventional and this invention, respectively.
Figure 6 shows the concentration of hot carriers generated near the field drain region of a MOS transistor.
Cross-sectional view showing the structure of an OS transistor, FIG. 7(a)-
(e) is a process cross-sectional view showing the conventional method of manufacturing the DDMOS transistor shown in FIG. 6, and FIGS. 8(a) and (b)
6 are configuration diagrams showing operating states of the conventional 100 MOS transistor shown in FIG. 6 in a pentode region and a triode region, respectively. In the figure, 1 is a P- semiconductor substrate, 2 is an N+ source region, 3 is an N+ drain region, 4.5 is an N- diffusion region, 7 is a gate oxide film, 8 is a gate electrode, 12 is a side wall, and 13 is an oxide 17 is a resist film, and 18 is a polysilicon layer. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Fig. 1 12: S4Y Tsuo 2shi Fig. 2 Fig. 2 (e) Fig. 3 0.0 0.1 0.2Lz
:P-type Senjumono all
(Source → ÷ Yanel) WAN''''bo d1 Ryoritsu Nagako Figure 5 (a) (b) :J-f$0 U) Figure 6 Figure 7 Figure 7 Figure 8 Procedural amendment (voluntary ) 1. Display of the incident Patent application No. 63-108140 No. 2
, Title of the invention MIS type transistor and its manufacturing method 3, Person making the amendment Representative Moriya Shiki 4, Agent 5, Correspondence to the amendment Figure 8 of the drawings 6 Contents of the amendment (1) Figure 8 of the drawings Correct as shown in the attached sheet. that's all

Claims (2)

[Claims] (1) a semiconductor substrate of a first conductivity type; first and second regions of a conductivity type opposite to that of the semiconductor substrate formed at a predetermined interval in the main surface of the semiconductor substrate; third and fourth regions adjacent to and between the first and second regions in a plane and having a lower impurity concentration and the same conductivity type than the first and second regions; an insulating film formed on the main surface of the semiconductor substrate in the third and fourth regions and between them; and an insulating film formed on the main surface of the semiconductor substrate in the third and fourth regions and between them. A MIS type transistor having a gate electrode formed by (2) A method for manufacturing an MIS transistor, comprising: forming a first insulating film on the main surface of a semiconductor substrate of a first conductivity type; and forming a first insulating film on the first insulating film to become a gate electrode. forming a second insulating film on the first semiconductor film, further applying and patterning a resist on the second insulating film, and masking the patterned resist. as said second
etching the insulating film and the first semiconductor film to leave only the resist portion; and using the pattern formed by the etching as a mask, insulating the semiconductor substrate at a relatively low concentration with a conductivity type opposite to that of the semiconductor substrate. a step of removing the resist and forming a second semiconductor film on the entire surface; and a step of removing the resist and forming a second semiconductor film on the entire surface of the first semiconductor film, leaving only a side wall portion of the first semiconductor film and other portions of the second semiconductor film. a step of performing anisotropic etching to remove the second insulating film, the first semiconductor film, and the second semiconductor film on the side wall portion thereof, using the second insulating film, the first semiconductor film, and the second semiconductor film on the sidewall portion as a mask, etching the semiconductor substrate in a direction opposite to the semiconductor substrate; A method for manufacturing an MIS type transistor, including a step of introducing a conductivity type impurity.