JPH01283870A - Charge transfer device - Google Patents

Abstract

PURPOSE:To reduce the total capacity of a floating diffused layer and to improve a signal detecting sensitivity by providing a low concentration region in the drain region of an output transistor having a gate electrode connected to the diffused layer. CONSTITUTION:The drain region of an output transistor 7 having a gate electrode 6 connected to a floating diffused layer 4 which receives charge through an output gate 3 from a charge transfer unit containing a plurality of charge transfer electrodes 2-1-2-6... provided through an insulating film on a P-type semiconductor substrate 1 is formed of a low concentration region 10 disposed near the electrode 6 and a high concentration region 11 provided adjacently thereto. In this transistor 7, a channel is formed at the time of source follower operation, and a depleted layer is extended in the drain region. In this case, since the depleted layer is extended toward the region 10, a capacity between the drain region and the gate electrode is reduced. Thus, an output signal voltage having high sensitivity can be obtained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a charge transfer device.

[Conventional technology]

Charge transfer devices accumulate information input such as electrical signals and incident light in the form of charges, and then sequentially transfer the charges using a large number of charge transfer electrodes, amplifying and extracting them as electrical signals. Semiconductor devices including such devices are used in imaging devices, memories, signal processing devices, and the like.

FIG. 2 is a schematic cross-sectional view of an example of a conventional charge transfer device. This conventional example is provided, for example, on a P-type semiconductor substrate 1 with an insulating film 8 interposed therebetween, as shown in FIG. φ1. A large number of charge transfer electrodes 2-1 to 2-6 driven by φ2 and φ3 and the final stage (2
-6) An output gate 3 provided through an insulating film on a P-type semiconductor substrate 1 in close proximity to the P-type semiconductor substrate 1 and fixed to a potential V2, and an N-type floating diffusion for converting transferred charges into voltage. By connecting the floating diffusion layer 4 and the gate electrode 6, a reset transistor 5 has the layer 4 as the source, the N-type impurity layer fixed at potential V1 as the drain, and the gate electrode to which the reset clock signal φR is applied. It is composed of an output transistor 7 for extracting charges to the outside as a voltage signal.

In this conventional driving method, reset is performed by first turning off the reset transistor 5 and setting the potential of the floating diffusion layer 4 to the potential v1 of the power supply, and then turning off the reset transistor 5.

Next, the three-phase clock signal φ1. φ2 and φ.

drives a large number of charge transfer electrodes 2-1 to 2-6 to generate potential wells on the surface of the P-type semiconductor substrate 1 under each charge transfer electrode to transfer charge signals, and for charge transfer in the final stage. The potential is stored in the potential well just below the electrode 2-6 as shown in FIG. 3(a).

Then, at the next clock timing, the charge is changed to the potential V
It is poured into the floating diffusion layer 4 through the surface of the P-type semiconductor substrate 1 under the output gate 3 to which 2 is applied, as shown in FIG. 3(b).

In this case, if the amount of charge transferred is Q and the total capacitance of the floating diffusion layer 4 is C, the potential difference ΔV between the floating diffusion layer 4 before and after the charge flows can be expressed as ΔV=-. .

Therefore, by outputting V to this potential difference through the output transistor 7, the information stored in this conventional semiconductor device can be read.

Here, the total capacitance C of the floating diffusion layer section 4 includes the capacitance between the floating diffusion layer 4 and the P-type semiconductor substrate 1, the capacitance between the floating diffusion layer 4 and the output gate 3, and the capacitance between the floating diffusion layer 4 and the gate electrode (φR ) and the sum of the gate capacitance of the gate electrode 6.

Regarding the above-mentioned gate capacitance, the portion of the output transistor 7 will be specifically explained using the schematic cross-sectional view of FIG.

The output transistor 7 formed by the gate electrode 6 electrically connected to the floating diffusion layer 4 is used as a source follower transistor in which the saturation region of the transistor is used so that the output signal voltage changes according to changes in the gate electrode potential. Because of this, the channel portion 9 under the gate electrode is cut just below the gate electrode, as shown in FIG. For this reason,
The gate capacitance is divided into the capacitance between the drain and the gate electrode fixed at the V1 voltage, the capacitance between the source and the gate electrode connected to the output signal terminal 12, and the capacitance between the gate electrode and the P-type semiconductor substrate.

The value of the output signal is determined by the total capacitance C of the floating diffusion layer described above. That is, in order to obtain a highly sensitive signal output, it is necessary to reduce the total capacitance C of the floating diffusion layer mentioned above. Furthermore, since the floating diffusion layer capacitance is largely determined by the area of the floating diffusion layer and the gate capacitance, it is necessary to reduce the area of the floating diffusion layer and lower the gate capacitance in order to increase sensitivity.

[Problem to be solved by the invention]

In the conventional charge transfer device described above, in order to obtain an output signal voltage that is highly sensitive to signal charges, it is necessary to reduce the total capacitance C of the floating diffusion layer, but it is also possible to reduce the area of the floating diffusion layer. There is a limit, and the size of the transistor cannot be reduced due to the gate capacitance and output impedance.
The drawback is that it cannot output highly sensitive signals.

[Means to solve the problem]

The charge transfer device of the present invention has a gate electrode connected to a floating diffusion layer that receives charges via an output gate from a charge transfer section including a plurality of charge transfer electrodes provided on a semiconductor substrate via an insulating film. In the charge transfer device including an output transistor, the drain region of the output transistor is composed of a low concentration region disposed near the gate electrode and a high concentration region adjacent thereto.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of a semiconductor chip showing the main parts of an embodiment of the present invention, showing an output transistor section, and other parts are the same as FIG. 2.

In this embodiment, charges are transferred through an output gate 3 from a charge transfer section including a plurality of charge transfer electrodes 2-1 to 2-6 provided on a P-type semiconductor substrate 1 via an insulating film. In a charge transfer device including an output transistor 7 having a gate electrode 6 connected to a receiving floating diffusion layer 4, the drain region of the output transistor 7 includes a low concentration region 10 disposed near the gate electrode 6 and a low concentration region 10 disposed adjacent thereto. It consists of a high concentration region 11 with a high concentration. Note that 13 is a source region, which is formed at the same time as the high concentration region 11.

In this output transistor, a channel similar to that shown in FIG. 4 is formed during source follower operation, and a depletion layer expands in the drain region. At this time, since the low concentration region 10 is provided, the depletion layer also extends in the direction of the low concentration region 10, so that the capacitance between the train region and the gate electrode becomes smaller than in the conventional example.

〔Effect of the invention〕

As explained above, in order to reduce the total capacitance of the floating diffusion layer, the present invention provides a low concentration region in the drain region of the output transistor having the gate electrode connected to the floating diffusion layer. By reducing the total capacity of
This has the effect of improving signal detection sensitivity.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of a semiconductor chip showing the main parts of an embodiment of the present invention, FIG. 2 is a schematic cross-sectional view of a charge transfer device, and FIGS. 3(a) and (b) are operations of the charge transfer device. FIG. 4 is a schematic cross-sectional view showing the main parts of a conventional example. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2-1 to 2-6... Electrode for charge transfer, 3... Gate for output, 4... Floating diffusion layer, 5... Reset transistor, 6...・Gate electrode, 7... Output transistor, 8... Insulating film, 9...
- Channel portion, 10...Low concentration region, 11...High concentration region, 12...Output signal terminal, 13... Source region.

Claims (1)

[Claims] A charge transfer unit including an output transistor having a gate electrode connected to a floating diffusion layer that receives charges via an output gate from a charge transfer unit including a plurality of charge transfer electrodes provided on a semiconductor substrate via an insulating film. A charge transfer device, wherein the drain region of the output transistor comprises a low concentration region disposed near the gate electrode and a high concentration region adjacent thereto.