JPH0128389B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a pattern generator used in a laser printer using a laser beam, which generates a plurality of dot patterns having different pattern dimensions from a basic dot pattern having a predetermined order. This relates to a pattern generation method.

Devices that generate patterns using the line scan method used in laser printers, etc., distribute the pattern into dots, marking white areas as “0” and black areas as “1”.
By converting into logic signals such as Rather than a dot pattern with a predetermined order, it is necessary to generate patterns with multiple dimensions to meet the user's requirements.

For this reason, when the line scan direction is in the horizontal or column direction, a method is used in which enlargement or reduction instruction information is stored in the pattern generator for vertical or row direction enlargement or reduction. The same method as above is also used in the column direction, but in the column direction, the time to read out instruction information for enlargement and reduction and the time to read out dot data must be considered separately, making the circuit of the device complicated. Since there is a problem that it becomes expensive, it is necessary to change the video clock and expand the column direction.
There are methods to perform reduction. However, this video clock switching method also has the disadvantage that it becomes difficult to implement as the video clock becomes faster. For example, when displaying a 9-point character divided into 30 dots x 30 dots
Assume that a 4MHz video clock is used. If this were to be reduced to a 7-point character, a pattern of 30 dots x 30 dots would have to be reduced to a size equivalent to 24 dots x 24 dots. For this reason, as mentioned above, reduction in the row direction involves inputting reduction instruction information into the pattern generator, but in the column direction, the video clock is converted and the size of each 30 dot is reduced to the size equivalent to 24 dots. It is necessary to Conversely, if you want to enlarge a 9-point character to a 12-point character, in the row direction, enlargement instruction information is input to the pattern generator, and in the column direction, the video clock is converted and the dimensions of each 30-dot dot are expanded. It is necessary to stretch it to a size equivalent to 40 dots.

For this reason, each video clock is inversely proportional to the number of dots because the scan time in the column direction of the line scan pattern generator is constant.
30×4/24=5MHz and 30×4/40=3MHz. To obtain these video clocks of 3MHz, 4MHz, and 5MHz, it is sufficient to divide the least common multiple of each clock, 60MHz. An example is shown in FIG. The basic clock oscillator 1 is a 60MHz oscillator, and its output is sent to frequency dividers 2, 3, and 4, where the frequency is divided to 3MHz,
The outputs of 4MHz and 5MHz are AND gates 5, 6, and 5, respectively.
7, the required frequency is selected by the selection signal F, and is sent to the OR gate 8, where it is sent out as a video clock. As explained above, by dividing the basic clock, which is the least common multiple of each video clock, the required video clock can be obtained for each pattern, and each pattern can be expanded or reduced on a pattern-by-pattern basis. However, the synchronization of each video clock is not as low as in the example above, but is usually very high, around 40MHz, in high-speed printers, and in this case, the least common multiple basic clock frequency is 600MHz.
This has the drawback that frequency division is extremely difficult and expensive. Furthermore, if each video clock is obtained from an individual oscillator, it is difficult to synchronize them, and if synchronization is not achieved, the relationships between patterns of different sizes will become disordered, making it impossible to obtain a complete pattern. Therefore, as described above, as the cycle of the video clock becomes faster, implementation becomes more difficult.

An object of the present invention is to reduce the frequency of the basic clock oscillator 1 by replacing the frequency dividers 2, 3, and 4 in FIG. The purpose is to make sure that the tsuku are synchronized. For example, as above
If a 40 MHz video clock is used to generate a 30 dot pattern, a 24 dot pattern requires a 50 MHz video clock, and a 40 dot pattern requires a 30 MHz video clock.

The frequency of each video clock is 30MHz, 40MHz,
In the case of 50MHz, each clock is 33.3ns,
Since they are 25 ns and 20 ns, the time required to output one pattern is 1 μs (33.3 ns×30 dots), 750 ns (25 ns×30 dots), and 600 ns (20 ns×30 dots), respectively.

Therefore, the common divisor is 50 ns, and in this case the basic clock frequency is 20 MHz.

The phase clock oscillator PLL needs to be an integer multiple of the fundamental clock frequency (20MHz), so the desired video clock above is 60MHz,
It can be obtained by dividing 80MHz and 100MHz by two.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram for explaining one embodiment of the present invention.

FIG. 3 is a time chart for explaining the operation of the block shown in FIG. 2.

In the figure, the basic clock oscillator 1 is an oscillator with a basic clock frequency _{of 0} , for example 20MHz,
The output ₀ is input to phase comparators 9, 14, 19 in each PLL 100, 101, 102.

By the way, each phase lock oscillator PLL
100, 101, and 102 are phase comparators 9 and 102, respectively.
14, 19, voltage controlled oscillator 11, 16, 21,
It is composed of low pass filters 10, 15, 20 and counters 13, 18, 23.

The PLLs 100, 101, and 102 each operate as follows. Furthermore, this operation
This will be explained using the PLL 100 as an example.

First, the phase comparator 9 uses the basic clock (20MHz) from the basic clock oscillator 1 and the voltage controlled oscillator 1.
1's oscillation output ₁ clock (60MHz) is counted down to 1/3 and converted to a clock with the same frequency as the basic clock.The phase comparison is made with the clock from the counter 13, and the control voltage v ₁ is determined according to the phase difference.
occurs.

In addition, in the PLL 101, the clock of output ₂ of the voltage controlled oscillator 16 is 80MHz, and the counter 18 counts down the clock to 1/4.
In the PLL 102, the clock of the output ₃ of the voltage controlled oscillator 21 is 100 MHz, and the counter 23 counts down the clock to 1/5.

The control voltage _v1 output from the phase comparator 9 is passed through a low-pass filter 1 to remove high frequency components and noise.
After passing through 0, it is input to the voltage controlled oscillator 11.

The voltage controlled oscillator 11 oscillates an oscillation output ₁ synchronized with the output ₀ of the basic clock oscillator ₁ using the control voltage v1.

Then, this oscillation output ₁ is counted down to 1/3 by the counter 13, becomes the same frequency as the basic clock frequency of the basic clock oscillator 1, and is input to the phase comparator 9, and the basic clock frequency _{is 0.}
Phase comparison is performed with

By performing the operations explained above, each
PLL100, 101, and 102 have oscillation outputs ₁ (60MHz: Figure 3 d), which are integral multiples of the basic clock ₀ (20MHz: Figure 3a) of the basic clock oscillator 1, ₂
(80MHz: Figure 3 c), ₃ (100MHz: Figure 3 b).

Then, the oscillation output ₁ of the voltage controlled oscillator 11, 16, 21 of each PLL 100, 101, 102,
₂ and ₃ are input to AND gates 5, 6, and 7, respectively, and one of them is selected by a selection signal F that is individually input to each.

The outputs of the AND gates 5, 6, and 7 are divided by frequency dividers 12, 17, and 22, respectively, to 30 MHz (Fig. 3 g) and 40 MHz (Fig. 3 f) necessary for outputting the above pattern. , 50 MHz (FIG. 3e) and sent out via the OR gate 8.

In the configuration described above, the clock switching operation accompanying a change in pattern size will be described with reference to FIG.

Now, if we are outputting a 9-point pattern, in Fig. 2, the output ₂ of PLL 101 (Fig. 3 c
The pattern is output using the clock shown in FIG.

In this state, when the selection signal F is applied to the AND gate 5 so as to output a 12-point enlarged pattern, the PLL 100 is selected and its output ₁ (clock in FIG. 3d) is selected.

Here, this selection signal F is output in synchronization with the basic clock ₀ of the basic clock oscillator 1, so it is output in units of 50 ns.

Therefore, the selection signal F output in units of 50 ns
On the other hand, the clocks in Figure 3 d are also synchronized (Figure 3 c,
b), so the switching is performed in synchronization with the clock without switching in the middle of the clock.

Then, the output ₁ (60MHz) of the voltage controlled oscillator 11, which is the other input of the AND gate 5, is output to the frequency divider 1.
2, is converted to the required 30 MHz clock, and is sent out via OR gate 8.

Therefore, when switching the pattern size, there will be no deviation in pattern spacing due to clock deviation.

Furthermore, the basic clock frequency of the basic clock oscillator 1 may be sufficiently low, making it possible to reduce the cost.

As mentioned above, the clock frequencies required for pattern output are 30MHz, 40MHz, and 50MHz.
In this case, it is necessary to divide the output of each PLL 100, 101, 102 using frequency dividers 12, 17, 22. At this time, the clocks shown in FIGS. 3e-f are not necessarily synchronized with the basic clock (FIG. 3a). However, since these clocks are divided after the clocks shown in FIGS. 3b-d are selected, no problem arises.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional video clock generation circuit, FIG. 2 is a circuit block diagram showing an embodiment of the pattern generation method according to the present invention, and FIG. 3 is a block diagram of the circuit shown in FIG. 2. It is a time chart. In the figure, 1 is the basic clock oscillator, 9, 1
4, 19 are phase comparators, 10, 15, 20 are low pass filters, 11, 16, 21 are voltage controlled oscillators, 12, 17, 22 are frequency dividers, 13, 18,
23 is a counter, 5, 6, 7 are AND gates, 8
is an or gate.

Claims (1)

[Claims] 1. A pattern generation method for generating patterns of a plurality of different sizes from a basic dot pattern of a predetermined size, which comprises: a basic clock oscillator that oscillates a basic clock; the basic clock is input;
a plurality of phase lock oscillators each generating a video clock of a different frequency corresponding to the time required to generate patterns of a plurality of different sizes proportional to the size of the basic pattern; The basic clock of the clock oscillator is set to be a clock with a frequency corresponding to the greatest common divisor of the respective times required to generate the pattern, and the plurality of phase lock oscillators are switched in synchronization at the turn of the pattern. A pattern generation method characterized by the following.