JPH01286071A - Information processor - Google Patents

Abstract

PURPOSE:To decrease an overhead caused by instruction execution by providing a means which erases an internal condition when a completion code indicates a normal completion, and sends an interrupting signal to a circuit to execute an instruction when the code indicates the abnormal completion. CONSTITUTION:A processor element 1-1 to request a processing holds the internal condition of the processor element at the time of a processing request into a register 15. A processor element 1-n have received the processing request execute the processing of the request, and then, notifies the completion code to indicate whether the execution is normally completed or abnormally completed to the processor element 1-1. The processor element 1-1 have received the completion code erases the internal condition held in the register 15 when the completion code indicate the normal completion, and sends the interrupting signal to the circuit to execute the instruction when the completion code indicates the abnormal completion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of configuring processors in an information processing device comprising a plurality of processors operating in parallel.

[Conventional technology]

Conventionally, in an information processing device composed of multiple processors, in order to know whether or not the processing has been completed normally after one processor requests processing to another processor, it is necessary to issue an instruction to know this. I was supposed to run it and check it. Related devices of this type include, for example, the Information Processing Society of Japan's 34th (first half of 1986) National Conference 4B.
There is a device that is discussed in Proceedings of the 2006 Proceedings of the 20th International Conference on 2009-5 (pages 347 to 348 of the proceedings).

[Problem to be solved by the invention]

In the above conventional technology, there is a high possibility that the requested process will be completed normally, and if it is completed normally, there is no need for the requesting side to do anything, for example, if the requested process is Even in the case where the value 1 is added to a variable located in a variable (in this case, if the variable overflows as a result of adding the value 1 to the variable, the requested processing is terminated abnormally), considering the reliability of the information processing system. An instruction must be executed to know that the process has completed normally. However, this process is a process that must be performed every time to detect an event that occurs only rarely, resulting in obvious overhead.

An object of the present invention is to enable the requesting processor element to detect when a process requested from one processor element to another processor element terminates abnormally; The objective is to reduce the overhead caused by the execution of instructions.

[Means to solve the problem]

The above object is to provide a means for retaining the internal state of each processor element when requesting processing to each processor element of an information processing device consisting of a plurality of processor elements; means for notifying the processor element that requested the processing of a termination code indicating whether the termination was normal or abnormal; and when the termination code indicates normal termination, the internal state is erased by an erase circuit, and the termination is terminated. This is achieved by providing means in each processor element for sending an interrupt signal to the circuitry executing the instruction when the code indicates abnormal termination.

[Effect]

The processor element that requests processing maintains its internal state at the time of requesting processing. The processor element that received the processing request executes the processing according to the request, and then notifies the processor element that requested the processing of an end code indicating whether the execution ended normally or abnormally. The processor element that receives this termination code erases the internal state held by the erase circuit when this termination code indicates normal termination, and sends an interrupt signal to the circuit that executes the instruction when the termination code indicates abnormal termination. It works like this.

Through the above steps, the object of the present invention is achieved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

First, an outline of an information processing apparatus according to the present invention will be explained with reference to FIG. In FIG. 1, 1-1 to 1-n are n independently operable processor elements. 1-1 to 1-n all have the same configuration. 2 is an interconnection network that receives a message transmission request issued from any processor element 1-1 to 1-n;
Forward the message to the specified processor element.

Next, the configuration of the processor element 1 will be explained with reference to FIG. The processor element 1 is a Von-Neumann type computer, and in addition to normal arithmetic instructions, it has new instructions to be described later. 3 is a receiving device that receives messages sent from network 2; Receiving bag! ! ! 3 has registers 3-1 to 3-5 that hold each field of the received message. A local memory 4 holds programs executed by the processor elements and data used by the programs. 5 is a transmitting device, and transmitting device l! The messages stored in registers 5-1 to 5-6 in 5 are transmitted to network 2. 6 is a register in which the number of the processor element concerned is stored. 7 is a decoder, 8 and 9 are N07 circuits, 10 and 11 are AND circuits, and 12 is a decoder. 13 and 14 are 1-bit registers, 15 and 16 are register groups, 17 is a selection circuit, and 18 is a general-purpose register group. 19 is an ALU that performs calculations, 20 is an instruction fetch circuit, and 21 is a program counter. 22 is the instruction register.

It is divided into fields 22-1 for storing instruction codes and fields 22-2 to 22-5 for storing register numbers. Reference numeral 23 denotes an instruction decoding control that decodes instructions and controls execution of the instructions. 24 is a register in which a code indicating a message for notifying an end code is fixedly stored.

The operation of the processor element will be explained with reference to FIG. First, the instruction fetch circuit 20 connects the line L4. The contents of the program counter 21 are transferred to the local memory 4 as a read address via L21.

Then local memory 4 is read and its contents are 1L.
15 and is set in the instruction register 22. The instruction decoding control 23 decodes the instruction code stored in the field 22-1 of the instruction set in the instruction register 22, and sends a signal to the inside of the processor element 1 to implement the operation specified by the instruction. Hand out, ALU19.
The general-purpose register group 18 and the like are operated. When the operation specified by the instruction is completed, the instruction decoding control 23 updates the value of the program counter 21 via line L7, and repeats the above operation.

The operation of network 2 will be explained. Network 2 is
When a message is set in the registers 5-1 to 5-6 in the transmitting device 5, the registers 3-1 to 3-5 in the receiving device 3 of the processor element specified by the contents of 5-1 are set. Transfer the contents of 5-2 to 5-6. Transmitting device l! If the message set within 5 is short and does not satisfy all of 5-1 or 5-6,
Transfer only the necessary parts of the message.

Before explaining the details of the circuit according to the present invention, an outline of the operation will be explained with reference to FIGS. 6 and 7M. 61st! I shows the flow when processor element i requests processing to processor element j, processor element j executes the requested processing, and the processing ends normally. When requesting processing, first processor element i
executes a ROP (Remote 0operation) instruction. FIG. 3 shows the format of the ROP instruction.

In FIG. 3, 301 is an instruction code, 3o2 is a general-purpose register number that stores the number of the processor element to which processing is requested, 303 is a general-purpose register number that stores a command code for specifying the requested processing, and 304 is the processing requested destination. A general-purpose register number 305 stores the address of data placed in the a-local memory of the processor element. The ROP instruction is 3
The operation specified in 303 is executed between the data stored at the address specified in 304 of the local memory of the processor element specified in 02 and the data specified in 305, and the result is transferred to the processor element specified in 302. The data is stored at the address specified in step 304. 303
The value stored in the general-purpose register specified by may indicate direct addition or multiplication, or this value may indicate the entry address of a subroutine. When executing this instruction, the processor element sends a message to request processing to the processor element to which the process is requested, and also holds the internal state of the processor element at the time when the circuit according to the present invention executes this instruction. The ROP instruction now ends, and processor element i can now execute the next instruction. When the message from the ROP instruction arrives at the destination processor element j, processor element j executes the requested process and sends a message to processor element i indicating whether or not the execution has been completed normally. In the example of FIG. 6, normal completion is sent. The circuit according to the invention of processor element i then erases the previously held internal state.

FIG. 7 shows the flow when processor element i requests processing to processor element j, processor element j executes the requested processing, and the processing ends abnormally. The execution procedure up to the request for processing is the same as in the case of FIG. In the example of FIG. 7, since the execution ends abnormally, the processor element i sends a message to the processor element i indicating that the execution has ended abnormally. Then, the circuit according to the present invention of the processor element i analyzes the internal state previously held within the interrupt handling routine that interrupts the circuit that executes instruction processing in the processor element i, and determines when It is possible to know whether the process requested by the ROP command executed in the previous process ended abnormally.

The format of messages related to the ROP command will be explained. Figure 4 shows the format of a message for requesting processing. In Figure 9, 311 is the number of the processor element to which the message is sent, 312 is the command code indicating the type of processing to be requested, and 313 is the command code indicating the type of processing requested. 314 stores data, 315 stores a pending number, and 316 stores the number of the processor element that is the processing request source. The hold number will be described later. Figure 5 shows the format of a message for conveying a completion code indicating whether execution of a requested process has ended normally or abnormally. ,
A code indicating that the message is a message notifying an end code is stored in 322, an end code is stored in 323, and a suspension number is stored in 324. The code stored in 322 is
The command code is selected so that it does not coincide with the command code stored in 312 in FIG.

Next, the operation of the circuit according to the present invention will be explained in detail. First, the initialization method will be explained. In initialization, the identification number of the processor element is set in register 6, and the contents of 1-bit registers 13 and 14 are set to 0.

Next, the message sending operation will be explained with reference to FIG.

The instruction code stored in the field 22-1 of the instruction register is decoded by the instruction decoding control 23.

When it is determined that the instruction is a ROP instruction, the instruction decoding control 23 transmits the number of the general-purpose register storing the operand of the instruction to the general-purpose register group 18 via line L23. Then, 22
-2.22-3.22-4゜The contents of the general-purpose registers specified by 22-5 are transferred to register 5 via line L5.
-1.5-2°5-3.5-4. Also,
The processor element number stored in register 6 is set in register 5-6. In parallel with this, the instruction decoding control 23 sends a signal to the selection circuit 17 via the line LIO. Then, the selection circuit 17 selects the 1-bit register 13.14.
input the contents of , and arbitrarily select one 1-bit register whose contents are 0. Here, it is assumed that the 1-bit register 14 is selected. Then, the selection circuit 17 writes 1 to the 1-bit register and simultaneously writes 22-2, 22-3.
22-4. Store the contents of the general-purpose register specified in 22-5 in register #16 via @L9.

Furthermore, the contents of the program counter 21 at this time are displayed on line L4. It is transferred to the register group 16 via line L9. Further, the selection circuit 17 sets the number assigned to the selected 1-bit register to 5-5 via 1iAL6. This number will be called a hold number. Due to the above, 5-1
Since a processing request message is set in 5-6, the transmitter 5 transmits the message to the network 2. The network 2 transfers the contents of 312 to 316 in FIG. 4 to the registers 3-1 to 3-5 of the processor element designated by the contents of 311. Note that when the contents of all 1-bit registers are 1, the start of the above operation is delayed until the contents of one or more 1-bit registers become O.

Receiving device from network 2! ! When a message requesting processing arrives at 3, the contents of 3-1 are first input to the decoder 7 and decoded. The decoder 7 detects line L18.3-1 only when the content of line L18.3-1 represents a message notifying an end code. The value l is output to L19. Therefore, when a processing request message arrives, O is output to line L18.19, and as a result, the output of AND circuit 10.11 becomes O, and AND circuit 10.11
The output of does not trigger any action. On the other hand, since the output of the NOT circuit 8 becomes 1, the following operation of the instruction decoding control 23 is activated via the line L12. First, the address of the local memory 4 is specified using the line L24, and the contents of the general-purpose register group 18 are saved to the local memory 4 using the line L14. For the address of the local memory 4 specified at this time, 1, for example, the contents of a stack pointer (not shown) may be used. After that, from the line L3 to the register 3-1.3-2
．． 3-3 is transferred to the general-purpose register group 18. In addition, the contents of 3-4 and 3-5 are stored in registers 5-1 and 5-, respectively.
Transfer to 4. Also, set the contents of register 24 (code indicating that the message is a message notifying an end code) to 5-2.
Transfer to. After that, the ALU 19 executes the operation specified by the command code using the local memory address and data transferred to the general-purpose register, and if it ends normally, the value 0 is set as the end code, and if it ends abnormally, the value 1 is set on the line Li2. The data is stored in register 5-3. As a result, a message having the format shown in FIG. 5 and for notifying the end code is created in the registers 5-1 to 5-4, so the transmitting device 5 transmits the message to the network 2. Then, network 2 becomes 322, 323 in FIG.
, 324 are respectively set in the registers 5-1.5-2.5-3 of the processor element designated by 321, that is, the processor element that requested the processing. In addition,
In parallel with this, the contents of the general-purpose register group 18 that had been saved in the local memory 4 are restored at 1L14.

When a message notifying the above end code arrives from the network 2 to the receiving device 3, the contents of 3-1 are input to the decoder 7 and decoded, and 1 is output on the line L18°Li2. As a result, the output of the NOT circuit 8 becomes 0, so that the NOT circuit 8 does not start any operation.

Here, when the content of 3-2 is O1, that is, when the requested process is normally completed, the output of the AND circuit 11 becomes 1. As a result, the decoder 12 is activated, and O is stored in the 1-bit register indicated by the pending number stored in 3-3. In this case, as previously assumed, 1-bit register 14 is selected and its contents are set to O.

When the content of 3-2 is 1, the output of the AND circuit 10 becomes 1, which is transmitted to the instruction decoding control 23 via the line Lll and becomes an interrupt signal for the instruction decoding control 23. When an interrupt occurs, the instruction decoding control 23 saves the contents of the general-purpose register group 18 to the local memory 4 as before, and
．． 3-2. After transferring the contents of 3-3 to the general-purpose register group 18, the 0 interrupt processing program branches to the interrupt processing program. By reading the contents of 16) from line L22, you can know the instruction address and operand of the ROP instruction that requested the abnormally terminated processing.At the end of 1 interrupt processing, the 1-bit register specified by 3-3 is (here 14
) is sent to the decoder to set the contents to 0, and at the same time, the contents of the general-purpose register group 18 saved in the local memory 4 are restored.

In the above, two sets of register groups 15 and 16 are provided as register groups representing the internal state of the processor, but how many there are is not the essence of the present invention. The register group can be implemented in the same way no matter how many devices there are.

〔Effect of the invention〕

According to the present invention, when a process requested from one processor element to another processor element terminates abnormally, it is possible to detect this in the instruction sequence of the requesting processor element; It becomes possible to reduce the overhead exerted on instruction execution in the processor element.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of an information processing device according to the present invention, and FIG.
The figure shows the configuration of the processor element, Figure 3 shows the format of the command to request processing from another processor element, Figure 4 shows the format of the message sent to request processing, and Figure 5 shows the process is normal. Format of a message that notifies an end code indicating whether or not it has ended, an information processing apparatus according to the present invention when a processor element requests processing to another processor element and the requested processing ends normally, as shown in FIG. FIG. 7 is a diagram showing the processing flow of the information processing apparatus according to the present invention when a process requested by a certain processor element to another processor element terminates abnormally. DESCRIPTION OF SYMBOLS 1... Processor element, 2... Network 1-work, 3... Receiving device, 4... Local memory, 5...
... Transmitting device, 15.16... Register, 18...
General-purpose register group, 20... instruction fetch circuit, 23.
...Instruction decoding control. ■ 3 zurei 4 concave 5 zuo b fig. 7

Claims (1)

[Claims] 1. In an information processing device consisting of multiple processors,
A means for maintaining the internal state of the processor when requesting processing, and a means for maintaining the internal state of the processor when requesting processing, and after executing processing requested by another.
Means for notifying the processor that requested the process of an end code indicating whether the execution ended normally or abnormally; and when the end code indicates normal end, the internal state is 1. An information processing apparatus characterized in that each processor has means for erasing the code and sending an interrupt signal to a circuit that executes an instruction when the end code indicates abnormal termination.