JPH01290220A - Compound semiconductor layer growth method - Google Patents

Compound semiconductor layer growth method

Info

Publication number
JPH01290220A
JPH01290220A JP11928088A JP11928088A JPH01290220A JP H01290220 A JPH01290220 A JP H01290220A JP 11928088 A JP11928088 A JP 11928088A JP 11928088 A JP11928088 A JP 11928088A JP H01290220 A JPH01290220 A JP H01290220A
Authority
JP
Japan
Prior art keywords
temperature
layer
growth
buffer layer
compound semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11928088A
Other languages
Japanese (ja)
Other versions
JPH0573333B2 (en
Inventor
Masahiro Akiyama
秋山 正博
Sachiko Onozawa
小野沢 幸子
Takashi Ueda
孝 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP11928088A priority Critical patent/JPH01290220A/en
Publication of JPH01290220A publication Critical patent/JPH01290220A/en
Publication of JPH0573333B2 publication Critical patent/JPH0573333B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To flatten the surface of a growth layer to be grown on a second buffer layer by growing the second buffer layer on a first buffet layer at an intermediate temperature between a growth temperature of the first buffer layer and an ordinary growth temperature of a compound semiconductor layer. CONSTITUTION:When a two-stage growth operation is executed, an Si substrate 10 is heat-treated; after that, a first buffer layer 12 of a compound semiconductor is grown on this substrate at a first temperature which is sufficiently lower than this heat-treatment temperature. In succession, a growth operation of this first buffer layer 12 is stopped once; a second buffer layer 16 is grown at an intermediate second temperature of a halfway value to raise a temperature to an ordinary growth temperature of this compound semiconductor. In succession, a growth operation of this second buffer layer 16 is stopped once; a temperature is raised to an ordinary growth temperature of this compound semiconductor; a compound semiconductor layer is grown on the second buffer layer 16 at this temperature. By this setup, even when a film thickness of the first buffer layer 12 is irregular, the surface of the compound semiconductor layer to be grown after that at the ordinary growth temperature becomes a good specular or a face close to this state.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、シリコン(Si)基板上にこの基板と格子
定数が異なった化合物半導体層、特に、■−v族化合物
半導体層をヘテロエとタキシャル成長させる方法に関す
る。
Detailed Description of the Invention (Field of Industrial Application) This invention provides a method for forming a compound semiconductor layer having a different lattice constant from that of a silicon (Si) substrate, in particular a ■-V group compound semiconductor layer, into a heterogeneous and taxial layer. Regarding how to grow.

(従来の技術) 従来より、Si基板上にGaAs等の■−v族化合物半
導体層を成長させて、大型の良質のウェハを製作する技
術の開発が進められ、実用に供されている。Si基板に
これら化合物半導体層をヘテロエとタキシャル成長させ
る方法として、例えば、文献: rJAPANESE 
JOυRNAL OF APPLIEDPHYSI’C
S  、  Vol、23.NO,11,(1984)
  Glp、L843−L845Jに開示されているよ
うな2段階成長法が用いられている。先ず、この従来方
法につき簡単に説明する。
(Prior Art) Techniques for producing large, high-quality wafers by growing a ■-v group compound semiconductor layer such as GaAs on a Si substrate have been developed and put into practical use. As a method of heterotaxially growing these compound semiconductor layers on a Si substrate, for example, refer to the literature: rJAPANESE
JOυRNAL OF APPLIED PHYSI'C
S, Vol, 23. NO, 11, (1984)
A two-step growth method is used, as disclosed in Glp, L843-L845J. First, this conventional method will be briefly explained.

第2図は、この従来の2段階成長法を説明するための成
長温度の説明図であり、横軸に時間及び縦軸に温度(℃
)l&プロットして示しである。また、第3図は従来方
法の説明に供するウェハ断面図である。
FIG. 2 is an explanatory diagram of growth temperature to explain this conventional two-step growth method, with time on the horizontal axis and temperature (°C) on the vertical axis.
)l & plotted as shown. Further, FIG. 3 is a cross-sectional view of a wafer used to explain the conventional method.

第2図及び第3図に示すように、Si基板10を900
 ’C程度の温度で熱処理した(第2図に工で示す、)
猪、第1段階では、400 ’C程度の低温でGaAs
の薄層すなわちバッファ層12を第一層目の成長層とし
て成長させ(第2図に■で示す、)、続いて、M2段階
でGaAs層+41Fr第二層目の成長層として成長さ
せる(第2図に■で示す、)、この第2段階での第二層
目のGa43層の成長(第2図のIII)は、第1段階
(第2図の■)での第一層目のGaAs層の成長を一旦
停止させて、通常のGaAsの成長温度である例えば7
00℃程度の温度にまで昇温させてからこのGaAs層
14の成長を再開する方法である。
As shown in FIGS. 2 and 3, the Si substrate 10 is
Heat treated at a temperature of about 'C (indicated by mark in Figure 2)
In the first stage, GaAs was produced at a low temperature of about 400'C.
A thin layer of , that is, a buffer layer 12, is grown as the first growth layer (indicated by ■ in FIG. 2), and then, in the M2 stage, a GaAs layer + 41Fr is grown as the second growth layer (indicated by ■ in FIG. 2). ), the growth of the second Ga43 layer in the second stage (III in Figure 2) is the same as the growth of the first layer in the first stage (■ in Figure 2). The growth of the GaAs layer is temporarily stopped, and the temperature is set to the normal GaAs growth temperature, e.g.
This is a method in which the growth of the GaAs layer 14 is restarted after the temperature is raised to about 00°C.

この2段階成長法によれば、無極性結晶上への有極性の
結晶を成長させ、単一のドメインの成長層を得ることが
出来るものである。さらに、基板と成長層との間に格子
不整合があっても結晶の成長が可能であり、従って、上
述した2段階成長法はSi基板上にGaAs等の化合物
半導体の格子不整合を有する結晶を成長させるための有
効な方法である。
According to this two-step growth method, a polar crystal can be grown on a non-polar crystal to obtain a growth layer of a single domain. Furthermore, it is possible to grow a crystal even if there is lattice mismatch between the substrate and the growth layer, and therefore, the above-mentioned two-step growth method can be used to grow a crystal with lattice mismatch of a compound semiconductor such as GaAs on a Si substrate. This is an effective way to grow.

(発明が解決しようとする課題) ところで、このようにSi基板10上に化合物半導体成
長層を形成して得られたウェハは、従来と同様に、種々
の電子デバイス素子が作り込まれるわヴであるが、その
ためには当然ながら成長層の表面は鏡面であることが望
ましい。
(Problem to be Solved by the Invention) By the way, the wafer obtained by forming a compound semiconductor growth layer on the Si substrate 10 in this way can be used as a wafer on which various electronic device elements are fabricated, as in the past. However, for this purpose, it is naturally desirable that the surface of the growth layer be a mirror surface.

しかしながら、この2段階成長法による場合には、この
成長層の表面状態は低温で成長させた第一層目の成長層
(バッファ層)の膜厚及びこれに続いて昇温しで成長さ
れる第二層目の成長層の当該成長温度によって影響を受
けるため、電子デバイス素子を作り込んだとき期待通り
の良い特性が得られるような成長層表面を必ずしも得る
ことが出来ない。
However, in the case of this two-step growth method, the surface state of this growth layer is determined by the thickness of the first growth layer (buffer layer) grown at a low temperature and the subsequent growth by increasing the temperature. Since it is affected by the growth temperature of the second growth layer, it is not always possible to obtain a surface of the growth layer that provides good characteristics as expected when an electronic device element is fabricated.

特に、第一層目の膜厚が薄い場合に、続いて成長させる
第二層目の成長温度が高いと、単一のドメインの成長層
は得られたとしても、成長層の表面は荒れた面となる傾
向があった0例えば、低温成長で得られた薄い成長膜は
第二層目の成長層の成長温度まで昇温しでいる間1こア
ニールされてこの薄膜を構成している原子が動きバッフ
ァ層として働くわけであるが、第一層目の成長層の膜厚
が薄すぎると、アニール温度が高い場合には膜の凝縮が
起り成長層に凹凸が多く出来てしまう、また、極端な場
合には、Si表面が表われたりすることもあるので、そ
の上側の第二層目の成長層の表面が荒れてしまう。
In particular, if the first layer is thin and the second layer is grown at a high temperature, even if a single domain growth layer is obtained, the surface of the growth layer will be rough. For example, a thin film grown at a low temperature is annealed while the temperature is raised to the growth temperature of the second growth layer, and the atoms that make up the thin film are annealed. acts as a buffer layer, but if the first growth layer is too thin and the annealing temperature is high, the film will condense and the growth layer will have many irregularities. In extreme cases, the Si surface may be exposed, and the surface of the second grown layer above it may become rough.

このような成長層の表面荒れの発生を防止するためは、
第一層目の成長層の膜厚を厚くすればよい、しかし、膜
厚が厚すぎると、アニールを行っても原子の並び換えが
充分でなくなるため、良好なバッファ層とならない。
In order to prevent the occurrence of surface roughness on the growth layer,
It is sufficient to increase the thickness of the first growth layer, but if the film is too thick, the rearrangement of atoms will not be sufficient even after annealing, so it will not be a good buffer layer.

従って、この2段階成長法による場合には、成長層の表
面を鏡面かほぼこれに近い良い面にするためには、第一
層目の成長層の膜厚を100〜200八程度に精度良く
制御することが必要であるが、この制御が困難であった
。また、仮りに第−層の膜厚を制御出来たとしても、第
二層目の成長層の成長温度が通常の成長温度よりも高い
場合には、成長表面の荒れを押えることは困難であった
Therefore, when using this two-step growth method, in order to make the surface of the growth layer a mirror-like surface or a mirror-like surface, the thickness of the first growth layer must be adjusted accurately to about 100 to 200%. It is necessary to control this, but this control has been difficult. Furthermore, even if the thickness of the second layer can be controlled, if the growth temperature of the second growth layer is higher than the normal growth temperature, it will be difficult to suppress the roughness of the growth surface. Ta.

この発明は上述した従来の課題に鑑み成されたものであ
り、従って、この発明の目的は、第一層目の成長層の状
態及びその猪の成長層の成長温度にかかわらず、成長層
に電子デバイス素子を作り込んだとき良好な特性が得ら
れるような当該成長層の良好な表面状態、すなわち、い
わゆる鏡面を再現性良く実現出来、しかも、実施が容易
となる、化合物半導体層の成長方法を提供することにあ
る。
This invention has been made in view of the above-mentioned conventional problems, and therefore, an object of the invention is to make the growth layer grow regardless of the state of the first growth layer and the growth temperature of the growth layer. A method for growing a compound semiconductor layer that can achieve a good surface condition of the grown layer, that is, a so-called mirror surface, with good reproducibility so that good characteristics can be obtained when an electronic device element is fabricated, and that is easy to implement. Our goal is to provide the following.

(課題を解決するための手段) この目的の達成を図るため、この発明の化合物半導体層
の成長方法によれば、 シリコン(Si)基板上に当該基板と格子定数の異なっ
た化合物半導体層をヘテロエとタキシャル成長させるに
当り、 この基板の熱処理後、この熱処理温度よりも充分低い第
一温度で化合物半導体の第一バッファ層を薄膜として成
長させる工程と、 通常の成長温度での化合物半導体層の成長に先立ち、こ
の第一温度よりも高くかつ前述の第一バッファ層を構成
する原子が充分に再配列する高い第二温度で、この第一
バッファ層上に化合物半導体の第二バッファ層を成長さ
せる工程とを含むことを特徴とする。
(Means for Solving the Problem) In order to achieve this object, according to the method for growing a compound semiconductor layer of the present invention, a compound semiconductor layer having a lattice constant different from that of the substrate is formed on a silicon (Si) substrate by a hetero-layer. In performing the taxial growth, after heat treatment of this substrate, a step of growing a first buffer layer of a compound semiconductor as a thin film at a first temperature sufficiently lower than this heat treatment temperature, and a step of growing a compound semiconductor layer at a normal growth temperature. Prior to this, a second buffer layer of a compound semiconductor is grown on the first buffer layer at a second temperature higher than the first temperature and at which the atoms constituting the first buffer layer are sufficiently rearranged. It is characterized by including a process.

この発明の実施に当り、好ましくは、この基板の熱処理
温度を900〜1000℃程度の範囲内の温度とし、前
述第一温度を400〜450℃程度の範囲内の温度とし
、前述の第二温度を550〜600℃程度の範囲内の温
度とし、前述の通常の成長温度を650〜750 ’C
程度の範囲内の温度とするのが良い。
In carrying out the present invention, preferably, the heat treatment temperature of this substrate is within the range of about 900 to 1000°C, the aforementioned first temperature is within the range of approximately 400 to 450°C, and the aforementioned second temperature is preferably within the range of approximately 400 to 450°C. is within the range of about 550-600'C, and the normal growth temperature mentioned above is set at 650-750'C.
It is best to keep the temperature within a certain range.

(作用) この発明の構成によれば、2段階成長法を行うに当り、
Si基板の熱処理後、この基板上にこの熱処理温度より
も充分低い第一温度で化合物半導体の第一バッファ層を
成長させる。続いて、この第一バッファ層の成長を一旦
停止させてこの化合物半導体の通常の成長温度まで昇温
させる途中の中間の第二温度で第二バッファ層を成長さ
せる。続いて、この第二バッファ層の成長を一旦停止さ
せてこの化合物半導体の通常の成長温度にまで昇温させ
てこの温度で第二バッファ層上に化合物半導体層を成長
させる。この第二温度は、第一バッファ層を構成する原
子が充分に再配列して単一のドメインとなる温度であっ
てしかも通常の成長温度よりも低い温度とする。
(Operation) According to the configuration of the present invention, when performing the two-step growth method,
After the Si substrate is heat-treated, a first buffer layer of a compound semiconductor is grown on the substrate at a first temperature that is sufficiently lower than the heat treatment temperature. Subsequently, the growth of the first buffer layer is temporarily stopped and a second buffer layer is grown at a second temperature midway through the temperature rising to the normal growth temperature of this compound semiconductor. Subsequently, the growth of the second buffer layer is temporarily stopped, and the temperature is raised to a normal growth temperature for compound semiconductors, and a compound semiconductor layer is grown on the second buffer layer at this temperature. This second temperature is a temperature at which the atoms constituting the first buffer layer are sufficiently rearranged to form a single domain, and which is lower than the normal growth temperature.

この第二バッファ層を上述した第二温度で成長させるこ
とによって、第一バッファ層の膜厚にバラツキがあった
としても、その後に通常の成長温度で成長される化合物
半導体層の表面は良好な鏡面又はこれに近い面となる。
By growing this second buffer layer at the second temperature mentioned above, even if there are variations in the thickness of the first buffer layer, the surface of the compound semiconductor layer that is subsequently grown at the normal growth temperature will be good. It becomes a mirror surface or a surface close to this.

従って、第一バッファ層の成長条件を厳とに制御する必
要はなくなりその成長条件の範囲を広くとることが出来
るのでこの方法の実施が簡単かつ容易となる。
Therefore, there is no need to strictly control the growth conditions of the first buffer layer, and the range of growth conditions can be widened, making this method simple and easy to implement.

(実施例) 以下、図面を譬照して、この発明の詳細な説明する。(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

この実施例では、Si基板上に■−v族化合物半導体の
うち一例としてGaAs層tMOcVD法によって成長
させてウェハを得る場合につき説明する。
In this embodiment, a case will be described in which a wafer is obtained by growing a GaAs layer as an example of a -v group compound semiconductor on a Si substrate by the tMOcVD method.

第1図はこの発明の化合物半導体層の成長方法におゆる
成長温度の説明図であり、横軸に時間及び縦軸に温度(
℃)を取って示しである。第4図はこの発明の成長方法
の説明に供するウェハの部分的断面図である。尚、これ
ら図は、この発明を理解出来る程度に概略的に示しであ
るにすぎず、また、断面を表わすハツチング等は省略し
て示しである。また、これら図において、第2図及び第
3図に示した構成成分等と同一の構成部分等に対しては
同一の符号を付しで示し、その詳細な説明は省略する。
FIG. 1 is an explanatory diagram of the growth temperature used in the compound semiconductor layer growth method of the present invention, with time on the horizontal axis and temperature (on the vertical axis).
℃) is shown. FIG. 4 is a partial cross-sectional view of a wafer used to explain the growth method of the present invention. It should be noted that these drawings are only schematic representations to the extent that the present invention can be understood, and hatchings and the like representing cross sections are omitted. Further, in these figures, the same components and the like as those shown in FIGS. 2 and 3 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

また、以下説明する実施例は単なる好適例であるにすぎ
ないため、数値的条件、その他の条件はこの実施例にあ
げた例にのみ限定されるものではないこを理解されたい
Further, since the embodiment described below is merely a preferred example, it should be understood that the numerical conditions and other conditions are not limited to the examples given in this embodiment.

先ず、Si基板101Fr用意し、これを従来と同様に
、900〜1000℃程度の範囲内の好適な温度で加熱
処理を行ってその表面の清浄化を行う(第1図に工で示
す、) 次に、この基板10上に2段階成長法によって、GaA
s層を成長させる。そのため、第1段階では、従来と同
様に、温度を基板熱処理温度よりも充分に低い成長温度
、すなわち、400〜450℃程度の低温の第一温度に
まで炉内の温度を低下古せ、この低温度で原料ガスとし
て例えばトリメチルガリウム(Ga (CHs ) s
 )及びアルシン(AsH3)と、キャリアガスとして
水素(H2)ガスとを任意好適な成長条件で流し、Si
基板10上に200A以下の膜厚、好ましくは、1oO
〜200八程度の膜厚のGaAs層12を成長させる(
第1図に■で示す、)、このGaAs層は従来の第−層
(第3図に12で示す層)に対応しでおり、第一バッフ
ァ層として機能する。
First, a Si substrate 101Fr is prepared, and its surface is cleaned by heat treatment at a suitable temperature within the range of about 900 to 1000° C. as in the conventional method (indicated by a mark in FIG. 1). Next, GaA is grown on this substrate 10 by a two-step growth method.
Grow the s-layer. Therefore, in the first stage, as in the past, the temperature inside the furnace is lowered to a growth temperature sufficiently lower than the substrate heat treatment temperature, that is, the low first temperature of about 400 to 450 °C. For example, trimethylgallium (Ga(CHs)s) is used as a raw material gas at low temperature.
) and arsine (AsH3) and hydrogen (H2) gas as a carrier gas under arbitrary suitable growth conditions, Si
A film thickness of 200A or less, preferably 1oO
Grow a GaAs layer 12 with a thickness of ~200.8 cm (
This GaAs layer (indicated by ■ in FIG. 1) corresponds to the conventional -th layer (indicated by 12 in FIG. 3) and functions as a first buffer layer.

尚、200Aより厚い膜とすると良好なバッファ層とし
て機能しなくなる恐れがある。
Note that if the film is thicker than 200A, it may not function as a good buffer layer.

次に、この発明では第2段階のGaAs層の成長を行う
前に、第二バ・ンファ層16を成長させる。
Next, in the present invention, a second buffer layer 16 is grown before the second step of growing the GaAs layer.

この第二バッファ層16の成長に当り、先ず、原料ガス
等の供給を止めて、第一バッファ層12の成長を一旦停
止した後、この第一温度から徐々に炉内の温度を、好ま
しくは550〜600℃程度の範囲内の適当な第二温度
に上昇させる。この第二温度はGaAsの通常の650
〜750 ’Cの成長温度よりも低い温度であるが、こ
の第二温度へ昇温することによって、第一バッファ層1
2を構成する原子の並び換えが起って原子が再配列して
、単一のドメインとなるので、第一バッファ層12は有
効なバッファ層となる。尚、この程度の温度では、原子
が動くことによって生ずる表面の凹凸はそれ程大きくな
く、従って、この第一バッファ層12の膜厚が薄くても
、下地のSi基板10の表面が表われるようなことがな
くなる。
In growing the second buffer layer 16, first, stop the supply of raw material gas, etc., temporarily stop the growth of the first buffer layer 12, and then gradually lower the temperature in the furnace from this first temperature. The temperature is increased to a suitable second temperature within the range of about 550-600°C. This second temperature is the normal 650°C for GaAs.
By increasing the temperature to this second temperature, which is lower than the growth temperature of ~750'C, the first buffer layer 1
The first buffer layer 12 becomes an effective buffer layer because the atoms constituting the first buffer layer 12 are rearranged to form a single domain. Note that at this temperature, the surface irregularities caused by the movement of atoms are not so large, so even if the first buffer layer 12 is thin, the surface of the underlying Si substrate 10 is exposed. Things will disappear.

そして、この発明では、この第二温度で原料ガス等の供
給を再開して、第一バッファ層12上にGaAsの第二
バッファ層161Fr例えば1000〜5000Aの膜
厚に成長させる(第1図に■で示す、)、この第二バッ
ファ層16は、下地の第一バッファ層12に凹凸があっ
たとしても、凹凸は極めて少なく、それ以上温度を上昇
させてもこの第二バッファ層16の表面の平坦さに変化
が生じない。
Then, in the present invention, the supply of the raw material gas etc. is restarted at this second temperature, and the second buffer layer 161Fr of GaAs is grown on the first buffer layer 12 to a thickness of, for example, 1000 to 5000 A (see FIG. 1). ), even if the underlying first buffer layer 12 has irregularities, the second buffer layer 16 has very few irregularities, and even if the temperature is further increased, the surface of the second buffer layer 16 is There is no change in the flatness of

このような平坦性の良い第二バッファ層16の成長後、
炉内温度を再び温度を昇温させてGaAsの通常の成長
温度である650〜750度の範囲内の適当な温度にし
、その温度で原料ガス等を流して、従来と同様に、第二
バッファ層16上に、電子デバイス素子を作り込むため
のGaAsの通常の成長層14(従来の第二層目の成長
層に対応する。)を適当な膜厚で成長させる(第1図に
■で示す、)、この通常の成長層14は表面に凹凸の少
ない高品質の結晶であり、この成長層14に電子デバイ
ス素子を作り込んだときその良好な特性が確保出来る。
After growing the second buffer layer 16 with good flatness,
The temperature inside the furnace is raised again to an appropriate temperature within the range of 650 to 750 degrees, which is the normal growth temperature for GaAs, and at that temperature, raw material gas, etc. is caused to flow, and the second buffer is heated as before. On the layer 16, a normal growth layer 14 of GaAs (corresponding to the conventional second growth layer) for manufacturing electronic device elements is grown to an appropriate thickness (marked with ■ in FIG. 1). ), this normally grown layer 14 is a high quality crystal with few irregularities on the surface, and when an electronic device element is built into this grown layer 14, its good characteristics can be ensured.

尚、上述した実施例で特に言及しなかった種々の成長条
件は設計に応じて任意好適な条件として設定することが
出来る。
Incidentally, various growth conditions not specifically mentioned in the above-described embodiments can be set as arbitrary suitable conditions depending on the design.

この発明は上述した実施例にのみ限定されるものではな
く、多くの変形又は変更をなし得ること明らかである0
例えば、GaAs以外の■−V族化合物半導体材料例え
ばInP、GaP、これらの混晶、その他の材料を用い
てもこの発明を適用することが出来る。
It is clear that the invention is not limited only to the embodiments described above, but that many variations and modifications can be made.
For example, the present invention can be applied to other materials such as -V group compound semiconductor materials other than GaAs, such as InP, GaP, mixed crystals thereof, and other materials.

また、この化合、物半導体層の成長をMOCVD法以外
の法認外成長させる場合にも、この発明の成長方法を適
用して好適である。
Furthermore, the growth method of the present invention is suitable for application to non-legal growth of the compound semiconductor layer using a method other than MOCVD.

(発明の効果) 上述した説明からも明らかなように、この発明の化合物
半導体層の成長方法によれば、第一層目の第一バッファ
層の他に、従来の第二層目に対応する化合物半導体の成
長層の成長をを行う前に、この第一バッファ層の成長温
度と化合物半導体層の通常の成長温度との間の中間の温
度で第一バッファ層上に第二バッファ層を成長させるの
で、第一バッファ層の膜厚のバラツキが大きくても、ま
た、その膜厚が薄くても、この第二バッファ層上に成長
させた常の成長層の表面は平坦となり、いわゆる鏡面又
はこれに近い面とすることが出来る。
(Effects of the Invention) As is clear from the above description, according to the method for growing a compound semiconductor layer of the present invention, in addition to the first buffer layer of the first layer, a layer corresponding to the conventional second layer is formed. Before performing the growth of the compound semiconductor layer, a second buffer layer is grown on the first buffer layer at a temperature intermediate between the growth temperature of this first buffer layer and the normal growth temperature of the compound semiconductor layer. Therefore, even if the thickness of the first buffer layer varies greatly or is thin, the surface of the normal growth layer grown on the second buffer layer will be flat and have a so-called mirror surface or It is possible to obtain a surface close to this.

また、この発明によれば、このような良好な成長層を得
るためのバッファ層の成長条件の範囲が広くなるので、
この発明の成長方法は簡単かつ容易である。
Furthermore, according to the present invention, the range of buffer layer growth conditions for obtaining such a good growth layer is widened.
The growth method of this invention is simple and easy.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の化合物半導体層の成長方法の説明に
供する成長温度の説明図、 第2図は従来方法の説明に供する成長温度の説明図、 第3図は従来方法の説明に供するウェハ断面図、 第4図はこの発明の化合物半導体層の成長方法の説明に
供するウェハ断面図である。 10・−8i基板、    + 2−・・第一バッファ
層14・−通常の成長層、  + 6−・・第二バッフ
ァ層。 特許出願人   工業技術院長  飯塚 幸三温度(’
C) 温度(’C) N  ヘ  (h  clo  ミ c;>   (:)    ’S>   も()q  
  z    cb    ()   c)従来のウェ
ハの断面図 第3図 この発明の説明に供するウェハ断面図 第4図
FIG. 1 is an explanatory diagram of growth temperature to explain the compound semiconductor layer growth method of the present invention, FIG. 2 is an explanatory diagram of growth temperature to explain the conventional method, and FIG. 3 is a wafer diagram to explain the conventional method. Cross-sectional view FIG. 4 is a cross-sectional view of a wafer used to explain the method for growing a compound semiconductor layer of the present invention. 10.-8i substrate, +2-..first buffer layer 14.-normal growth layer, +6-..second buffer layer. Patent applicant Kozo Iizuka, Director General of the Agency of Industrial Science and Technology ('
C) Temperature ('C) N he (h clo mic;> (:) 'S> mo()q
z cb () c) Cross-sectional view of a conventional wafer (Fig. 3) Cross-sectional view of a wafer used to explain the present invention (Fig. 4)

Claims (2)

【特許請求の範囲】[Claims] (1)シリコン(Si)基板上に当該基板と格子定数の
異なった化合物半導体層をヘテロエピタキシャル成長さ
せるに当り、 前記基板の熱処理後、該熱処理温度よりも充分低い第一
温度で化合物半導体の第一バッファ層を薄膜として成長
させる工程と、 通常の成長温度での化合物半導体層の成長に先立ち、こ
の第一温度よりも高くかつ前記第一バッファ層を構成す
る原子が充分に再配列する高い第二温度で、前記第一バ
ッファ層上に化合物半導体の第二バッファ層を成長させ
る工程と を含むことを特徴とする化合物半導体層の成長方法。
(1) When heteroepitaxially growing a compound semiconductor layer having a lattice constant different from that of the substrate on a silicon (Si) substrate, after heat treatment of the substrate, the first layer of the compound semiconductor is grown at a first temperature sufficiently lower than the heat treatment temperature. growing a buffer layer as a thin film, and prior to growth of the compound semiconductor layer at a normal growth temperature, a second temperature higher than the first temperature and at which the atoms constituting the first buffer layer are sufficiently rearranged; A method for growing a compound semiconductor layer, comprising the step of growing a second buffer layer of a compound semiconductor on the first buffer layer at a temperature.
(2)前記基板の熱処理温度を900〜1000℃程度
の範囲内の温度とし、前記第一温度を400〜450℃
程度の範囲内の温度とし、前記第二温度を550〜60
0℃程度の範囲内の温度とし、前記通常の成長温度を6
50〜750℃程度の範囲内の温度とする請求項1記載
の化合物半導体層の成長方法。
(2) The heat treatment temperature of the substrate is within a range of about 900 to 1000°C, and the first temperature is 400 to 450°C.
The second temperature is within a range of 550 to 60°C.
The temperature is within the range of about 0°C, and the normal growth temperature is 6°C.
2. The method for growing a compound semiconductor layer according to claim 1, wherein the temperature is within a range of approximately 50 to 750°C.
JP11928088A 1988-05-18 1988-05-18 Compound semiconductor layer growth method Granted JPH01290220A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11928088A JPH01290220A (en) 1988-05-18 1988-05-18 Compound semiconductor layer growth method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11928088A JPH01290220A (en) 1988-05-18 1988-05-18 Compound semiconductor layer growth method

Publications (2)

Publication Number Publication Date
JPH01290220A true JPH01290220A (en) 1989-11-22
JPH0573333B2 JPH0573333B2 (en) 1993-10-14

Family

ID=14757475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11928088A Granted JPH01290220A (en) 1988-05-18 1988-05-18 Compound semiconductor layer growth method

Country Status (1)

Country Link
JP (1) JPH01290220A (en)

Also Published As

Publication number Publication date
JPH0573333B2 (en) 1993-10-14

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