JPH01293725A - Error detecting circuit with statistical bit error correcting function - Google Patents

Abstract

PURPOSE:To improve transmission quality and to decide whether a bit error is an accidental error or a regular error inherent in a system by arranging a bit error correcting circuit at the rear step of a bit error detecting circuit and providing an error position polynomial calculating circuit between the bit error detecting circuit and the bit error correcting circuit. CONSTITUTION:A know pattern generating circuit 1 generates a known pattern fitting the synchronization of input data from an input terminal 6 and sends the generated known pattern to a bit error detecting circuit 2. The circuit 2 collates the input data with the know pattern, increases the count of an error counter 5 for 1 whether one bit error exists, and sends the bit position of the bit error to an error position polynomial calculating circuit 4. Further, error information can be obtained, and an error position polynomial can be generated by repeatedly inserting the pattern into the circuit 2 and collating the pattern with the input data. A bit error correcting circuit 3 corrects every bit error by examining bit positions corresponding to respective bits from the top bit to the last bit of the input data and inverting every bit in which its bit position is the solution of the polynomial and outputs the corrected data.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to data transmission systems, and particularly to data transmission systems that contain bit errors inherent to the equipment during device development or during quality determination after manufacturing. This article relates to an error detection circuit with statistical bit error correction function in a transmission system.

[Conventional technology]

Conventionally, this type of test function continuously inserts known pattern data onto the transmission line of the transmitting station, receives the data at the receiving station, and compares it with known pattern data similar to the above. It was not possible to correct errors in the data, only to check the quality of the device by detecting errors by verifying data sent and received.

[Problem to be solved by the invention]

The conventional test function described above continuously inserts known pattern data onto the transmission line of the transmitting station, and the receiving station receives the data and compares it with the same known pattern data as above to detect bit errors. Therefore, whether the bit error is an accidental bit error caused by interference such as noise, attenuation distortion, or pulse noise, or it is due to a regular error unique to the device between the data insertion point and the receiving section) iAυ Not only do we not know whether the error is true, but even if regular bit errors occur that are unique to the device, there is no way to correct the error when actually transmitting data, and incorrect data is sent to the terminal side. There was a problem.

Means for Solving CHIM] The error detection circuit with statistical bit error correction function of the present invention is a bit error detection circuit with a statistical bit error correction function that performs matching between known pattern data inserted at a transmitting station and known pattern data generated at a receiving station in a data transmission system. In a detector that continuously detects bit errors in a transmission path using an error detection circuit, a bit error correction circuit is installed after the bit error detection circuit, and the bit error detection circuit and the bit error correction circuit are combined. By providing an error locator polynomial calculation circuit between them, it is possible to extract statistical bit error positions and control bit errors.

[Effect]

In the present invention, a transmitting station inserts known pattern data, a receiving station compares the sent pattern data with the known pattern, and outputs error information by counting the number of error bits. Generate an error level polynomial.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 is a known pattern generation circuit that receives input data from input terminal 6, and 2 is a bit error detection circuit that matches the input data from input terminal 6 with the known pattern of known pattern generation circuit 1 and υ. be. Then, a bit error detection circuit 2 is configured to continuously detect bit errors in the transmission path, which collates known pattern data inserted at a transmitting station, which will be described later, and known pattern data generated at a receiving station, which will be described later. ing.

3 is a bit error p correction circuit installed after the bit error detection circuit 2, and 4 is an error locator polynomial calculation circuit installed between the bit error detection circuit 2 and the bit error correction circuit 3. It is configured to be able to extract statistical bit error positions and also to control bit errors.

5 is an error counter inputting the output of the bit error detection circuit 2, and T is an output terminal from which data output is obtained. Note that the portion surrounded by a dashed line indicates a portion having a test function.

FIG. 2 is a diagram showing an example of a system configuration when the present invention is added to a data transmission system.

In the figure, 21 indicates a transmitting station and 22 indicates a receiving station.

23 is a pattern generation and pattern insertion circuit, 24 is a line interface, 25 is a data service unit,
26 is a transmission path, 27 is a data service unit, 28 is a line interface, and 29 is an error detection circuit with a tl-1R statistical bit error correction function. Here, line interface 24.28 and data service unit) 2
5.27 and the like are devices that have functions such as waveform shaping for digital transmission.

Then, known pattern data is inserted onto the transmission path in a pattern generation and pattern insertion circuit 23 on the transmitting station 21 side. The receiver 22 converts the received data into an error detection circuit 29 with a statistical bit error correction function according to the present invention.
send to.

Next, the operation of the embodiment shown in FIGS. 1 and 2 will be explained.

First, in FIG. 1, input data input from an input terminal 6 is input to a known pattern generation circuit 1 and a bit error 9 detection circuit 2. The known pattern generation circuit 1 includes a synchronization establishment circuit (not shown), and generates a known pattern matching the cycle of input data from the input terminal 6 and sends it to the bit error detection circuit 2.

The bit error detection circuit 2 compares the input data from the input terminal 6 with a known pattern, increments the error counter 5t-1 each time there is a bit error, and sends the bit position to the error locator polynomial calculation circuit 4. Then, by repeating the pattern insertion and pattern matching nine times, error information (error rate) is obtained and an error locator polynomial is generated.

Next, a case will be described in which the pattern generation and pattern insertion circuit 23 on the transmitting station 21 side shown in FIG. 2 stops inserting known patterns and allows data from the outside to pass through to perform actual data communication.

Input data input from the input terminal 6 in FIG. 1 is input to the bit error correction circuit 3. This beep) vA! The 0 correction circuit 3 includes a memory buffer and an error position determination circuit (not shown), and the error position determination circuit determines the bit position corresponding to each bit from the first bit to the last bit of the input data. It is checked whether the pit position becomes zero by substituting it into the polynomial, and if the pit position is the solution to the erroneous 9-position polynomial, the error is corrected by inverting the bit in the correction circuit 3 and outputting data.

〔Effect of the invention〕

As explained above, the present invention inserts known pattern data at the transmitting station, collates the transmitted pattern data with the known pattern data at the receiving station, and outputs error information by counting the number of error bits. By generating an error locator polynomial from the position of , when performing actual data communication, the pit position of input data is multiplied by the error locator polynomial each time, and if it is a solution, the bit is inverted and corrected to correct data. This has the effect of effectively increasing transmission quality.

Bit errors are noise on the transmission path, especially when used during device development or when determining the necessity after manufacturing.

This has the advantage that it can be determined whether the bit error is an accidental bit error due to interference such as attenuation distortion or pulse noise, or a regular error inherent to the system, and defects such as failures can be quickly discovered.

Further, since regular bit errors can be corrected by the error correction circuit, there is an effect that error information of only the occasional bit error p can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a system configuration when the present invention is added to a data transmission system. 1... φ known pattern generation circuit, 2... Bit error detection circuit, 3... Bit error correction circuit, 4...
...Error locator polynomial calculation circuit, 21...Sending station, 2
2.φ...Receiving station, 23...Pattern generation and pattern insertion circuit.

Claims (1)

[Claims] In a data transmission system, in a detector that continuously detects bit errors in a transmission path by a bit error detection circuit that collates known pattern data inserted at a transmitting station and known pattern data generated at a receiving station, A bit error correction circuit is installed after the detection circuit, and an error position polynomial calculation circuit is installed between the bit error detection circuit and the bit error correction circuit to extract statistical bit error positions and correct bit errors. What is claimed is: 1. An error detection circuit with a statistical bit error correction function, characterized in that it is capable of controlling