JPH01302243A - Camera - Google Patents

Abstract

PURPOSE:To securely inform a photographer of a release/lock state by providing a release button operation state decision means and a buzzer sounding controller. CONSTITUTION:A body CPU 200 and a flash 7 are powered on by one battery 130 and the CPU 200 performs various operations during intermediate flash charging. Therefore, the flash charging and automatic focus adjustment can not be performed in parallel, so focusing is performed at the completion point of the flash charging and it is decided whether or not a flash is required, thereby making the decision making accurate. When the flash is required and a flash device 7 is not charged, it begins to be charged and even if a release switch SW1 is closed thereafter for a specific period, the shutter is not released, so that the CPU 200 serves as a charging decision means. The gap of the flash charging is utilized so as to inform the photographer of the lock state where in the shutter can not be released, and the LED display circuit 560 of a display warning circuit 500 is used to blink an LED in a finder and make a buzzer BZ sound intermittently, so that the CPU 200 serves as a buzzer operation controller.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a release switch for starting a release operation that is activated by operating a release button on a camera body, and a release switch for starting a release operation that is activated by operating a release button on a camera body; A charging voltage discriminating means for discriminating the charging voltage, and a release locking means for prohibiting the operation of the release switch in the low voltage discriminating state by the charging voltage discriminating means. Even if the release button is operated, the release switch is prohibited from operating and the release operation is not activated until the charging voltage for light emission reaches the level required for light emission (hereinafter referred to as
This state is referred to as a release button state), and the present invention relates to a camera that can prevent wasted photography due to failure to emit flash light.

[Conventional technology]

Conventionally, in the above-mentioned camera, when the charging voltage for flashing the flash device reaches a predetermined voltage or higher and the flash becomes ready to emit light, a display device installed in the viewfinder or the like is used to display this fact. The shutter is configured so that the photographer can recognize that the release is locked by the absence of the display, or conversely, the release is locked until the flash device's charging voltage for firing reaches a predetermined voltage. There is known a configuration in which the above-mentioned display device is used to display this information to inform the photographer.

[Problem to be solved by the invention]

However, in the conventional camera described above, in the former configuration, the absence of a predetermined display allows the photographer to recognize that the release is locked, so it is not necessary to proactively indicate that the release is locked. On the other hand, in the latter configuration,
Although this system uses a predetermined display to notify the photographer that the release is locked, be careful; inexperienced or novice photographers often overlook this display and cannot release the shutter. You may not know that it is locked.

Therefore, when such photographers operate the release button to start the release operation and the release operation fails, they do not assume that the release is due to the release lock status, but instead assume that there is some malfunction. There have been times when I have worried that this has occurred, or mistakenly thought that the battery has run out and ended up replacing the battery unnecessarily.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a camera that can reliably notify a photographer that the release is locked.

[Means to solve the problem]

The camera according to the present invention has a characteristic configuration that includes an operation presence/absence determination means for determining whether or not the release button is operated, and an operation presence/absence determination means that determines whether the charging voltage for light emission of the flash device is high or low with respect to a predetermined voltage in the operation presence determination state. A control device is provided for operating a buzzer when the release lock means prohibits the operation of the release switch in a low voltage discrimination state by the charging voltage discrimination means.

[For production]

In other words, when the release button is operated while the release is locked, the control device sounds a buzzer to appeal to the sense of hearing, which is not necessary for shooting, rather than to the sense of sight. Since it is possible to tell even if the shutter release is not in the locked state, it is possible to reliably notify the photographer that the release is locked.

In addition, the buzzer does not continue to sound while the release is locked, but only when it is determined that the release button has been pressed, so it will not be noisy while other operations are being performed. Furthermore, only when the photographer operates the release button with the intention of photographing, can the photographer be informed that the release is locked and is not yet in a state in which photography can be performed.

In particular, for notifications and warnings in other operations, such as focus notifications or inoperable warnings in automatic focus adjustment operations,
If a buzzer is provided to notify the completion of film rewinding, this buzzer can also be used to make the process extremely simple and inexpensive.

[Example〕 Hereinafter, the present invention will be described in detail based on the drawings.

FIGS. 2(a) to 2(c) are schematic diagrams of the overall configuration of the camera according to the present invention. This camera has a camera body (
1) and the lens mount (I) of this camera body (1).
A) a photographic lens (9) detachably attached to the lens;
It consists of a flash device (7) detachably attached to the hot shoe (IB) of the camera body (1).

FIG. 2(A) shows a state in which the photographic lens (9) is not attached, and FIG. 2(C) shows a state in which neither the photographic lens (9) nor the flash device (7) is attached. (1
1) is the release button for shooting, (12)
) is a main switch that switches the camera between an enabled state and a disabled state.

(13) and (14) are a pair of operation keys for switching the operating state, (13) is a photographing mode switching key, and (14) is a self-timer key. Reference numeral (15) denotes a display window of a display device consisting of a liquid crystal display, which displays operating states, film counts, etc. switched by operating the pair of operation keys (13) and (14). (16
) is the photographic lens (
(17) is a contact group for transmitting and receiving signals with the photographic lens (9) when the photographic lens (9) is attached to the lens mount (IA). . (18) is a focus mode switching lever for switching between automatic and manual focusing of the photographic lens (9), and (19) is a back cover release lever for opening the back cover (IC). It is. Further, although not shown, a mid-rewind switch for rewinding the film midway is provided on the bottom surface of the camera body (1).

FIG. 3 is a block diagram of the internal electric circuit of the camera according to the present invention, and also shows the photographing lens (9) and flash device (7).

(200) is a CPU (hereinafter abbreviated as body CPU) provided in the camera body (1) for controlling the camera operation, and is used to control each device in the camera body (1) and the camera such as the flash device (7). Control the entire operation. That is, the body CPU (200) performs a photometry operation, an automatic focus adjustment operation, a release operation, a flash emission operation, an operation for exchanging data with the flash device (7) and the photographic lens (9), and the like.

Is (700) a flash operation system? A control circuit on the flash device (7) side whose main component is a CPU for I (hereinafter abbreviated as flash CPU).
). (900) is a photographic lens (9)
An internal circuit provided in the lens stores various lens information (open F-number, focal length, etc.) specific to the photographic lens (9).

In the camera body (1), (300) is an IC for a photometry circuit and an interface circuit (hereinafter abbreviated as LMIF), (400) is a focus detection circuit, and (500) is a display warning circuit. Further, in the flash device (7), (730) is a booster/light emitting circuit.

(130) is a power supply battery that is detachably attached to the camera body (1), and is similar to the above-mentioned L M I F (300
), focus detection circuit (400), and display warning circuit (500)
, and also supplies power to various motors, magnets, etc. that will be described later. (134) is a battery check circuit that checks the voltage level of the power supply battery (130). As will be explained later, this camera does not have a dedicated flash device (
7) is configured so that power is supplied to the flash device (7) from the power battery (130) when the flash device (7) is attached, and this battery check is performed depending on whether the dedicated flash device (7) is attached or not. The voltage determination level by the circuit (134) is configured to be different.

(140) is a DC-DC converter, and the body CPU
(200) from the output terminal (210) of the control signal (P
WC) is received at the input terminal (143), and its control signal (P
While the input terminal (WC) is at “L” level, it becomes active and the input terminal (
The output of the power battery (130) applied between the pair of output terminals (141) and the ground terminal (142) is boosted.
4) Output at [5,5V] and [3,3V] from (145), respectively. (150) is a voltage regulator, with input terminal (151) and ground terminal (152)
A stable voltage [3,3
V].

(160) is a backup capacitor for the body CPU (200). This backup capacitor (160) is connected to the DC power supply when the power battery (130) is loaded and the body CPU (200) is in a sleeve state.
- When the DC converter (140) is not operating, it is normally charged by the output from the voltage regulator (150) and maintains a potential of [approximately 3V]. When the body CPU (200) is activated and the DC-DC converter (140) starts boosting operation, the backup capacitor (160) becomes [approximately 5V] from the DC-DC converter (140) through the diode (146). will be charged up to. As will be described in detail later, during boost charging in the flash device (7), the DC-DC converter (14
0) is stopped and the body CPU (200) enters the sleeve state, but at this time the power supply from the DC-DC converter (140) is stopped, so the backup capacitor is used for [400 m5] during flash charging. (160) causes the body CPU (
200). DC-DC converter (1
The diode (146:!) provided on the output side of the voltage regulator (150) and the diode (154) provided on the output side of the voltage regulator (150) are used to connect the capacitor (160) to the body CPU (200). to prevent backflow.

(194) is a capacitor for resetting the body CPU (200), which resets the body CPU (200) when the power battery (130) is attached to the camera body (1).
) to initialize the body CPU (200) by outputting a reset signal to the reset terminal (203) of the body CPU (200).
(201) is the power supply terminal of the body CPU (200),
(202) is a ground terminal of the body CPU (200).

(190) is a high-speed clock oscillation circuit, and the body CPU
(200) to input terminal (204) [8,38MH2
] Outputs a high-speed clock signal. (192) is a low-speed clock oscillation circuit which outputs a low-speed clock signal of [32,768 KHz] to the input terminal (206) of the body CPU (200).

This camera is configured to reduce the weight of the flash device (7) by supplying power to the flash device (7) from the power battery (130) of the camera body (1). As will be described in detail later, the booster/light emitting circuit (730) of the flash device (7) is directly connected to the power supply battery (130), while the control circuit (700) of the flash device (7)
) is configured such that power is supplied from the output sides of the DC-DC converter (140) and the voltage regulator (150), respectively. (170) is a PNP transistor as a switching element that controls the power supply to the control circuit (700) of the flash device (7), and is connected to the output terminal (200) of the body CPU (200).
In response to the control signal (FPWC) from 12), the control signal (FPWC) becomes active while at "L" level, supplies power to the control circuit (TOO) of the flash device (7), and performs its control. Power supply is stopped when the signal (FPWC) changes to "H" level.

(214) is an output terminal that outputs a control signal (FCHG) for boosting and charging control to the flash device (7). By setting this control signal (FCHG) to “H” level, the flash device (7) The boost circuit in the boost/light emitting circuit (730) is activated, and this control signal (PCI (G) is
By setting it to I level, the operation of the booster circuit in the booster/charging circuit (730) is stopped. In addition, this control signal (FC
There is an X contact (SWx) on the signal line where HG) is transmitted.
is connected.

This X contact (SWx) is mechanically closed when the leading curtain of the focal plane shutter (not shown) completes travel.
The information is sent to the control circuit (700) of the flash device (7).
transmitted to. After the release is completed, this X contact (SWx) is opened in conjunction with charging of the focal plane shutter.

(216) sets the flash selection signal (C3FL) to LM
This is an output terminal that outputs to the input terminal (316) of the I F (300), and is used as a flash selection signal ( C5FL)
L Increase to level 11.

(21B) is a pair of shutter magnets (3) for driving the leading and trailing curtains of the focal plane shutter.
40), control signal (1c/2c) for (342)
MGS) to L M I F (300) input terminal group (
318), and (222) is an output terminal that outputs a control signal (FMGS) for the aperture magnet (344) to operate the aperture to the input terminal (320) of LMI F (300). , (220) is
The control signal (AMl) for the automatic focus adjustment motor (hereinafter abbreviated as AF motor) (392) is L.
The output terminal group (224) that outputs to the input terminal group (322) of the MIF (300) controls the motor (hereinafter referred to as the winding motor) (391) that winds and rewinds the film. This is an output terminal group that outputs the signals (WMI, WM2) to the input terminal group (324) of LMI F (300).

(226) is an input/output terminal group for transmitting and receiving a control signal to the photometric circuit and a photometric signal from the end measurement circuit to and from the input/output terminal group (326) of L M I F (300). (330) and (331) are a pair of light-receiving elements for measuring ambient light using a two-part photometry method;
32) is a light receiving element for measuring flash light.

(370) is an AF encoder circuit that detects the position of the movable lens part of the shadow lens (9) when performing automatic focus adjustment operation, and inputs the input terminal (300) of the LMI
37B) Output the navel detection signal. The detection signal is sent to the output terminal (37) of LMI F (300).
9) to the input terminal (27) of the body CPU (200)
9).

(301) is the power supply terminal for the analog circuit of LMI F (300), and (302) is the power supply terminal for LMI F (300).
) logic circuit power supply terminal, (303) is a pair of shutter magnets (340), (342), aperture magnet (344), and a pair of motors (391), (3
This is the power supply terminal for the power circuit of the LMIF (300) to which power is supplied together with the driving bridge circuit (380) and the like for (92). (304) is L M I F (30
0) analog circuit ground terminal, (305) is L M
IF (300) logic circuit power supply terminal, (30
6) is the ground terminal for the power circuit of LMI F (300).

(307) is a drive output terminal for the front curtain shutter magnet (340) of the focal plane shutter;
08) is a drive output terminal for the rear curtain shutter magnet (342) of the focal brain shutter, (30
9) is a drive output terminal for the aperture magnet (344), and (350) is a pair of motors (391).

(392) is a drive output terminal for the drive bridge circuit (380).

(310) is a control circuit (700) of the flash device (7).
), and (312) is an output terminal for outputting a clock signal during serial communication.

(260) is an output terminal that outputs the lens selection signal (C5L) to the lens internal circuit (900), and the body CPU (20
0) sets the lens selection signal (CSL) to the "L" level when performing serial communication, which will be described later, with the lens internal circuit (900).

(262) is frequency-divided from the [8, 38 MHz] high-speed clock source oscillation section when performing serial communication between the lens internal circuit (900) and the control circuit (700) of the flash device (7). This is an output terminal that outputs a clock signal for serial communication (e.g. [65,536 KHz]), and this clock signal is transmitted to the intra-lens circuit (900) during serial communication with the intra-lens circuit (900). , the control circuit (700) of the flash device (7)
) during serial communication with L M IF (30
This clock signal input to the input terminal (362) of L M I F (300) is transmitted to the output terminal (312
) is output.

(264) is an input terminal for data when performing serial communication between the lens internal circuit (900) and the control circuit (700) of the flash device (7);
When performing serial communication with the lens (900), the lens internal circuit (900)
0), while during serial communication with the control circuit (700) of the flash device (7), the input/output terminal (310) of the LMIC (300)
The data signal input to is output from the output terminal (364) of the LMIF (300), and the data signal
is input.

(266) is a control circuit (70) of the flash device (7).
This is the output terminal for data when performing serial communication with LMI F (300).
66), the data signal input to L M IF (
300) from the input/output terminal (310) of the flash device (
7) is transmitted to the control circuit (700).

(101) to (107) are a group of contacts provided on the hot shoe (IB) of the camera body (1), and when the flash device (7) is attached to the hot shoe (IB), the flash device (7) (101), (101), (101), 701) is the positive power supply contact (VDD) for flash charging.
O), (102), (702) are 7 rough '/
Negative power supply contact (PGND) for charging
, (103).

(703) is the control circuit (700) of the flash unit W (7).
) power supply contact (FVoo+), (104),
(704) Control signal for flash charging (
FC) IG) and the signal transmission contact (Fl) for the opening/closing signal of the X contact (SWx), (105), (705
) is the data signal transmission contact (F2) during serial communication,
(106), (706) are clock signal transmission contacts (F3), (106), (706) during serial communication.
) is a grounding contact (DGND) for the control circuit (700) of the flash device (7).

(111) to (115) are a group of contacts (indicated by (17) in Figure 2 (A)) provided inside the lens mount (IA) of the camera body (1), and are connected to the photographing lens (9).
is attached to the lens mount (18), the corresponding contact groups (911) to (911) provided on the photographic lens (9)
915) for exchanging data signals. When explained in combination for each corresponding contact point, (111)
, (911) is a grounding contact for the lens circuit (900), (112), (912) is a ground contact from the lens circuit (900) during serial communication to the body CPU (20
0), (113), (9
13) is the body CPU (200) during serial communication.
A contact (114) for transmitting a clock signal from the lens to the in-lens circuit (900).

(914) is the lens selection signal (C5L) during serial communication.
), (115), (915
) is a contact point for supplying power to the in-lens circuit (900).

(121) to (125) are a group of contacts for reading the DX code provided in the cartridge chamber (not shown) inside the camera body (1), and there are conducting parts and non-conducting parts on the outer peripheral surface of the film cartridge. Touch the DX code attached as a combination of , and read the sensitivity information of the film.

(270) sends a control signal to the focus detection circuit (400) and a focus detection circuit (400) to the focus detection circuit (400).
This is a group of input/output terminals for transmitting and receiving focus detection signals from (400).

(280) is a drive output terminal group for the liquid crystal display circuit (510) for displaying various information on the display window (15) on the top surface of the camera body (1) out of the display warning circuit (500), (290) Of the display warning circuit (500),
A drive output terminal group (298) for the LED display circuit (560) for displaying various information in the finder is as follows:
This is a drive output terminal for the buzzer (580) in the display warning circuit (500).

The switches, which are opened and closed in conjunction with buttons and keys provided on each part of the camera, have one end grounded and the other end pulled up inside the body CPU (200). The status signal is sent to the body CPU (200
) is entered.

(630) is a main switch (SWM) that opens and closes in conjunction with the slide of the main switch (12) provided on the top surface of the camera body (1), and its status signal is sent to the input terminal of the body CPU (200). (230).

(632) is a photometry switch (SWl) that is closed by the first press operation on the release button (11), and its status signal is sent to the input terminal (200) of the body CPU (200).
232). And this photometering switch (6
32), photometry operation and automatic focus adjustment operation are started. (634) is a release switch (SWx) that is closed by a second press operation following the first press operation on the release button (11), and its status signal is sent to an input terminal of the body CPU (200). (234). Then, the release operation is started by closing the release operation switch (634).

(636) is a shooting mode switching switch (636) that is closed in conjunction with the pressing operation on the shooting mode switching key (13).
SWxoot), and its status signal is sent to the body CPU (SWxoot).
200) is input to the input terminal (236). and,
Each time this photographing mode changeover switch (636) is closed, the photographing mode is switched.

(63B) is a self-timer switch (
SWstty), and its status signal is sent to the body CPU (SWstty).
200) is input to the input terminal (238). and,
Each time this self-timer switch (638) is closed, the normal mode and self-timer mode are switched.

(640) is an intermediate rewind switch (SW*tw) that is closed during rewind operation in conjunction with the slide of the intermediate rewind switch provided on the bottom surface of the camera body (1), and (642) is an open back cover. The camera back opening switch (Sk++c) is opened in conjunction with the operation on the lever (19) and closed in conjunction with the closing operation of the camera back, and (644) is the lens exchange button (16).
) is a lens attachment switch (SWLtg) that is closed when a lens is replaced, and (646) is a focus mode changeover switch (SWAyz) that is closed by an operation of the focus mode changeover lever (18).
and each of those switches (640) and (642)
, (644), (646) are sent to the corresponding input terminals (204) of the body CPU (200).
.

(242), (244), and (246).

(654) is a sprocket signal generating switch (SWsp) that opens and closes in conjunction with a sprocket (not shown) that rotates as the film is fed;
) is the aperture encoder (
The aperture encoder signal generation switch (SW, , ) is opened and closed in conjunction with the switch (not shown), and both switches (SW, 6
54) and (656) are the body CPU
(200)'s corresponding input terminals (254), (2
56).

The body CPU (200) and the flash device (7
) control circuit (700) and boost/light emitting circuit (73
0) will be further explained using FIG.

In FIG. 1, the same numbers are given to those already explained in FIG. 3, and explanations will only be added as necessary.

As already explained, in this camera, power for the flash device (7) is supplied from the power battery (1) on the camera body (1) side.
130). Then, to the boosting/emitting circuit (730) of the flash device (7),
From the power supply battery (130) to the power supply line (j! l), (
It is configured to be directly supplied with power using f.

Therefore, while power is being supplied to the booster/light emitting circuit (730), there is a possibility that the power applied to the body CPU (200) may fall below the minimum operating voltage due to large power consumption. Therefore, as already explained, a backup capacitor (160) and a pair of diodes (146), (
154) A charge hold circuit consisting of
While power is being supplied to the light emitting circuit (730), its capacitor (
160) to supply power to the body CPU (200).

The body CPU (100) is in a low power consumption mode (low speed clock mode) while power is being supplied to the booster/light emitting circuit (730). In this (low speed clock mode), when the body CPU (200) is in the sleeve state, the low speed clock generation circuit (1) is used as the system clock.
It is in a state where it operates with a [32,768 KHz] clock signal from the body CPU (200).
7) The applied voltage is in a normal operating state within the range of [2.5V to 5.5V] (7).

Note that there is one more operation mode for the body CPU (200), and this operation mode is a (high-speed clock mode) that consumes more power than the above-mentioned (low-speed clock mode). This (high speed clock mode)
(200) is activated to control a series of photographing operations, when high speed is required, the system clock is a clock signal of [8.38 MHz] from the high speed clock generating circuit (190). It is in the operating state, and the voltage applied to the body CPU (200) is [4,
It operates normally in the range of 5V to 5.5V].

Then, the body CPU (200) terminates the operation of the booster/light-emitting circuit (730) for a predetermined period of time, and switches on the power source battery (
While waiting for the recovery of the DC-DC converter (130)
40) and connect the backup capacitor (16).
0) until it reaches [approximately 5V], switch the operation mode to (high-speed clock mode), and then
7) determines the charging state of the capacitor for light emission, and if the charging voltage has not reached the light emission level (
Hereinafter, this state will be referred to as an unfilled state), and the booster/light-emitting circuit (730) will be operated again for a predetermined period of time (hereinafter, this operation will be referred to as flash charging), and the charging voltage of the capacitor for light-emitting will reach the light-emitting level. The above-mentioned operation is repeated until the charging state is reached (hereinafter, this state is referred to as a charging state). In other words, by performing flash charging intermittently, the power battery (130) is
(200) and the flash device (7) without increasing the capacity of the power battery (130).
The structure is such that both operations can be performed in parallel.

Furthermore, when performing flash charging intermittently,
Since flash charging is performed at predetermined intervals,
For example, in a configuration in which the power supply voltage to the body CPU (200) is directly checked by hardware and flash charging is interrupted when the voltage falls below a predetermined voltage, it is possible to eliminate the need for a circuit for detecting the voltage, CPU
By using the timer that the (200) is inherently equipped with, a configuration for performing flash charging intermittently can be realized with a very simple configuration, a small number of parts, and cost reduction.

In addition, when performing flash charging repeatedly intermittently, the body CPU (200) uses the battery check circuit (134) to control the power supply while flash charging is not being performed (hereinafter, the operation during this period is referred to as a control operation). It is configured to determine the capacity of the battery (130) and repeat flash charging until the charging voltage reaches the light emission level only if the capacity is sufficient to withstand flash charging.

The above-mentioned operation will be further explained using the time charts of FIGS. 4(a) and 4(0). As shown in FIG. 4(a), flash charging is performed for [40 S] from timing <t4) to timing <t,>. During this time, the operation mode of the body CPU (200) is (low speed clock mode).

As shown in FIG. 4 (El), for a period of [50m5] from the timing <ts> when flash charging was interrupted, the power supply battery (130) is waited for recovery, and the control signal (PWC) is set to "L".
” level and start the operation of the DC-DC converter (140) <ts+>, DC-DCC for [5ms]
- Formula - After the rising edge of data (140), start outputting the high-speed clock signal (ts*>, wait for the rising edge of the high-speed clock for [2I!ls], and then switch the system clock to the high-speed clock. Set the operation mode to (high-speed clock mode) (ts 3> - In this (high-speed clock mode), first, the control signal (
After setting the FPWC to "L" level and starting power supply to the control circuit (700) of the flash device (7), serial communication is performed with the flash CPU (710) for checking the state of charge, etc. After that, displays, warnings, and other operations as well as checking the power supply battery (130) are performed, the system clock is switched to a low-speed clock, the operation mode is returned to (low-speed clock mode), and the control signal (PWC) is After setting the level to ``H'' and stopping the operation of the DC-DC converter (140), the power supply battery (
130), flash charging is started again (tb). Flash charge interruption time (<ts)
~<ti>) is approximately [100 ois].

Then, as shown in Figure 4 (a), the flash device (
The charging voltage of the capacitor for light emission in 7) gradually increases by repeating flash charging as described above.
The light emission level is reached at the timing <t+3>.

The control of flash charging by the body CPU (200) described above is performed by a control signal (hereinafter referred to as a charge control signal) (FCHG) output from the output terminal (214) of the body CPU (200).

Returning to FIG. 1 and continuing the explanation, this charging control signal (F
The signal line (14) through which CHG) is transmitted is connected to the X contact (
It also serves as a signal line for transmitting open/close signals for SWx). In other words, the timing at which the charging control signal (FCIIG) is transmitted is until the exposure control operation is started, while the timing at which the opening/closing signal of the X contact (SWx) is transmitted is only during the exposure control operation. By focusing on the fact that the timings at which these two signals are transmitted are completely independent, by using the same signal line (!4), the hot shoe (IB) and the foot part (7C) of the flash device (7) By reducing the number of contacts provided in the hot shoe (IB), the area occupied by the hot shoe (IB) can be kept small, and by reducing the number of parts related to these contacts, it is possible to reduce costs and improve reliability.

However, during exposure control operation, the flash CPU (710)
It is configured as follows to be able to receive the opening/closing signal of the X contact (SWx) and to prevent flash charging from being performed by opening/closing the X contact (SWx).

The signal line (j2.) is connected to the base of a switching transistor (734) for starting and stopping flash charging by the booster/light emitting circuit (734). When the charging control signal (FCIIG) is at the "H" level, this transistor (734) is activated and a current is generated between the base and emitter, and the charging/light-emitting circuit (734) is activated.
0) is performed. On the other hand, the charging control signal (FCH
When G) is at “L” level, this transistor (734)
is in a non-operating state, and the charging/light-emitting circuit (730) does not operate. During exposure control operation, this charge control signal (FCHG
) is maintained at "L" level. Further, a diode (736) blocks current from flowing to the flash CPU (710) side.

During exposure control operation, charging prohibition signal (OSCSTP) from output terminal (718) of flash CPU (710)
is maintained at “L” level, and the transistor (734
) is no longer working. In addition, flash C
The output circuit of the output terminal (718) of P U (710) has an open drain configuration, and when flash charging is not prohibited, this output circuit is configured to be in an inactive state and disconnected from the transistor (734). has been done.

On the other hand, during exposure control operation, the output terminal (721) of the flash CPU (710) is pulled up internally.
The output signal (XEN) is maintained at "H" level.

Therefore, by closing the X contact (SWx), the input signal to the input terminal (720) of the flash CPU (710) drops from the "H" level to L11, and as a result, the input signal to the input terminal (720) of the flash CPU (710) falls from the "H" level to can detect the closing of the X contact (SWx). In addition, a diode (18
2) blocks current from flowing to the body CPU (200) side.

Referring again to the time chart in FIG. 4 (a), the charging control signal (FCHG) is activated when the main capacitor of the flash device (7) reaches the light emission level before the exposure control operation is started at timing <t□>. intermittently until reaching “
It becomes H” level and flash charging is performed.
<j! When the exposure control operation is started at the timing of +>, the output signal (X
EN) becomes "H" level. The time chart in Fig. 4 (a) shows the two signals (FC) IG), (X
It also shows the state of the signal line (f,) which is combined with EN).

During exposure control operation, at timing <t,>, the X contact (SWx) is closed in synchronization with the completion of travel of the front curtain of the shutter, causing this signal line (14) to go to the "L" level. Flash CPU of its status signal (710)
The input to causes the flash device (7) to emit light.

On the other hand, power is supplied to the flash CPU (710) from the power supply battery (130) to the charging/light-emitting circuit (730) through other lines (2,) such as power supply lines (i,) and (ffil). It is configured to In other words, the power consumption when performing flash charging is
(710), so if the power supply line is shared, there is a risk that the flash CPU (700) will malfunction due to impedance problems.To avoid this, separate power supply lines are used. This makes it possible to configure the line and the shape of the contacts to have a capacity commensurate with the amount of power supplied.

Power supply line (
2,) is provided from the output side of the DC-DCC type controller (140) and the voltage regulator (150) to the flash CPU (700), and a switching transistor (170) is provided along the way.
It is interposed. The operation of this transistor (170) is controlled by a control signal (FPWC) from an output terminal (212) of the body CPU (200).

Then, when charging the flash, the body CPU (200) sets the control signal (FPWC) to the "°H" level, stops power supply to the flash CPU (700), and exclusively operates the charging/emission circuit (730). On the other hand, when the flash is not being charged, the (FCHG) is set to +1L" level to supply power to the flash CPU (710), and the body CPU The power supply line (!,) is also connected to the reset circuit (732) of the control circuit (700) of the flash device (7). The control signal (FPW
When power supply starts due to the falling edge of C), the flash CPU
(710) is configured to be reset.

In addition, the flash CPU (710) is a body CPU
Due to serial communication with U (200),
Since it is operated by a high-speed clock, as mentioned earlier, it is configured so that power is supplied to the flash CPU (710) from the output side of the DC-DC converter (140). U (710
The timing at which the control signal (FPWC) is set to the "L" level to start power supply to the DC-DC converter (140) is after the output of the DC-DC converter (140) is sufficiently stabilized. To explain using the time chart in Figure 4 (+1), (tsz
This is after the timing of >, specifically, the timing of (tss> when switching to the high-speed clock mode).

Flash device (7) equipped with a camera according to the present invention
As will be explained in detail later, as shown in FIGS. 2(a) and 2(TI), the light emitting part (7A) is exposed by protruding from the flash body (7B) and can emit light, and the light emitting state is The part (7A) is housed in the flash body (7B) and is configured to be switched to a housed state in which light cannot be emitted. Then, the body CPU (200) detects the closing of the main switch (630) by turning on the main switch (12) on the side of the camera body (1), which is a starting switch, and switches on the flash CPU (710). , is configured to output a control signal for causing the light emitting section (7A) to protrude from the flash body (7B) (hereinafter, this operation will be referred to as flash pop-up). As a result, when the operation switch on the flash device (7) side is in the ON state and the flash device (7) can be operated, the flash CPU (710) operates the drive mechanism to be described later to activate the light emitting unit. (7A) to the flash body (7A).
B).

Therefore, when it is necessary to use flash light from the flash device (7), the light emitting part (7A) of the flash device (7) is activated in conjunction with the ON operation of the main switch (12), which is always performed to start the camera. By making it stand out,
The flash device (7) can be reliably activated without the risk of forgetting to operate it, unlike when a separate dedicated operation tool is provided, and it is possible to take pictures without failure. Furthermore, since the flash device (7) shifts to the operating state when the camera is started, and the flash device (7) is already in the operating state when the release button (11) is operated, the flash device (7) is not activated when the release button (11) is operated. It is possible to reduce the time lag that occurs when the flash device (7) is brought into operation according to the result of photometry operations that are performed in conjunction with each other;
Even if the release operation is suddenly started by operating the release button (11), it is possible to respond quickly.

In addition, the body CPU (200) is a camera body (
When the main switch (630) is opened due to the off operation of the main switch (12) on the side 1), the flash CP is activated.
The U (710) is configured to output a control signal for housing the light emitting section (7A) in the flash body (7B) (hereinafter, this operation is referred to as flash pop-down). This allows the flash CPU (
710) operates the drive mechanism to house the light emitting part (7A) in the flash body (7B).

Therefore, in the operating state of the flash device (7), the state of the main switch (12) on the camera body (1) side can be determined by looking at the state of the light emitting part (7A), and the light emitting part of the flash device (7) can be determined. (7A) protruding from the flash body (7B) indicates that the main switch (12) on the camera body (1) side is in the ON state, so the main switch (12) on the camera body (1) side This makes it possible to prevent forgetting to cut it.

Note that when the operating switch on the flash device (7) side is in the off state, the light emitting part (7A) remains housed in the flash body (7B) regardless of the state of the main switch (12) of the camera. Also, when the main switch (12) on the camera body (1) side is turned on, the flash device (7
) is turned on, the flash pop-up is performed at the timing when the photometry switch (632) is closed.

To explain using the time chart in Figure 4 (a), <t,>
At the timing of , press the main switch (
12) is input and detected at the timing of <11>, the control signal (PWC) is set to “L” level and D
The operation of the C-DC converter (140) is started, and the control signal (FPW
C) to “L” level and flash CPU U (71
0) to perform flash pop-up. Once the flash popup is completed <t4>
, start flash charging.

Also, the main switch (12) of the camera body (1) is turned off at the timing of (tz6>, and it is turned off at the timing of (tz7).
When detected at the timing of >, the DC-DC converter (1
40) and flash CPU (7
10) and performs a flash pop-down from the timing of (hs>).When the flash pop-down is completed (tzq>, the body CPU (2
00) is in the sleeve state.

On the other hand, the body CPU (200) has a photometry switch (
632), the distance measuring operation for photometry and automatic focus adjustment starts. Then, based on the result of the photometry operation, it is determined whether photography using flash light from the flash device (7) (hereinafter referred to as flash photography) is necessary. The criteria for determining that flash photography is necessary are when the subject is dark and its luminance is lower than a predetermined luminance, and when the subject is backlit. That is, the body (200) constitutes charging voltage determining means.

If it is determined that flash charging is necessary, first check the charging status of the main capacitor of the flash device (7), and if it is not fully charged, start flash charging and press the release button (11). Even if the release switch (634) is pressed to the second step and the release switch (634) is closed, the release operation is not performed (hereinafter, this operation is referred to as an incomplete release lock state), that is, the release lock means is composed of a body CPU (200). Further, the photometry switch (632) constitutes operation/non-operation determining means for detecting the presence or absence of an operation on the release button (11).

In addition, when it is determined that flash photography is necessary and the main capacitor of the flash device (7) is fully charged, and when it is determined that flash photography is not necessary, automatic After the focus adjustment operation is performed and the photographing lens (9) reaches a focused state, the photometry operation is performed again to determine whether a flash ti shadow is necessary.

In other words, power is supplied to the body CPU (200) and the flash device (7) from one power supply battery (130), and as described above, while flash charging is performed intermittently, the body CPU Because each operation (200) is performed, flash charging and automatic focus adjustment cannot be performed in parallel, regardless of whether the photographic lens (9) is in focus or not. First, perform light metering to roughly determine whether flash photography is necessary. If it is determined that flash photography is necessary and the battery is not fully charged, first charge the flash and use flash photography. Be prepared. Then, when charging is completed, automatic focus adjustment is performed, and as a result, when the photographic lens (9) is in focus and the subject to be photographed is reliably captured, metering is performed again and flash photography is performed. By determining whether or not flash photography is necessary, it is possible to prioritize flash charging and enable flash photography at an early stage, while also being able to accurately determine whether flash photography is necessary.

The above operation will be explained using the time chart of FIG. 4(a). Closing of the photometric switch (632) causes an interrupt to the body CPU (200). At the timing of <11>, press the photometry switch (63).
An interrupt occurs due to the closing of 2), and the body CPU (2
00) interrupts flash charging, switches the operating mode to (high-speed clock mode), performs photometry and distance measurement, and determines whether or not flash photography is necessary. Since the main capacitor of the flash device (7) is not fully charged at this time, flash charging is started at the timing <t.>. After this <[,> timing, the release is in an incomplete release lock state, and even if the release switch (634) is closed at the <t,> timing,
Release operation is not started, i.e. body CP
U (200) constitutes charging voltage determining means.

In the incomplete release lock state described above, in order to notify the photographer of this, the LED of the display warning circuit (500) is activated while the flash is not being charged.
The display circuit (560) is used to blink the LED in the finder, and the buzzer (500) of the display warning circuit (500) is activated.
580) is configured to sound intermittently. That is, the body CPU (200) is activated by the buzzer (580).
) constitutes a control device for operating.

To explain using the time chart in Figure 4 (a), (t+o
The display warning circuit (500
) is set to "H" level. The output timing of this control signal is the timing at which serial communication ends (tsd
Hereafter.

Further, the uncharged release lock state is not released even if the main capacitor of the flash device (7) becomes fully charged, but is released when the photometry switch (632) is opened once. ing.

In other words, if the uncharged release lock state is released when the main capacitor of the flash device (7) transitions to the fully charged state, the release button (11) is
This is because if the pressing operation continues up to the third step, the release operation will be performed at a timing different from the intended timing.

If the unfilled release lock state becomes fully charged, the display warning circuit (500) is turned on until the unfilled release lock state is released in order to notify the photographer.
LED in the viewfinder using the ED display circuit (560)
is lit continuously, and the display warning circuit (500
) is configured to continuously sound a buzzer (580).

To explain using the time chart in Figure 4 (a), (t+z
During flash charging, which started from the timing of (t
's> becomes a complete state, which means (t
+4>, the control signal to the display warning circuit (500) is set to the "H" level from the timing (t+s) by being detected by serial communication during the control operation starting from the timing (t+s).

Then, at the timing of (t+a>), release switch (
634) is released, and then the photometry switch (632) is released at a timing of (1+1>), thereby releasing the incomplete release lock state and also sending a control signal to the display warning circuit (500). Change to "shi" level.

After that, at timing <t's>, press the first step of the release button (11) again to release the photometry switch (6).
32) is closed, it is determined that flash photography is necessary by the same operation as before, and since the flash is fully charged at this time, the flash is not charged and the release is not locked. The focus adjustment operation is started at the timing of (t+w>). After the focus adjustment operation is completed, the photometry operation and the distance measurement operation are performed again, and the AE lock state (a state where the determined aperture and shutter speed are not changed) is established. The camera shifts to the AF lock state (the state in which the photographic lens (9) is not driven), and the release switch (634), which was closed at the timing <tz.>, is detected at the timing (tz+>), and the release operation is activated. will be started.

After taking a picture using flash light from the flash device (7), from the timing of (hs>), charge the shutter and wind the film by one frame, (b4)
The release operation ends at the timing of .

In addition, with this camera, when shooting with a flash, the flash starts charging again after the release operation is completed, but when shooting with normal natural light (hereinafter referred to as natural light shooting) instead of flash shooting, is configured so that flash charging is not performed after the release operation is completed.

In other words, if you take a flash photo, there is a high probability that the next photo will be a flash photo as well, whereas if you take a natural light photo, there is a high probability that the next photo will also be a natural light photo. Flash charging, which consumes a huge amount of power, is performed only when there is a high probability of being executed after the release operation is completed, causing inconvenience in flash photography. This is to reduce the consumption of the power source battery (130).

The time chart in FIG. 4(a) shows a case where flash charging is started again from the timing <t's> since flash photography has been performed.

Next, the operation of the body CPU (200) will be explained based on the flowcharts shown in FIGS. 5 to 14. Prior to explaining the operation, the flags used in each flowchart and the status signals serially communicated with the flash cPU (710) will be summarized.

First, flags will be explained.

(SMF) is a main switch flag to remember that the main switch (Sol) has been opened.When the main switch (SN) is opened, it becomes 1", and when the main switch (Sol) is closed, it becomes 1". It becomes O”. (W.A.
KEN) is an interrupt enable flag for permitting an interrupt due to the closing of the photometric switch (SW+), and is 1" in a state in which an interrupt is permitted, and 0" in a state in which an interrupt is prohibited.

(SIF) is a photometry switch flag to continue charging control when the photometry switch (SW l ) is closed. It is “0” from the start of charging until the photometry switch (SWz) is opened. It is “1” in other cases. (S2F
) is a release switch flag to continue charging control when the release switch (S6) is closed, and is "0" from the start of charging until the release switch (S6) is opened; otherwise, it is "0". 1”.

(RELDIS) is a release prohibition flag for prohibiting the release operation, and is "1" when the release operation is prohibited, and 0 when the release operation is permitted. (AFTER) is the release prohibition flag after the release operation. This post-release flag is "1" from the time the release operation is completed until the body CPU (200) enters the sleeve state, and from the time of startup until the release operation is completed. It is “0”.

(FLF) uses a flash device (7) for photography (
This is a flash mode flag to indicate (flash mode), and it is "1" when it is (flash mode), and the flash device (7) is not used for shooting (natural light mode).
(CHG RE Q) is a flash charging request flag indicating that there is a charging request for the flash device (7), and is 1 when there is a charging request.
'°, and is "0" when there is no charging request.

(GOFCHG) is a charge start flag indicating that the flash device (7) starts flash charging, and is set to “1” when all the conditions for flash charging by the flash device (7) are met and flash charging starts. , and is "0" at other times.

(RDYLOCK) is an unsatisfied lock flag that indicates an unsatisfied lock state, and is “1” in an unsatisfied lock state.
”, otherwise it is “0”. (BZF) is
This is a buzzer flag to request the sound of the buzzer (560) in the incomplete lock state, and is "1" when requesting the buzzer sound, and is 0 in other cases. (AF
AEL) is a lock flag that indicates that the focus state and photometry state are locked (hereinafter referred to as AF-AE lock state). When the automatic focus adjustment operation is completed in the AF-AE lock state (focus adjustment state in which the lens (9) is stopped and the shadow lens (9) is fixed), it becomes "1".
In other cases, it is O''.

(RCF) is a camera back flag that stores the open/closed status of the camera's camera back.
is "0" in the open state, and "1" in the closed state when the back cover is closed and the back cover switch (SWac) is closed. (RE
WF) is a rewinding flag indicating the rewinding state of the film, which is "1" from the time when rewinding is completed until the back cover is opened, and is "0" otherwise.

Next, the status signal will be explained.

(SMOFF) is a main switch open/close signal that indicates the status of the main switch (SWM) on the camera body (1) side. It is "0" when the main switch (SWM) is closed, and it is "0" when the main switch (SWs) is open. In the state, it is "1". (POPEN) is a pop operation enable/disable signal indicating whether or not flash pop operation is possible. In the state where flash pop operation is not possible, it is "1", and flash pop operation is possible. The main switch opening/closing signal (SMOFF) and pop operation enable/disable signal (POPEN) are the body CPU (200).
from there to the flash CPU (710).

(FLON) is a flash usability signal indicating whether or not the flash device (7) is in the operating state.
) is in the operating state where it protrudes from the flash body (7B) and is exposed; otherwise it is "1".
It is 0゛. (RDY) is a flash charging completion signal that indicates the charging state of the main capacitor of the flash device (7), and is "1" in a fully charged state and "0" in an unfilled state.
It is. (INFOP) is a pop operation status signal indicating the operating state of the flash pop operation, and is "0" during flash pop operation, and "l" in other states.
It is. Then, the flash enable/disable signal (POPEN
), the flash charge signal (RDY), and the pop operation status signal (INFOP) are the flash CPU (710
) to the body CPU (200).

FIG. 5 is a flowchart of a startup routine (power-on reset) that is started by loading the power battery (130) into the camera body (1).

When the power battery (130) is loaded, it first disables various interrupts (I2), which will be described later, and performs a port initialization to stop the operation of various motors and magnets.
DC-D with control signal (PWC) set to “°H” level
Stopping the operation of the C converter (140), controlling the control signal (FP
The power supply to the control circuit (700) of the flash device (7) is stopped by setting the control circuit (700) of the flash device (7) to “H” level, and the charge control signal (F
CHG) is set to "Lo" level to prohibit flash charging, etc., and set each output terminal to the initial state <I4>.

Next, the liquid crystal display circuit (51) of the display warning circuit (500)
0), the LED display circuit (560), and the buzzer (580), and clear various displays and warnings.+16) After clearing the contents of the RAM,
8>, set the main switch flag (SMF) to “1”,
The photometry switch flag (SIF) is set to "°1'', the release switch flag (S2F) is set to "1", and the release prohibition flag (RELDIS) is set to "0" (not in the prohibited state).
The after-release flag (8FTER) indicates before release.
°0, set the flash mode flag (FLF) to “0” (natural light mode), and set the flash charge request flag (C
HGREQ) is set to 0' which is not in the requested state, the charge start flag (GOFCHG) is set to 0'° which is not in the start state, the lock flag (AFAEL) is set to 0° which is not in the AF-AE lock state, and the 1M flag (RCF ) to "1", which indicates the back cover is closed, and the rewind flag (REWF) to "0", which indicates that the film rewind is not completed.<11
10>.

After that, the S)7 proutine (S) shifts to the sleeve state.
TP) (1112>).

Figure 6 shows the stop routine (
STP) is a flowchart.

When entering this routine, the first step is to disable various interrupts.
1102>, stop the timer operation 11104>,
Perform an output port reset (power-on reset) in the same way as routine #4>, set each output terminal to its initial state, and erase the LED and turn off the buzzer (
Do not process the LCD) <#106>, perform flag processing, set the release inhibit flag (RELD IS) to 0°, which is not in the inhibited state, and set the after-release flag (AFTER
) is set to “0” indicating before release, and the unfilled lock flag (
RDYLOCK) is set to 0', which indicates that it is not in an incomplete lock state, the buzzer flag (BZF) is set to "0", which indicates that it is not in a buzzer request state, and the lock flag (AFAEL) is set to AF.
- Reset each to "0" which is not in the AE lock state (11108>).

After that, check the status of the main switches (SWs) and set the interrupt flag (WAKEN) to "I1110" only when the main switch (sW+) is in the closed state.
Set to 1 to enable interrupts caused by opening of the photometry switch (sW, ) 11112>, and then enable timer interrupts (1114>. This timer interrupt will be described later, but when not flash charging, This interrupt is used to scan the boat every [250 m5] and check whether there is any change in the input.Then, the charging start flag (GOFCHG) is checked (+1116>).

If the charging start flag (GOFCHG) is set and flash charging is to be started, then a subroutine (BATCHK) for checking battery capacity is called, and the battery check circuit (134) checks the power supply battery (130). Please check the capacity +1122>,
Depending on the result, if it is determined that the power battery (130) has sufficient capacity to charge the flash, the process proceeds to (1126>) and the power battery (130) has sufficient capacity to charge the flash. If it is determined that there is no battery remaining, jump to (l1142>) and select a sequence that does not perform flash charging.

(1126> sets the timer setup time to [
400m5], then start the timer <#12B>, switch the system clock (Φ5ys) from the high speed clock signal [8,38M1lz] to the low speed clock signal [32,768KHz] (low speed clock mode). After stopping the high-speed clock signal (#132>, the control signal (pwc) is set to "H" level to stop the operation of the DC-DC converter (140) (1134>), and the charging control signal (FCH
After setting G) to "H" level to start flash charging (1136), the process proceeds to (1160>).

On the other hand, the charging start flag (GOFCIIG
) is reset and there is no need to start flash charging, and when there is a request to start flash charging at (11124>) but the capacity of the power supply battery (130) is insufficient, (11142> Proceed to step 1 and set [250m5] as the timer setup time, then start the timer <1l144>, enable external interrupts (11146>, and convert the system clock (Φ5ys) to a high-speed clock signal [8,38MHz]. to the low-speed clock signal [32,768KHz] (low-speed clock mode) #148>, stop the high-speed clock signal (11150>), and switch the control signal (PW
C) to the “H” level and the DC-DC converter (1
40) after stopping the operation <11152>, <1
1160>.

<11160> enables interrupts. The interrupts permitted here are a timer interrupt every [250 m5] during normal operation, a timer interrupt every [400 m5] during flash charging, and a hard interrupt caused by closing the photometry switch (SW+). Thereafter, at (11180>), the device enters the sleep state and waits for input of an interrupt signal. In this sleep state, only the low-speed clock generation circuit (192), the liquid crystal display circuit (510), and the timer are operating.

FIG. 7 is a flowchart of an interrupt routine for processing the timer interrupt and hard interrupt described above.

When either a timer interrupt or a hard interrupt occurs, first the timer is stopped 1202>, the timer interrupt is disabled 11204>, and then the unfilled lock flag (R
DYLOCK) <11206>.

If the unfilled lock flag (RDYLOCK) is set and it is in the unfilled locked state, the process proceeds to <1216).

If the unfilled lock club (RDYLOOK) has been reset and is not in the unfilled locked state, then the charging control signal (FCHG) is checked <11208>.

If the charge control signal (FCHG) is at "L" level, that is, if charging is not in progress, it is a normal timer interrupt or a hardware interrupt, and the charge control signal (FCHG) proceeds to (121B>).
If IIG) is at "H" level, that is, if charging is in progress, it is a timer interrupt or hardware interrupt during flash charging, and after the charging control signal (FCHG) is set to "L" level and flash charging is stopped. (11210>, reset the charging start flag (GOFCHG) to “O”12
12>, to recover the power battery (130) and charge the backup capacitor (160) [50 m
5] After waiting, proceed to <1214> and (+1216>).

In <216>, the buzzer flag (BZF) is set to "l" to request a warning buzzer sound in the unfilled lock state, and then the process proceeds to (1218>, <1
218>, the control signal (PWC) is checked.

If the control signal (PWC) is at “°L” level, that is, D
If the C-DC converter (140) is in operation, this is a hard interrupt during control operation, and the process returns to the step where the interrupt occurred. On the other hand, the control signal (PWC) is “H”
If the level is DC-DC converter (140)
If it is not in the operating state, it is an interrupt in the sleeve state,
(Startup determination routine after 11230 (?WAKE)
Proceed to.

The startup determination routine (?WAKE) first disables interrupts (1230), resets the interrupt enable flag (WAKEN) to “O”°, and disables hard interrupts caused by the closing of the photometry switch (SW, ) (1232). >, then check the status of the main switch (SW, ) (1
If the main switch (SWW) is closed, the process proceeds to <1240>; if the main switch (SWM) is open, the process proceeds to <11280>, and in both cases the main switch flag (SMF) is checked.

(1240> and main switch flag (SMF) is 1″
If it is set to "O", it indicates that the main switch (SW+<) has been closed from the open state, and the main switch flag (SMF) should be reset to "O" (1124).
2>, Flash charging request flag (CIIGREQ)
After setting “1” which is the request state (1244>
, it should display an on display (124) to indicate that it has been started.
6>, please call the subroutine (PWRUP) to switch to high-speed clock mode (248), and call the subroutine (POPF) to perform flash pop-up.
After calling (1250>L), the startup routine (W
AKE) (1260>).

Also, <1240> sets the main switch flag (SMF).
is reset to “0”, the main switch (S
WX) indicates that it has been in a closed state for some time,
Next, it is checked whether there is a switch input by closing the back cover opening switch (SW, l,), focus mode changeover switch (SWar/x), and lens mounting switch (SWLLx) ($252>).

If there is a switch input, proceed to (a256), and if there is no switch input, then check the charging request flag (CHGREQ) (1254>.Charging request flag (C)lG
If I'1EQ) is reset to '0'', flash charging is not necessary and the process jumps to the stop routine (STP) <+1270>.In addition, the charging request flag (C
If IIGREQ) is set to "1", flash charging is required and the process proceeds to (a256>). (1125
6> calls a subroutine (PWRUP) for switching to (high-speed clock mode), and then jumps to the startup routine (KE) <1260>.

On the other hand, the main switch flag (SMF
) is set to “1”, the main switch (S
W,) indicates that it has been in an open state for some time,
Jump to stop routine <STP><#2
70>. Furthermore, if the main switch flag (SMF) is reset to "0" at (11280>), this indicates that the main switch (SWM) has been released from the closed state, and the main switch (sh,) is set to 1. ” to indicate that the main switch (12) has been turned off (a284), and a subroutine to switch to (high-speed clock mode) (PWR
After calling <11286> (tlP), a subroutine (POPFL) is called to perform a flash popdown.
) to call 11288>, charging request flag (CHG
REQ) is not in the request state° After resetting to “0” <
11290>, jump to stop routine (STP>) (11270>.

FIG. 8 is a flow chart of the startup routine (WAKE>).

When this routine is entered, a boat scan is first performed to check whether there is any change in the input (1302>. Then,
Call the subroutine (?TNIL) that performs the initial winding operation and determines its success or failure, and then press the camera back switch (SW*c).
), it is determined whether or not an initial winding operation of the film is necessary, and if necessary, the initial winding operation is performed (11303>).

Next, check the status of the halfway rewind switch (SW*tw) +1304>, halfway rewind switch (SW*yw)
) is closed, the charging request flag (CHGREQ
) is reset to “0” which is not in the requested state (+130
6>, Proceeds to the rewinding control routine for rewinding the film by driving the motor (391) (1310>, when the rewinding of the film is completed, the liquid crystal display circuit (510)
+1 to indicate that rewinding is complete on the display window (15)
312>, after setting the rewinding flag (REWP) to "1" indicating that the rewinding is completed <1314>
, jump to stop routine (STP) <11
316>.

If the rewind switch (SW*t) is not closed during the process, then check the status of the shooting mode changeover switch (SW 11312>), and if the shooting mode changeover switch (SL+onz) is closed, The process proceeds to the mode processing routine for switching the shooting mode <1320>
, the explanation of this routine will be omitted.

If the shooting mode selector switch (SWxoot) is not closed, then check the status of the self-timer switch (S-5°, +1322), and if the self-timer switch (SWsEty) is closed, the self-timer The process proceeds to a self-processing routine for switching between the timer mode and the normal mode (1330>, but a description of this routine will be omitted).

If the self-timer switch (SWstLy) is not closed, then check the status of the release switch (SWZ) (1332) and close the release switch (sh,
) is closed, then the release switch flag (S2F) is checked <11334>.

If the release switch flag (S2F) is set to "1", it indicates that the release switch (SWZ) has been closed from the open state, and after resetting the release switch flag (S2F) to "0"<11336>
, jump to the switch processing routine (SON) (1
1340>.

Also, at (11334>) release switch flag (52
If F) is reset to "0", it indicates that the release switch (S6) has been in the closed state from before, and the charging request determination routine (?C) after <1360>
Proceed to the IGRE exit).

If the release switch (S6) is closed at (11332>, then check the status of the photometry switch (SW, ). switch flag (SIF)
Check (11344>. Photometry switch flag (
If SIF) is set to "l", it indicates that the photometry switch (SWl) has been closed from the open state, and after resetting the photometry switch flag (SIF) to "0"(1346>, Switch processing routine (SON)
Jump to (+1350>.

Additionally, if the photometry switch flag (SIF) is reset to "0" in (1344), the photometry switch (SWI)
) has been in a closed state for some time, and (1
360> and the subsequent charge determination routine (?CHGREQ).

Furthermore, even if the photometry switch (Sl) is not closed at (11342>), the process proceeds to the charging determination routine (?CHGRE port) after (11360>).

In the charging request determination routine (?CHGREQ), first check the charging request flag (CHGREQ).
0> If the charging request flag (C) IGRE port) is reset to "0°" and flash charging is not required, jump to the stop routine (STP) <1380>
.

If the charging request flag (CHGRIQ) is set to "1" and flash charging is necessary, then the buzzer flag (BZF) is checked (#362>).

If the buzzer flag (BZF) has been reset to “0” and the buzzer (580) does not need to sound, <1368>
If the buzzer flag (BZF) is set to '1' and the buzzer (580) needs to sound, then check the status of the photometry switch (SWI) <113
64>. If the photometry switch (SWl) is open (
11368>, and if the photometry switch (S-1) is closed, the buzzer (580) and LED display circuit (56
0) to display the uncharged lock (1136
6>, proceed to (136B>. In addition, the buzzer (580) and LED display circuit (560) activated in (11366>)
The unfilled lock display due to the stop routine (ST
P> is stopped at <1106>.

(+1368>, the control signal (FPWC) is set to "L" level to start power supply to the control circuit (700) of the flash device (7), and in order to reset the flash CPU (710) [20m5] After waiting (1
370) Flash CPU via serial communication (710
) to call the subroutine (RFL) that receives data from #372>, and the subroutine (?FCHGON) that determines whether flash charging can be performed.
) after calling <#374), stop routine <
Jump to STP>(1380>).

FIG. 9 is a flowchart of the switch processing routine (SON).

When this routine is entered, the subroutine (PWRUP) for switching to high-speed clock mode is called (1402>), and then the battery capacity check subroutine (B
ATCHK) is called to check the state of consumption of the power battery (130) (1403). Next, call the film rewind determination subroutine (REWCHK) to check whether rewinding is complete 11404>
, if rewinding is completed, release lock processing is performed.

Thereafter, the control signal (FPWC) is set to "L" level to start power supply to the control circuit (700) of the flash device (7).
) after waiting [20+ms] for reset of (1
406>, read the film sensitivity information <1408>
, (1410) and the subsequent photometry routine (SLOOP).

In the photometry routine (5LOOP), first serial communication is performed with the lens internal circuit (900), and after inputting various lens data (open F value data and focal length data) <11410>, the lock flag (AFAEL) is input. )
(1412>) and check the lock flag (AFA
Photometry/distance measurement is performed only when EL) is reset to “0” and the AF-AE lock state is not established (+1
414>.

After that, a subroutine <RFL> that performs serial communication with the flash CPU (710) is called (11416>. In this subroutine (RFL),
The flash CPU (710) receives the above-mentioned flash usability signal (FLON), flash charging signal (RD'/), and the like.

Next, arithmetic processing is performed to calculate exposure using the Apex method and determine whether or not flash photography is necessary, and if the subject is low brightness or backlit, flash photography is performed (flash mode). If possible, set the flash mode flag (FLF) to 1", but in other cases, reset the flash mode flag (FLF) to "0" to perform natural light shadowing (natural light mode). After transmitting the result to the flash CPU (710) via serial communication <++420>, the post-release flag (AFTER
) (1422>).

If the after-release flag (AFTER) has been reset to "0" and the release operation has not yet started, then check the state of the release switch (SWZ) <1I42
4〉. If the release switch (sh, ) is closed, the process proceeds to <1450), and if the release switch (shz) is open, the state of the photometry switch (sh, ) is subsequently checked <11426>.

If the photometry switch (SW+) is closed (1145
0), and if the photometry switch (SW, ) is open, jump to the stop routine (STP>) (14
30).

On the other hand, if the release flag (AFTER) is set to ``l'' in <1422> and the release operation has been completed, then the flash mode flag (FLF) is checked <1432>. Flash mode flag (F
LF) is reset to “°0” (natural light mode), the flash charge request flag (CIIGR
After resetting the E port) to "On"<1I442>, jump to the stop routine (STP) (+1440>
.

Also, in (I432), the flash mode flag (FLF
) is set to “1°” (flash mode)
In this case, the flash charge request flag (CHGRE port) should be set to "1" (11434), and a subroutine (
? After calling FC1lGON) <11436>, check the charging start flag (GOFCHG) <I43
8). Charging start flag (GOFCHG) is u I 11
11 to jump to the stop routine <STP> when flash charging is started.
440>, if the charging start flag (GOPCIIG) has been reset to °゛0'° and charging is not to be started, proceed to (1424>), and as mentioned above, press the release switch (SW, ) or metering. If any of the switches (sw+) is closed, the process proceeds to <11450>, otherwise the process jumps to the stop routine (STP) (1430>).

<I450), the flash mode flag (FLF
). Flash mode flag (FLF)
is reset to "0" (natural light mode), immediately proceeds to <I460>, and if the flash mode flag (FLF) is set to "In" (flash mode), then flash charging starts. Signal (RDY
), please check I452>, flash charge signal (R
When DY) is set to "l" and is in the fully charged state, <
11460>.

(1460> is the unfilled lock flag (RDYLO(J
) to "0'°, and then check the release prohibition flag (RELDTS) <11462>. Even if the release prohibition flag (RELD IS) is set to 1" and the release is prohibited after the release operation is completed. If the release prohibition flag (RELDIS) is reset to uO++ and the release is permitted, then the lock flag (AFAEL) is checked (I464>).

If the lock flag (APAEL) is reset to "0" and the AF-AE is not locked, lens drive control for automatic focus adjustment including input of lens data from the lens internal circuit (900) is performed (1466). >, then after performing the photometry/distance measurement operation <11468>, it is determined whether the automatic focus adjustment operation is completed l1470>,
Until the automatic focus adjustment operation is completed (11466>~<1
470> is repeated. When the automatic focus adjustment operation is completed, the lock flag (AFAEL) is set to "1" indicating the locked state, and then <11472>, (I474>
Proceed to.

On the other hand, if the lock flag (AFAEL) is set to "1" in <s, i64> and the AF-AE lock state is already established, the process immediately proceeds to <11474>.

(11474> checks the state of the release switch (SWt). If the release switch (SWt) is open, return to (1410> and repeat the above operation until the release switch (S6) is closed. For example, the program jumps to a release routine (REL) for performing a release operation <11480>.

On the other hand, at (+1452>) the flash charge signal (RDY)
If it is reset to "0" and is in an uncompleted state, then the release prohibition flag (RELDIS) is set to "l" to inhibit the release operation (1482).
The attached flash device (7) is attached to the camera body (1)
<11484>
.

If the flash device (7) is a power supply sharing type, the flash charging request flag (CIIGREQ) should be set to the request state of "1486>, and the charging start flag (GOFCHG) should be set to "1486> to start flash charging. After setting <11488>, jump to the stop routine (STP) (11490>).

In addition, if the flash device (7) is not a shared power supply type in (1484>), it should be displayed that it is in an unfilled and idle state (1492), and an unfilled lock flag (RD
After setting YLO(J) to 1°° (1494>, <
1410> and repeat the above operation.

FIG. 10 shows a release routine (
REL) is a flowchart.

When entering this routine, it is first determined whether or not the mode is the self-timer mode (1502). If the mode is the self-timer mode, the process proceeds to a self-processing routine that activates the self-timer and delays the start of the release operation for a predetermined period of time (1502).
10>, the explanation of this routine will be omitted.

If it is not the self-timer mode (1502>, then a control signal is output to the LED drive circuit (560) and the buzzer (580) to stop the display and warning.<#52
0>, after raising the mirror using mirror control and narrowing down the aperture to a predetermined aperture using aperture control (1
522>, shutter speed control controls the operation of the front and rear curtains of the shutter to expose the film for a predetermined exposure time ($524>).

After that, the after-release flag (AFTER) should be set to "1"1526>, and the release prohibition flag (RELD) should be set to "1".
IS) is set to ``1 ++, which is a prohibited state.
11528>, increments the film counter in the display device (1530>, charges the shutter and winds the film by one frame (+1532)
>.

After that, it is necessary to determine whether the film has finished or not.
4> If the film has not ended, jump to the stop routine (STP). On the other hand, if the film has finished, the flash charge request flag (CHGREQ)
After resetting to “0” which is not in the request state <1542>
, a rewind control routine that rewinds the film into the cartridge (
Jump to REW (1550>).

FIG. 11 is a flowchart of a subroutine (PWRLIP) for switching the operation mode to (high speed clock mode).

When this subroutine is called, first the control signal (
PWC) to L” level and the DC-DC converter (1
40) is started (1602>, and after waiting for [5n+s] to stabilize the operation of the DC-DC converter (140) (11604>, the high-speed clock signal [8,3
8MHz] starts oscillation (11606>, waits [2ms] for the oscillation of the high-speed clock signal to stabilize, and then <!
1608>, switch the system clock (Φ, 6) to a high-speed clock signal <11610>. As a result, the operation mode is switched to (high-speed clock mode). It then returns to the original routine that was called.

FIG. 12 shows serial communication between the flash CPU (710) and the flash CPU (710).
) is a subroutine that receives flash data from RF
L) is a flowchart.

When this subroutine is called, the flash CP
Performs serial communication with U (710) and inputs various flash data <11702> The flash data input through this serial communication includes a signal indicating the model of the flash device (7) and whether or not the flash can be used. Signal (FLON), flash charge signal (RDY)
, pop-up status signal (INFOP), etc.

After that, check the status of the flash enable/disable signal (FLON) and flash charge signal (RDY).
4>, <1706>, release prohibition flag (R
Check the flash unit W (7) in auto mode and its light emitting part (7A).
is an operating state in which the flash unit (7B) protrudes from the flash body (7B) and is exposed, and furthermore, the main capacitor for light emission of the flash device (7) is in a fully charged state, and in addition, the release prohibition flag (RELDIS) is "0". ” and the release operation is permitted, the complete state is displayed in the [28Z] cycle (11710>, -, if at least one of the above conditions is missing). If it is, after clearing the display of the completion status (117)
20>, both return to the originally called routine.

FIG. 13 is a flowchart of a subroutine (?FC11GON>) for determining whether flash charging is possible.

When this subroutine is called, first, the state of the main switch (SWN) is determined (11802>).

If the main switch (SW, ) is open, after resetting the flash charge request flag (CHGREQ) to "O"<1830>, the process returns to the original called routine.

If the main switch (SW, ) is closed in <1802>, then the model of the flash device (7) is determined (1804). If the flash device (7) is not a shared power supply type, the flash charging request flag (CHGREQ
) is reset to "0"(1830>) and returns to the original routine that was called.

If the flash device (7) is the power sharing type in (1804>), the process proceeds to the power sharing type processing routine (SCFL) after (1810>).In this routine (SCFL), first, the flash availability signal (FLON) is Check the status ($1810>. If the flash availability signal (FLON) is reset to "0" and the flash device (7) is not available, reset the flash charging request flag (CHGREQ) to 0. After doing so (1830>), the routine returns to the original routine that was called.

If the flash enable/disable signal (FLON) is set to "1" in <1810> and the flash device (7) is in a usable state, then the flash charge signal (RDY
) (1812>).

If the flash charge signal (RDY) is reset to "0" and is in an uncompleted state, the flash charge request flag (CHGREQ) is set to "1'', which is the requested state, and then called (#820). Return to the original routine.

At <11812>, the flash charge signal (RDY) becomes “1”.
” and is fully charged, then check the status of the photometering switch (SW, ) (1822).
>. If the photometry switch (SW I) is closed, then the release prohibition flag (RELDIS) is checked <11824>. Release prohibition flag (RELDIS)
) is set to 1'' and release operation is prohibited, the buzzer (580) will then sound continuously to warn the photographer that the release lock state has transitioned from the incomplete release lock state to the fully released state. In order to
Repeat the loop up to.

If the photometry switch (SW+) is open at (11822>), the output of the drive signal to the buzzer (580) is stopped, and after the buzzer (580) stops sounding (+1828
>, and also (1824> sets the release prohibition flag (RE).
If LDIS) is reset to "0" and release operation is permitted, nothing is done, and the call is made after resetting the flash charge request flag (CHGREQ) to "0" (1830). Return to the original routine that was executed.

In FIG. 14, the flash device (7) is caused to perform a flash pop operation. It is a flowchart of a subroutine (POPFL).

When this subroutine is called, first the control Hi number (F
PWC) to the “L” level and the flash device (7)
Start supplying power to the control circuit (700) 1902>
After waiting [20m5] for the reset of the flash CPU (710) (11904>), it performs serial communication with the flash CPU (710) and receives the flash data from the flash CPU (710). calls the subroutine (RFL) that takes <
11906>. Thereafter, the model of the flash device (7) is determined based on the flash data obtained through serial communication (u90B>).

If the flash device (7) is not of the shared power type, the routine returns to the original called routine without doing anything.

If the flash device (7) is a shared power supply type, [2
ms] after waiting (+1910>, then check the main switch flag (SMF) 1+912>, only if the main switch flag (SMF) is set to l" and the main switch (SWX) is open. After resetting the main switch open/close signal (SMOFF) to "0" to perform flash pop-down <11914>, the pop operation enable/disable signal (POPEN) is reset to "OII"(11916>).

Next, serial communication is performed with the flash CPU (710), and the above-mentioned main switch open/close signal (
SMOFF) and the pop operation enable/disable signal (POPEN) are transmitted to the flash CPU (710) (191).
B>, both signals (SMOFF), CPOPE
Set N) to “1” <11920>, <19
22>.

After that, it waits for [2ms] and calls a subroutine (RFL) that performs serial communication with the flash CPU (710) to receive and receive flash data from the flash CPU (710) (1
926>, then the model of the flash device (7) is determined based on the flash data obtained through serial communication (11928>).

If the flash device (7) is not of the shared power type, the routine returns to the original called routine without doing anything.

If the flash device (7) is a shared power supply type, then check the status of the pop operation status signal (INFOP) (1930>.Pop operation status signal (INFOP)
is set to "1" and the flash pop operation is not in progress, the routine returns to the original called routine.

Also, if the pop operation status signal (INFOP) is reset to "0" and the flash pop is in operation, (
#924> and repeats the above-described operation.

FIG. 15 is a flowchart of a subroutine (?INIL) for determining the initial hoisting operation and its success or failure.

This subroutine is related to film loading, and when the back cover of the camera is closed, it automatically advances the film in advance and
This is for setting the frame.

When this subroutine is called, it first checks the status of the camera back switch (SWXc) (1t1502>), and if the camera back is open, resets the camera back flag (RCF) to "0" (11504). > , returns to the original routine that was called.

(If the camera back is closed in 11502>, check the camera back flag (RCF). If the camera back flag (RCF) is set to "1n," the camera back is closed since the last check. Since there is no change in the opened state, the process returns to the original routine that was called, and if the camera back flag (RCF) has been reset to "On," the camera back is closed from the open state. Therefore, the S lid flag (RCF) is set to "1"(11512>).

Next, the winding motor (391) is driven to start the initial film winding operation, and the film is advanced by a predetermined amount (for example, 4 frames) to prepare for shooting (11514>).

At this time, various methods have already been proposed regarding the initial winding technique, and although I will not discuss them in detail since they are different from the gist of the present invention, the setting position of a part of the film leader when closing the back cover of the camera, etc. In some cases, initial winding may fail. If a failure occurs, if you continue shooting without knowing this, it will be the same as not loading the film, so the following steps should be taken to avoid any serious problems in the unlikely event that the initial winding fails. This is the routine.

After the initial winding process is completed, it is determined whether the initial winding was successful (+11516>. If the initial winding was successful, the liquid crystal display circuit (510) displays the display window (15).
After displaying °°1” as the film counter (+1
1530>, returns to the original routine that was called. If the initial winding fails, a buzzer (
580) for one second <#1520>, <1152
2> Enter the following release lock processing routine.

(111522>), check the status of the back cover switch (SW, C), and if it is closed, then check the status of the photometry switch (SW +).
>, if the photometry switch (SWI) is in the closed state, the buzzer (580) sounds <111526>, and if the photometry switch (SWI) is in the open state, after the buzzer (580) stops sounding<11528) , (Return to #1522>.

That is, if the initial winding fails, the camera enters the release button state, and when the release button (11) is operated, the buzzer (580) sounds only during that time to give a warning to the photographer.

Then, at (11522>) the camera back switch (SW*
c) is released and the camera back is opened, the camera back flag (RCF) is reset to “0” and then <1.
11540>, returns to the original routine that was called. In other words, if the initial winding fails, the release lock will be applied until the camera back is opened.

FIG. 16 shows a subroutine (REW) for determining film rewinding.
CH) is a flowchart.

This subroutine includes processing for checking the rewinding state of the film and locking the release when rewinding is complete to prevent erroneous photography.

When this subroutine is called, first the rewind flag (REWF) is checked ($1602>).

If the rewind flag (REWF) is reset to 0'', it is a normal state and the routine returns to the original called routine without doing anything. Also, the rewind flag (REWF)
If it is set to "Il+", it means that rewinding has been completed, so the state of the photometry switch (sW, ) is checked <11610>.

If the photometry switch (SWI) is in the closed state, next check the state of the camera back switch (SWIl) (116).
20>, if the back cover switch (SW*c) is in the closed state, that is, if the back cover is closed, the buzzer (580
) and returns to (111622>, <11610>. If the photometry switch (SW + ) is open in (#1610>), the buzzer (580) stops sounding, then (11612> is called. Return to original routine.

Also, when it is detected in <11620> that the camera back switch (SW, c) is opened and the camera back is opened, the buzzer (580) stops sounding and the camera back flag (RCF) is set. After both the rewind flag (RHWP) and the rewind flag (RHWP) are reset to 0', <11632>, the routine returns to the original called routine.

That is, this subroutine is executed in the switch processing routine (SON) described above, that is, when the release button (1
This is called when 1) is pressed, so when the film rewind is completed, press the release button (11).
) until you stop operating it or open the back cover to take out the film (11610>→(+
11622>→<111610>, and the photographer can be clearly warned that rewinding is complete.

Figure 17 shows the battery capacity check subroutine (BAT
CHK) is a flowchart.

This subroutine is a battery check circuit (134).
This is to check the capacity of the power supply battery (130) by operating the power supply battery (130), and outputs the following three types of check results.

In other words, if there is enough capacity to charge the flash [BCV=2], or if there is insufficient capacity to charge the flash but the camera can operate without flash (natural light mode) [ BCV=1]
, and when the power battery (130) is exhausted and normal camera operation cannot be guaranteed even if the power source battery (130) is in natural light mode [B
CV/O].

The battery check circuit (134) supplies a dummy current to a dummy load only when performing a battery check, and calculates the battery voltage [V] as a value related to the amount of decrease in battery voltage at that time.
oo. ] is divided by a resistor and the reference value [Vref, , Vref is determined by measuring the value [V+].

(Vref+>Vrefz)], the value of [BCV] is determined.

When this subroutine (BATCHK) is called,
First, output a command to the battery check circuit (134) to flow a dummy current to the dummy load.
, wait for 2ms until the load condition stabilizes <11
704>, the value obtained by dividing the battery voltage [Vooo] [V+
Measure 1 n706> and output a command to stop the dummy current to the dummy load <111708>
.

Next, <11706> compares the measured value [v1] with the reference value [Vreftl<111710>, and as a result, if [Vl > Vref r ], the battery voltage drop is slight and the flash is charged. After determining that there is sufficient battery capacity for the battery and setting it to [BCV.2] <11712>, the process returns to the original routine that was called.

(11710>, if [V, <Vreftl, then the partial pressure value [V,] and the reference value [Vref z (Vref
, < Vref l) ] and <11172
0>, [V,>Vreftl, then [V
ref, >V, >Vreftl, and the battery capacity is insufficient to charge the flash, but it is determined that the camera can operate without using the flash (natural light mode), so it is set to [BCV・1]. (gt722)
, returns to the original routine that was called.

Furthermore, if (11720> is [V, <Vreftl), it is determined that the power battery (130) is exhausted and normal camera operation cannot be guaranteed, and after setting it to [BCV・0] (11
1730>, release prohibition flag (REL, 01S)
should be set to "1" indicating that the release is prohibited (
111734>, returns to the original routine that was called.

Next, the internal electric circuit of the flash device (7) will be further explained using FIG. 18.

As already explained, (700) is the control circuit, (710
) is a flash CPU (732) that controls charging for flash emission, controls flash emission, and performs serial communication with the body CPU (200).
) is the reset circuit, (730) is the boost/light-emitting circuit, (
701) to (707) are a group of contacts provided on the foot portion of the flash device (7).

In the booster/light emitting circuit (730), (740) is D
A C-DC converter boosts the voltage supplied from the camera body (1). (760) is the light emitting part (7A)
It is a xenon tube installed inside for flashlight emission.

(760) is a trigger circuit for causing the xenon tube (750) to emit light. (760) is a light emission control circuit, and the xenon tube (750)
) stops emitting light.

(780) is the main capacitor for flash emission (
This is a charging control circuit that controls charging to the main capacitor (782), and depending on whether the voltage applied to the main capacitor (7B2) is high or low relative to a predetermined voltage, the main capacitor (782) is turned on when the applied voltage is higher than a predetermined voltage. It has a neon tube (784) for monitoring charging voltage to charge the battery.

(790) is an up-down circuit for moving the light emitting unit (7A) mentioned above into and out of the flash body (7B), and is a motor (hereinafter referred to as pop motor) (
792) in forward and reverse directions to perform flash pop-up and flash pop-down (hereinafter collectively referred to as flash pop operation) via a drive mechanism to be described later.

(708) is the power supply terminal of the flash CP tJ (710). (709) is a reset terminal, and when a pulse signal of "L" level is input, the flash CPU (710
) is reset and started. (714) is the ground terminal of the flash CPU (710).

(711) is an output terminal (SO) for data to the camera CPU (200) when performing serial communication with the body CPU (200), and (712) is a data output terminal (SO) for the body CPU (200).
The data input terminal (S
I) and (713) are input terminals (SCK) to which a clock signal is input during serial communication.

(733) is the activation switch (
FS+), and its status signal is sent to the flash CPU (710
) is input to the input terminal (715). (734) is
- The up detection switch (FSt) is closed when the light emitting unit (7A) is in the protruding position, and its status signal is input to the input terminal (716) of the flash CPU (710). (735) is a down detection switch (FSs) that is closed when the light emitting unit (7A) is in the storage position, and its state signal is input to the input terminal (717) of the flash CPU (710). Each of the above switches (FS
l) to (FS:l) all have one end at ground potential,
The other end is pulled up inside the flash CPU (710).

(718) is an output terminal that outputs a control signal (OSC5TP) for voltage boost control to the voltage boost/light emitting circuit (730), and the control signal (OSC5TP) output from this output terminal (71B) is “°L”. The boost operation is stopped at this level. (719) is an output terminal that outputs a trigger signal (XETRIG) for causing the xenon tube (750) to emit light.

(720) is the X contact (SWx) on the camera body (1) side.
) is the input terminal to which the status signal (XON) is input. As mentioned above, the signal line (14) that is pulled up during the release operation changes to the L" level when the X contact (SWx) is closed. With this, the X contact (S
Wx) is detected.

(721) is an output terminal for an output signal (XEN) for pulling up the above-mentioned signal line (24) during the release operation. (722) and (723) are control signals (
This is an output terminal that outputs MOUTI) and (MOUT2).

(724) is a charge detection signal (
This charge detection signal (MON) is input to this input terminal.
MON) is at “L” level in the charging state, while
In the unfilled state, it is at "H" level.

(725) is an interrupt input terminal, and body CPU (20
0), the body CP
An interrupt is generated by inputting a clock signal from U (200).

Here, the above-mentioned flash pop operation is performed every time the camera body (1) side is operated, and the flash device (
7) Each of the above-mentioned switches (FS I ) to (FS3)
A summary of each condition is shown in Table 1 on the next page.

In addition, in the column of flash pop operation in the table, the down state refers to the retracted posture of the light emitting unit (7A) shown in FIG. The protruding posture of the light emitting part (7A) is shown.

Next, the drive mechanism (DM) for flash pop operation provided inside the flash device (7) will be explained.

As shown in Figure 20 (a) and (b), the light emitting part (7
A) is attached to the flash body (7B) so as to be rotatable around the axis (7x). A cam hole (7a) is formed in the side surface of the light emitting part (7A), and a drive member (11) that is rotatable around an axis (llx) is connected to one end of the cam hole (7a). The driven pin (lla) is fitted. A pinion gear (12) meshes with a gear portion (llb) formed around the periphery of this drive member (11). The pinion gear (12) has a compression coil spring (13
) to the same shaft center (12) as this pinion gear (12).
x), and this gear (14) is connected to the pop motor (16) of the up-down circuit (790) through a gear train (15) (in FIG. 792)) is interlocked and connected to the drive shaft (16a).

FIG. 20(a) shows the housed state in which the light emitting part (7A) is in the housed position, and from this state, the pop motor (16
) is rotated clockwise in the figure, the gear (14) is rotated counterclockwise via the gear train (15),
A pinion gear (12) connected to this gear (14) via a compression coil spring (13) also rotates counterclockwise.
As a result, the drive member (11) rotates clockwise and its drive pin (lla) is inserted into the cam hole (7a) of the light emitting part (7^).
) to the right in the figure, align the light emitting part (7A) with the axis center (7
x) Rotate clockwise around the flash body (7B
) is a flash pop-up.

FIG. 20 (0) shows a working state in which the light emitting part (7^) is in a protruding position as a result of the above-mentioned flash pop-up, and from this state, the pop motor (16) is driven and rotated counterclockwise in the figure. As a result, the gear (14) rotates clockwise via the gear train (15).
) via a compression coil spring (13) also rotates clockwise, causing the drive member (11) to rotate counterclockwise and its drive pin (l
la) moves inside the cam hole (7a) of the light emitting part (7A) to the left in the figure, and rotates the starting part (7A) counterclockwise around the axis (7X) to open the flash body (7B). ). This is the flash popdown.

The light emitting section (7A) is configured to be positioned by abutting against a stopper (not shown) in both the retracted position and the extended position. The pop motor (16) is driven continuously for a while after the light emitting part (7^) comes into contact with one of the stoppers, thereby ensuring that the light emitting part (7A) is in the protruding position or It is configured so that it can be placed in the storage position. At that time, since the compression spring (13) is interposed between the pinion gear (12) and the gear (14), slippage occurs between the pinion gear (12) and the gear (14). Pop motor (16) and gear train (15)
) etc. to prevent excessive force from being applied to the drive mechanism (DM).

In addition, the compression spring (13) is used to prevent the movement of the light emitting part (7A) from occurring during flash pop-up or flash pop-down due to some reason, such as being hit by the photographer's hand. (
12) and the gear (14), similarly prevents excessive force from being applied to the drive mechanism (DM) such as the pop motor (16) and the gear train (15).

Furthermore, by utilizing this configuration, when the pop motor (16) cannot be operated due to a decrease in the capacity of the power supply battery (130), the photographer can hold the light emitting part (7A) with his/her hand.
It is also possible to change the posture from the housed position to the protruding position, or from the protruding position to the housed position.

That is, the compression spring (13) causes slippage between the pinion gear (12) and the gear (14) when a torque sufficiently larger than the driving torque for normal flash pop operation is applied. The spring constant is as follows.

On the other hand, the drive member (11) has a pair of bosses (llc
) is provided in a protruding manner, and a switch piece (17) is crimped and fixed to the boss (llc). A switch board (18) having a pattern shape shown in FIG. 21 is disposed at a position facing the switch piece (17).

The switch piece (17) includes a pair of brushes (17a).
.

(17b). The first brush (17a) comes into sliding contact with the first pattern (18a) of the switch board (18) over the entire rotation range according to the rotation of the driving member (11). Further, the second brush (17b) is connected to the drive member (1).
According to the rotation of the switch board (18), one end of the rotation range corresponding to the accommodation posture of the light emitting part (78) comes into sliding contact with the second pattern (18b) of the switch board (18), and the light emitting part (
At the other end corresponding to the protruding position of the switch board (18
) into sliding contact with the third pattern (18c).

The second pattern (18b) and the third pattern (18c) of the switch board (18) each have a flash C
Input terminals (717), (71) of P U (710)
6), and the first pattern (18a) of the switch board (18) is grounded. The first pattern (18a) and the third pattern (18c) constitute an up detection switch (FS,) that detects that the light emitting part (7A) is in the protruding position.
8a) and the second pattern (18b) are the light emitting part (7A)
Down detection switch (
FSI).

Note that the second brush (17b) of the switch piece (17)
), the third pattern (18c) or the second pattern of the switch board (18) is released slightly before the light emitting part (7A) comes into contact with each stopper in its protruding or retracted position.
It is configured to be in sliding contact with the pattern (18b),
The flash CPU (710) operates the light emitting unit ( 7A) is configured to reliably shift to either posture.

FIG. 22 shows the bottom of this flash device (7), and the foot part (7C) is arranged as shown in the figure.
The aforementioned contact group (701) to (707) ((V,,
,).

(PGND), (FVIl+o+)+ (Fl)
, (F2), (F3), (DGND)). On the other hand, the hot shoe (IB) of the camera body (1) has a corresponding through contact group (101) to (107) ((VaI, e) in the arrangement shown in FIG. 2 (c).
, (PGND).

(FVDDI), (Fl), (F2), (F3)
, (DGND)).

Figure 2 (A) is attached to the hot shoe (IB) and Figure 2 (C) is attached to the hot shoe (IB).
The camera body (hereinafter referred to as the new camera body) (1) has contact groups (101) to (107) arranged as shown in FIG.
01) to (707) (hereinafter referred to as a new flash device) (7) is shown attached.

In addition, by interposing the first adapter (21), the new flash device (7) can be attached to the new camera body (1).
) (hereinafter referred to as the old flash device) (7') can be attached to the new camera body (1), and by installing the second adapter (22). The new flash device (7) can be attached to a conventional type camera body (hereinafter referred to as the old camera body) (1') other than the one shown in the previous figure.

Figure 23 shows the old flashing device (7°) attached to the new camera body (1), and Figure 24 shows
The new flash device (7) is shown attached to the old camera body (1). In addition, in Fig. 24,
The old camera body (1″) is equipped with a flash device (
Since the new flash device (7) is not configured to supply power to the flash device (7), the new flash device (7) is shown as having a dedicated power supply battery inside.

Figure 25 (a) or 25) shows the new camera body (1)
1st for attaching the old flash device F (7') to
An adapter (21) is shown, and FIGS. 26(a) to 26(b) show a second adapter (22) for attaching the new flash device (7) to the old camera body (1').

Please note that the old flash device (7') is attached to the new camera body (1).
), the control circuit and boost/light emitting circuit configuration of the old flash unit ff (7') now operates at the opposite voltage to that of the new camera body (1). Because there are some cases where
As shown in Figure 7, the contact point (F
A diode (21a) for preventing reverse pressure is interposed between the ground terminal (DGND) and the ground terminal (DGND).

Next, the operation of the flash CPU (710) is
This will be explained based on the flowcharts shown in FIGS. 8 to 32. Prior to explaining the operation, the status signals used in each flowchart will be summarized.

(POPB) is a pop operation flag for determining the status of flash pop operation; it is uO'' when stopped, “1” during flash pop-up, and “2” during flash pop-down. ” (POPOK)
is the pop stop detection flag, and the up detection switch (FS
X) or movement of the light emitting part (7A) after the down detection switch (FS, ) is closed (hereinafter, this movement is referred to as extra movement)
Inside, it is "1", and when the light emitting part (7A) is stopped moving, it is "O".

(FSI) is the status signal of the operating switch (FSI), which is "0" in the closed state and "1" in the open state, (
FS, ) is the up detection switch (FS) status signal,
(FS3) is the state signal of the down detection switch (FS3), which is “O” in the closed state.
”.

(FC), (CF), and (R[!L) are all interrupt flags for determining the type of interrupt when an interrupt occurs to the flash CPU (710).
) from the flash CPU (710) to the body CP
If an interrupt occurs due to a signal to U (200),
(CF) indicates a case where an interrupt occurs due to a signal from the body CPU (200) to the flash CPU (710), and (REL) indicates a case where an interrupt occurs due to a release signal.

The flash CPU (710) distinguishes between these separate interrupt flags (FC), (CF), and (REL) based on the difference in their duration. CF), (RE
The duration of L) is [FC<CP<REL].

(CTRI) is the first timer that controls the operating time of the flash pop operation, and its time-up time is [2,5s
] has been secerated. (CTR2) is the up detection switch (FSI) or down detection switch (FS,)
The second timer controls the travel time of the light emitting part (7A) after closing, that is, the extra travel time, and the time-up time is [
It is set at 10m5l.

FIG. 28 is a flowchart of the main routine that starts when power supply starts from the body CPU (200).

When this routine starts, first execute the reset routine (RESET) that performs initial settings.11002>
, then execute a loop routine (LOOP) that checks the switch input and charging status.11004>
, Furthermore, after executing the pop routine (POPCONT) that controls the flash pop operation (111006
>, return to <111004> and repeat the above operation.

During the execution of the loop routine (LOOP) and pop routine (POPCONT), the body CPU (2
An interrupt routine (INT) is executed by an interrupt generated by inputting a clock signal from 00 (1110).
10).

Figure 29 shows the reset routine (RES) that performs initial settings.
ET) is a flowchart.

When this routine is entered, it first disables various interrupts and <
11102>, reset the output port to return each output terminal to the initial state 111104>, output signal (O5
CSTP), (XETRIG), and (XEN) are all set to "L" level <11106>. Then R.A.
After clearing the contents of M 111108> and initializing each flash data (11110>), clear the pop operation enable/disable signal (POPEN) and the main switch open/close signal (11110>).
SMOFF) is set to the initial state of "1 + 1"<111112>, then each flag should be reset 111114>, the timer time-up time should be set to [250m5] 111116>, and after enabling interrupts ( 11118>, loop routine (
LOOP) <111120>.

FIG. 30 is a flowchart of a loop routine (LOOP) for checking switch input and charging status.

When entering this routine, first the pop operation flag (POP
Check B) <111202>. If the pop operation flag (POPB) is "0", that is, if the flash pop operation is not performed, then after inputting the status of the activation switch (FSI) and the up detection switch (FSz) (+11204> , those both switches (F
Please check the status of SI) and (FS2) +112
06>, if they are both closed, i.e.
The operation switch (FS, ) is on and the light emitting part (78)
is in the protruding position, a flash enable/disable signal (FLO) is sent to indicate that the flash device (7) is in operation.
After setting N) to "1'"<#1208>, 012
Proceed to 12).

On the other hand, the pop operation flag (POPB
) is not "0" and the flash pop is in operation, and <111206> is the activation switch (FSI).
When at least one of the and up detection switch (FSX) is open, the flash enable/disable signal (FSX) is activated to indicate that the flash device (7) is not activated.
After resetting (LON) to “0” (11210>, (
Proceed to +11212>.

(111212>, the main capacitor for light emission (7
82), and if it is fully charged, set the flash charge signal (RDY) to "1".
111214>, on the other hand, if it is in an unfilled state, after resetting the flash charge signal (RDY) to '0', <11
216>, both are pop routines (POPCONT
) Jump to <111220>.

FIG. 31 is a flowchart of the pop routine (POPCONT) that controls the flash pop operation.

When entering this routine, first the operation switch (FS, ), up detection switch (psz), and down detection switch (
FS3) <mt302>.

Next, check the pop stop detection flag (POPOK) (111304>.
OK) is set to "1'" and the light emitting part (7A) is running extra, then check whether the second timer (CTR2) has timed up.
If the second timer (CTR2) has not timed up, it means that the light emitting part (78) is still running, and after counting up the second timer (CTR2) (#
1312), jump to the loop routine (LOOP) 11390>, and if the second timer (CTR2) has timed up, proceed to <111350>.

On the other hand, the pop stop detection flag (PO
POK) is reset to “0” and the light emitting part (7A)
If it has stopped, then the main switch open/close signal (S
MOFF) <111320>, this main switch open/close signal (SMOFF) is set to "1" when the flash device (7) is activated, so normally the next step (111322> is skipped). hand(
This main switch open/close signal (S
The camera body (1
) side, the main switch (shx) is opened, “
The main switch open/close signal (SMO
FF) is transmitted, and in this case, in order to forcibly stop the operation of the flash device (7) in conjunction with the opening operation of the main switch (SW, ) of the camera body (1), After setting it to off (11322>, <
Proceed to #1324>.

(111324> checks the pop operation flag (POPB). If the pop operation flag (POPB) is not reset to "0", it indicates that the flash is pop-up or pop-down, and then Check whether the first timer (CTRI) has timed up <11330>.

If the first timer (CTRI) has not timed out, it indicates that the flash pop operation is in progress, and then the pop operation flag (POPB) is checked to detect the direction of the flash pop operation <111332>. (
111336>.

(111332>, the pop operation flag (POPB) is set to “
If it is set to 1, it indicates that the flash is popping up, and then the up detection switch (
FSz) is checked (11334>), and if the up detection switch (pst) is not closed yet,
Jump to loop routine (LOOP) 11390
), if the up detection switch (psz) is closed, proceed to (111340>. On the other hand, in <11336>, the pop operation flag (POPB) is set to 2°.

If it is set to FS, it indicates that flash popdown is in progress, and then the down detection switch (FS
3) Check the status <111338>, and if the down detection switch (FS3) is not closed yet, jump to the loop routine (LOOP) 11390
>, if the down detection switch (FS3) is closed, proceed to (111340>).

At <11340>, the first timer (CTRI) is reset, and then the pop stop flag (POPOK) is set to "1" indicating that the vehicle is running extra, and then at <11342>,
Jump to loop routine (LOOP) (113
90>.

On the other hand, the pop operation flag (POPB
) is reset to “0”, it indicates that the light emitting part (78) is stopped, and then the activation switch (
Check the status of the up detection switch (FSI), down detection switch (FS3) and <11132.
6>, <111328>, different processes are performed depending on the combination of states.

(111326>), the activation switch (FS,) is closed and the up detection switch (PSz) is open, that is, the activation switch (FSI) is closed and flash pop-up is completed. (1113) is not satisfied.
28>, the activation switch (FSI) is open and the down detection switch (FSz) is open, that is, the activation switch (FS, ) is open and flash pop-down is not completed. When the conditions are not met, that is, the activation switch (F
SI) is closed and the light emitting part (7A) is in the protruding position, and when the activation switch (FS + ) is open and the light emitting part (7A) is in the retracted position, the light emitting part (7A) is in the retracted position. 8) There is no need to change the posture of the light emitting part (7A).
In order to maintain the stationary state, the process proceeds to the stationary routine from (#1350> onward).

In addition, if the second timer (CTR2) times up at <11310>, that is, if the extra run is completed,
When the first timer (CTRI) times up at (11330>, that is, when the first stage of the flash pop operation is completed and only an extra run is left, this <
11350>.

(il1350> resets the second timer (CTR2), then resets the first timer (CTRI) (11352>, then the pop motor (792) should be stopped (, two motor control signals (MOUTI),
Set both MOUT2) to “H” level 111354
> Furthermore, the pop operation state signal (INFOP) transmitted to the body CPU (200) is set to "1" indicating that the flash pop is not in operation,
After setting both the two status signals (SMOFF) and (POPEN) to "l"(<111356), reset the pop operation flag (POPB) to "0" indicating the stopped state (+11358), and then start the loop routine. Jump to (LooP) (111390>.

On the other hand, if the conditions are met that the activation switch (FS,) is open at (+11328) and flash pop-down is not completed, then
In order to change the posture of A) to the accommodation posture, (111360
>Proceed to the subsequent flash pop-down routine.

<11360> sets the pop operation status signal (INPOP) to "0" to indicate that the flash pop is in operation.
After resetting the first timer (CTRI) <111362>, the pop operation enable/disable signal (P
OPEN) status <111364>. If the pop operation enable/disable signal (POPEN) is set to "l" and the flash pop operation is impossible, jump to the loop routine (LOOP) (+11390>
. Furthermore, if the pop operation enable/disable signal (POPEN) is reset to "0" and flash pop operation is possible, the first motor control signal (MOUTI) is at "H" level and the second motor control signal (MOUT2 ) should output a “L” level pop-down drive signal 11366>
, after setting the pop operation flag (POPB) to “2” indicating that the flash pop-down is in progress (at3
68>, jump to loop routine (LOOP)<#1390).

Furthermore, if the conditions are met that the activation switch (FS,) is closed at (+11326>) and the flash pop-up is not completed, then the light emitting unit (
In order to change the posture of (7A) to the protruding posture, (11137
0> Proceed to the subsequent flash pop-up.

<111370> sets the pop operation status signal (INFOP) to "0" to indicate that the flash pop is in operation.
” and then reset the first timer (CTRL) <!t1372>, the pop operation enable/disable signal (
Check the status of POPEN (111374>).

If the pop operation enable/disable signal (POPEN) is set to "1" and the flash pop operation is impossible, jump to the loop routine (LOOP) (11139).
0>. Also, the pop operation enable/disable signal (POPEN) is “°
0" and flash operation is possible, the first motor control signal (?l0UT1) is at the 'L' level and the second motor control signal (MOUT2) is at the 'H' level as the pop-up drive signal. Output 11376)
, after setting the pop operation flag (POPB) to "l" indicating that the flash is pop-up,
78>, jump to loop routine (LOOP) <111390>.

Figure 32 shows the body CP during execution of the loop routine (LOOP) and pop routine (POPCONT).
2 is a flowchart of an interrupt routine (INT) that is executed when an interrupt occurs due to input of a clock signal from U (200).

When this routine is entered, it first performs interrupt processing, disables interrupts, saves registers, etc. <11402),
Next, an interrupt flag is input (11404>.Then, the type of interrupt flag is determined based on the duration of the interrupt flag (i1410>).

<111420>, <11440>.

(111410> and if there is an interrupt flag (FC), the flash CPU (710) to the body CPU (
111412>, data is transmitted in synchronization with the clock signal, and the transmission is completed. Check <11416> and repeat data transmission until transmission is completed. Once the data transmission is complete, (1
11480>.

Also, if there is an interrupt flag (CF) at (11420>),
From body CPU (200) to flash CPU
This indicates the start of serial communication to (710), and since the signal line (42s) is shared, the output (SO) from the output terminal (711) on the flash CPU (710) side is set to “H”. ” level and set this output terminal (
After opening 711) (11422>, start accepting clock signals for serial communication. 11424>
, data is received in synchronization with the clock signal <11426>, and the data is stored in the RAM.
1428>, checks whether the reception is completed (#1430>, and continues from (11426) to (1) until the reception is completed.
1142B> is repeated. Once the data reception is complete,
<111480).

Furthermore, if there is an interrupt flag (REL) at (11440>, it indicates the start of the release operation, and then the flash enable/disable signal (FLON) should be checked (111442>) and the main capacitor (782) It is necessary to determine whether charging is completed 111444>, it is necessary to determine whether the flash is in a forced flash prohibition state due to a command from the body CPU (200) l11446>, and the flash enable/disable signal (FLON) is set to "1°". Only when the flash device (7) is usable and fully charged, and is not in a forced flash prohibition state,
(111450>Proceed to the subsequent light emission routine (FLASH), otherwise proceed to (111480).

When entering the light emission routine (FLASH), first the output signal (
After setting the timer time-up time to [250o+s], the X contact (sW, ) is closed. Check if it has been completed (111454>).

If the X contact (SWx) is not closed, then use the timer to check whether [250m5] has elapsed.
7, return to (111454> and wait for the X contact (SWx) to close until [250m5] has elapsed, and when [250m5]
Proceed to 80>.

If the X contact (SW, ) is closed at <11454>, then the light emission control signal (XETRIG) is set to the "H" level to start light emission at <111456>, [2,5 m
s] After waiting <111458>, the light emission control signal (X
ETRIG) is set to L" level to stop light emission (111460>. After that, wait until the X contact (SWX) is opened, that is, until the shutter charging is completed. If it is opened, the output signal (XEN) will be returned to “L” level.
1464>, after resetting the flash charge signal (RDY) to O" indicating the unfilled state (111466>, (
11480>.

<11480> performs the return processing from the interrupt, restores the registers and enables the interrupt, and then
Return to the original routine that caused the interrupt.

[Another example] Next, another example of the present invention will be listed.

<1> In the previous embodiment, a configuration was described in which the release lock state is indicated by an LED in addition to the sound of the buzzer (580), but in carrying out the present invention, the LED display is omitted. Good too.

<2> When the buzzer (580) is used for notification or alarm in different situations as in the previous embodiment, the sounding pattern of the buzzer (580) may be varied depending on the situation. . In addition, when using an LED display, etc., the sound pattern of the buzzer (580) should be the same in all situations, and the LED display etc. should be used to display a display according to each situation. 580) may be used only to prompt the photographer to look at the display.

<3> In the previous embodiment, the configuration in which the buzzer (580) was provided on the camera body (1) side was explained, but instead of that,
A buzzer (580) may be provided on the flash device (7) side.

<4> The present invention provides the camera body (
1) and a flash device (7) that can be attached to and removed from the camera body (1), as well as cameras that have a flash device fixed or removably incorporated into the camera body (1). can do.

〔Effect of the invention〕

As described above, in the camera according to the present invention, charging of the flash device is completed while the release button is being operated with the intention of starting the release operation, by the sound of the buzzer, which is easier to recognize than the display. This ensures that the photographer is aware that the release is in the locked state, even if the photographer is not able to start the release operation by operating the release button. However, since it can be easily determined that the problem is due to the release lock status, it is possible to avoid anxiety or take incorrect measures, and to continue shooting operations smoothly. can. Therefore, it has become possible to provide a camera that is advantageous in terms of handling as a whole.

[Brief explanation of the drawing]

The drawings show an embodiment of the camera according to the present invention, and FIG. 1 is an internal circuit diagram of the main parts, FIG. 2 (A) is an overall front view, and FIG.
0) is an overall side view, Figure 2 (C) is a top view of the camera body, Figure 3 is an internal circuit diagram, Figure 4 (A) is a time chart of the entire camera operation, and Figure 4 (B) is an important part. 5 to 17 are flowcharts showing the operation of the body CPU, FIG. 18 is an internal circuit diagram of the flash device, and FIG. 19 (A) is a perspective view of the flash device in the stored state. Figure (b) is a perspective view of the flash device in the operating state, Figure 20 (a) is a side view of the drive mechanism in the housed state, Figure 20 (El) is a side view of the drive mechanism in the operating state,
Fig. 21 is a front view of the switch board, Fig. 22 is a bottom view of the flash device, Figs. 23 and 24 are front views showing the connected state of the camera body and flash device, and Fig. 25 (a) is Top view of the first adapter, Figure 25 (
II) is a rear view of the first adapter, and Figure 25 (c) is a rear view of the first adapter.
The front view of the adapter, Figure 25 (d) is the left side view of the first adapter, Figure 25 (book) is the bottom view of the first adapter, the second
Figure 6 (a) is a top view of the second adapter, Figure 26 ([+)
is a rear view of the second adapter, FIG. 26(C) is a left side view of the second adapter, FIG. 26(D) is a bottom view of the second adapter, FIG. 27 is an internal circuit diagram of the first adapter, 28 to 32 are flowcharts showing the operation of the flash CPU. (1)...Camera body, (11)...
...Release button, (580) ...Buzzer,
(632)...Operation presence/absence determination means, (634
)...Release switch.

Claims (1)

[Claims] A release switch for starting the release operation that is activated by operating the release button on the camera body, a charging voltage determining means for determining whether the charging voltage for light emission of the flash device is high or low with respect to a predetermined voltage, and low voltage determination by the charging voltage determining means. A camera is provided with a release lock means for prohibiting the operation of the release switch when the release button is in an operation state, and an operation presence/absence determining means for determining whether or not the release button is operated, and a release lock means for disabling the operation of the release switch when the release button is in an operation state determined by the operation presence/absence determination means. A camera equipped with a control device that operates a buzzer when the release switch is prohibited from operating by a locking means.