JPH01302742A - Compound semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Summary] Element bones of compound semiconductor integrated circuits such as GaAs IC
Regarding the method for forming the 1f band, in a compound semiconductor integrated circuit having an active layer laminated on a semi-insulating semiconductor substrate with a buffer layer interposed therebetween, in order to eliminate side gate effects and leakage current to the substrate, an inert layer is provided between the semiconductor substrate and the buffer layer, and an element separation band for separating the semiconductor elements is made of a void, an inert material, or a mixture of a void and an inert material and is in contact with the inactive layer. It is characterized by

The manufacturing method includes a step of forming an inactive layer by implanting ions over the entire surface of a semi-insulating semiconductor substrate, followed by epitaxial growth of a buffer layer and an active layer, and then chemical etching of device isolation bands. The method is characterized in that it includes a step of forming up to the inactive layer by ion implantation or a mixture of chemical etching and ion implantation.

[Industrial application field]

The present invention relates to a method for manufacturing a compound semiconductor device.
The present invention relates to a method of forming element isolation bands for compound semiconductor integrated circuits such as ICs.

Recently, compound semiconductor ICs (integrated circuits) have been manufactured as ultra-high-speed devices, and element isolation is a particularly important issue for achieving high integration.

[Conventional technology]

Figures 4(a) and 4(b) show cross-sectional views of conventional HEMTICs (ICs consisting of high electron mobility transistor elements), and in both figures, symbol 1 is a semi-insulating GaAs substrate, 2 is a semi-insulating GaAs substrate, and 2 is a semi-insulating GaAs substrate. 1-Buffer layer made of GaAs layer (thickness 500
0), 3 is an electron supply layer made of an n-AlGaAs layer (thickness: 400), 4 is a contact layer made of an n-GaAs layer (thickness: 1000), 5 (partially)
is a two-dimensional electron layer (2DEG), 6 is a gate electrode, 7, 8
are the source and drain electrodes, TI, T2゜T3
indicates a HEMT element.

In addition, FIG. 4(a) shows an example in which a gap-like element isolation band 9 reaching the buffer layer 2 is provided, and one of the elements shown in FIG. This is an example in which the element isolation zone 9 in the form of a void is formed by selective chemical etching using lithography technology to create a void, and the element isolation zone 10 made of an inert material is formed using a resist film. Cover the mask with oxygen ions (0+)
This is a separation method in which the material is inactivated (insulated) by injecting it.

[Problem to be solved by the invention]

However, since the device isolation bands 9 and 10 that reach the buffer layer 2 shown in FIGS. However, there is a problem in that the device characteristics are unstable due to the side gate effect.The side gate effect is a phenomenon that occurs in an IC consisting of an element having an n-type active layer, for example, as shown in FIG. When the element T2 shown in al is operating by applying a voltage of QV to the source, the adjacent element T1 has a voltage of -3V applied to the source or drain.
If a voltage of -3V is applied, or a gate voltage of -3V is applied, a phenomenon occurs in which the threshold voltage vth of the element T2 changes.

That is, when the adjacent element T1 operates at a lower voltage than T2, the vth of the element T2 changes, which is a major quality defect. Note that this side gate effect is largely related to the depth and width of the device isolation band, and its cause is thought to be at the interface between the semi-insulating GaAs substrate and the buffer layer (IEEE Electron De
vice Letters Vol, EDL-8No,
6 p. 280 (1987)).

Further, when a high electric field is applied to a semi-insulating compound semiconductor substrate, for example, when a potential of several volts is applied at intervals of several cranes, leakage current occurs and various problems occur. In this way, I.C.
When constructing a semi-insulating substrate, there are different problems than insulating substrates.

The present invention proposes a compound semiconductor device and a manufacturing method thereof, which aim to alleviate such problems and eliminate side gate effects, leakage current related to semi-insulating substrates, and the like.

[Means to solve the problem]

The problem is that, as shown in the principle diagram shown in FIG. An inactive layer 20 is provided between the buffer layer 13 and the semiconductor elements Tl, T2 . T3
The device isolation band 19 separating the elements is solved by a compound semiconductor device that is in contact with the inactive layer 20 by a void, an inert material, or a combination of a void and an inactive material.

In addition, the manufacturing method includes a step of forming an inactive layer by implanting ions into the entire surface of a semi-insulating semiconductor substrate, and then epitaxially growing a buffer layer and an active layer, and then chemically etching an element isolation band, or The present invention is characterized in that it includes a step of forming up to the inactive layer by ion implantation or a mixture of chemical etching and ion implantation. The structure is such that the sides are separated by a gap and an inert material to completely electrically isolate the entire periphery of the semiconductor element. By doing so, it is possible to block the side gate effect and leakage current when a high electric field is applied, which are conventional problems.

〔Example〕

Hereinafter, embodiments will be described in detail with reference to the drawings.

FIG. 2 shows a cross-sectional view of an embodiment according to the present invention,
Tl, T2. T3 is a HEMT element, 30 is an inactive layer, 2
Reference numeral 9 denotes an element isolation band having a void in the upper part and an inert material in the lower part, and the other symbols are the same parts as in FIG. 4 and are given the same symbols. Among these HEMT elements, T2 has a source applied voltage of OV, and this source voltage is the lowest voltage applied to element T2. Further, the same voltage as T2 is also applied to element T3. On the other hand, a source voltage of 13cm is applied to element T1, and therefore, due to the side gate effect, element T2. Since vth of T3 changes, in order to suppress this change, a structure is used in which the periphery of all elements is electrically isolated. With this configuration, leakage current from the semi-insulating GaAs substrate can also be blocked. In the embodiment shown in FIG. 2, the element isolation strip 29 has a structure in which the upper part is a void and the lower part is an inert material, but the entire element isolation strip 29 may be composed of a void or an inert material.

Next, FIGS. 3(a) to 3(el) show step-by-step cross-sectional views of the manufacturing method of the embodiment shown in FIG. 1 is a cross-sectional view of an insulating GaAs substrate 1, which is a semi-insulating substrate doped with Cr (chromium).Therefore, there is a risk that leakage current will occur when a high electric field is applied to the substrate.

FIG. 3 (see bl; this semi-insulating GaAs substrate 1.
Oxygen ions (O+) are implanted onto (Cr-doped) to form an inactive layer 30 (film thickness of about 1000 nm).Ion implantation conditions are acceleration voltage 40 to 60 KeV, dose amount 10
/cJ.

FIG. 3 (see C1; then, 1-
Buffer layer 2 made of GaA5ji (non-doped)
(thickness: 5000 layers), electron supply layer 3 consisting of n-AlGaAs layer (thickness: 400 layers), n-GaAs
A contact layer 4 (film thickness: 1,000 layers) is sequentially grown epitaxially by MOCVD, MBE, or the like.

Refer to FIG. 3(d); Next, using lithography technology, the upper surface is covered with a resist film mask 31, and the exposed element isolation zone region is chemically etched to a depth of about 3000 mm.
A groove-shaped void 32 is formed. As the etching agent, a diluted mixed solution of hydrofluoric acid and hydrogen peroxide is used.

See FIG. 3(e); then, the resist film mask 31
Oxygen ions are injected into the exposed groove-shaped void 32 while leaving the inactive layer 30 to form an inert body 33 at the bottom thereof and connect it to the inactive layer 30. Ion implantation is performed at an acceleration voltage of 100~2
This is carried out under the conditions of 00 KeV and a dose of about 1012/crA.

Thereafter, the resist film mask 31 is removed, and gate electrodes and source/drain electrodes are formed by a known manufacturing method to complete the process. The device isolation band 29 in which the upper part is a void and the lower part is an inert body as in this embodiment has the advantage that its width can be formed relatively narrow.

The structure according to the present invention as described above can eliminate the side gate effect of a compound semiconductor IC and leakage current when a high electric field is applied, and can stabilize device characteristics.

Note that the above explanation uses an IC made of a HEMT element as an example, but it can also be applied to an IC made of other compound semiconductor elements such as a MESFET (metal semiconductor field effect transistor) element.
Needless to say, it can also be applied to

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a compound semiconductor rc with stable characteristics can be obtained, contributing to the development of ultrahigh-speed ICs.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram, Fig. 2 is a sectional view of an embodiment according to the present invention, and Fig. 3 (a)
〜tel is a step-by-step sectional view of the manufacturing method of the example, FIG. 4 (
al. (b) is a cross-sectional view of a conventional HEMTIC. In the figure, ① is a semi-insulating GaAs substrate, 2 is a buffer layer made of an i-GaAs layer, and 3 is an n-GaAs substrate.
Electron supply layer made of AIGaAs layer, 4 is n-GaAs
5 is a two-dimensional electron JW (2D
EG), 6 is a gate electrode, 7.8 is a source electrode and a drain electrode, TI, T2.
T3 is a HEMT element or a semiconductor element, 9, 10, 19, and 29 are element isolation bands, 11 is a semiconductor substrate, 12 is a buffer layer, 13 is an active layer, 20 and 30 are inactive layers, 31 is a resist film mask , 32 indicates a void, and 33 indicates an inert body. 1st Figure JJEf H,, yh > 6taPse 4 and 4 Kuritai)
2 to tn2 figure edge] 卜's t-IEMTIc/)'
1℃ ■

Claims (2)

[Claims] (1) In a compound semiconductor integrated circuit having an active layer stacked on a semi-insulating semiconductor substrate via a buffer layer, an inactive layer is provided between the semi-insulating semiconductor substrate and the buffer layer, and a semiconductor element 1. A compound semiconductor device characterized in that an element isolation band that separates the layers is made of a void, an inert material, or a mixture of a void and an inactive material, and is in contact with the inactive layer. (2) After forming an inactive layer by ion implantation on the entire surface of the semi-insulating semiconductor substrate, a step of epitaxially growing a buffer layer and an active layer, and then chemical etching or ion implantation of device isolation bands, or A method for manufacturing a compound semiconductor device, comprising the step of forming up to the inactive layer by a mixture of chemical etching and ion implantation.