JPH01303534A - Resetting system for runaway of bus master unit - Google Patents

Abstract

PURPOSE:To prevent the repetitive resetting actions due to an everlasting fault by producing automatically an internal reset signal in case the CPU runaway of a bus master is detected by a watchdog timer to start a resetting action of the bus master and also to perform the self-diagnosis of the hardware for detection of the fault. CONSTITUTION:A watchdog timer 17 is periodically triggered by the output pulse of a CPU 11 and produces an abnormality detecting signal in case the triggering is not applied from the CPU 11 for a fixed time to inform the occurrence of the abnormality to a reset signal generator 18 and the CPU 11. The generator 18 detects the abnormality detecting signal received from the timer 17 or a system bus and produces the internal reset signal of a bus master unit to supply this signal to a system bus interface circuit 15, a CPU 11 and a peripheral circuit respectively. Thus the repetitive resetting actions due to the hardware troubles can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multiprocessor system having a plurality of bus masters, and particularly to a method for recovering and restarting processing when one of the bus masters goes out of control.

Conventional technology Conventionally, in order to detect a CPU runaway using a watchdog timer, the watchdog timer is programmed to continue to be triggered periodically during normal operation using methods such as real-time interrupts. When there is no trigger from the CPU for the dog timer,
The watchdog timer generates an abnormality detection signal as if some kind of failure has occurred in the CPU and caused it to run out of control.
Generally, the processing of the processing system under the control of the PU is stopped, initialized, and re-executed.

Problems to be Solved by the Invention As mentioned above, when the bus master unit of a multiprocessor processing system is configured in such a way that processing is stopped or initialized and re-executed based on the abnormality detection signal of the watchdog timer, Considering the ripple effect on other connected processing systems, stopping the operation of the processing system should be avoided as much as possible.

It is not a good idea to immediately stop processing when the process goes out of control.

However, if you use the instant execution method, if the cause of the failure is not temporary but a permanent cause such as a hardware failure, processing will be restarted without removing the failure. However, there is a high probability that the abnormal state will occur again, and in that case, the recovery operation will be repeated, which is likely to have an adverse effect on the operation of the system.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a new recovery method when a bus master unit runs out of control, which makes it possible to eliminate the above-mentioned drawbacks inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above-mentioned objects, the present invention provides a method for recovering from an abnormality in the bus master unit by configuring a multiprocessor processing system in which a plurality of processing systems use a single system bus. The bus master unit includes a CPU, a memory circuit, a system bus interface circuit, and the above C.
It has a reset signal generator for generating a reset pulse by sensing an abnormality detection signal from a watchdog timer for detecting runaway of the PU, and the reset signal generator generates a reset pulse by sensing an abnormality detection signal generated by the watchdog timer. When this occurs to the CPU, the CPU monitors the abnormality detection signal of the watchdog timer, and in the case of a restart caused by the watchdog timer output, the CPU executes a self-diagnosis program before enabling the system bus interface circuit. The system is characterized in that it investigates whether there is a hardware failure or not, and restarts processing only when no abnormality is detected, and enables the system bus interface circuit.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Referring to Figure 1, CPIII is connected to ROO20RA old 3, I10 boat 14 via an internal bus,
The internal bus is connected to the system bus through system bus interface circuit 15. Real-time interrupt generator 1
The output signal of 6 is connected to the interrupt input of cputt,
- Interrupt the CPU 11 at fixed time intervals and start the interrupt service program. The watchdog timer 17 is periodically triggered by the output pulse of the CPUII, and when the trigger from the cputt is not performed for a certain period of time, it generates an abnormality detection signal and sends it to the reset signal generator 18 and CI'U11. Notify of abnormality. The reset signal generator 18 detects the abnormality detection signal from the watchdog timer 17 or the abnormality detection signal from the system bus, generates an internal reset signal for the bus master unit, and generates an internal reset signal for the system bus interface circuit 15, C.
Supplies PUII and peripheral circuits.

In a steady state, an interrupt service program is activated by the real-time interrupt generator 16 at regular time intervals, and the CPU II supplies a trigger pulse to the watchdog timer 17 in connection with this interrupt. If you count with a counter, evaluate the counter value outside of the real-time interrupt service, and embed a routine in the normal processing routine that generates a trigger pulse to the watchdog timer 17 when it exceeds a certain value, If the CPU II goes out of control due to a failure such as a memory read/write error or a bus short, a trigger pulse cannot be generated, and the watchdog timer 17 generates an abnormality detection signal.

This abnormality detection signal is detected by the reset signal generator 18, an internal reset signal of the bus master unit is generated, and the bus master unit is initialized. The reset signal generator 18 also has the function of generating an internal reset signal in response to the system reset signal from the system bus, but the restart in the event of an error is different from this when the CPU II generates the watchdog timer 17. If the abnormality detection signal is latched, a self-diagnosis program will be automatically executed at the time of start of Sera 1 to perform hardware tests such as memory test and I10 board test, and at least it can be detected by self-diagnosis. If no range failure is recognized, the watchdog timer 17 is initialized, the system bus interface circuit 15 is enabled, and processing is restarted.

During this series of processing, in order to minimize the impact on the system bus, the system bus interface circuit 15 is disconnected from the system bus (disabled state) by an internal reset signal, and self-diagnosis and initialization are executed normally. , the circuit configuration should be such that it is enabled only when processing is restarted.

If a fault is found in the self-diagnosis program during lister 1~, an alarm is output to the outside by a method such as lighting a lamp or outputting a message to immediately notify the occurrence of the fault, and the system bus interface circuit 15 is disabled. Retain state. This facilitates early detection of failures and isolation of faulty parts, contributing to improved system maintenance performance.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the CP of the hess master
When U runaway is detected by the watchdog timer, an internal reset signal is automatically generated, and at the same time the recovery is started, hardware self-diagnosis is executed, and a failure is detected, making it possible to repeat the recovery operation due to a permanent failure. It prevents occurrences, outputs alarms and contributes to early detection of failure locations, and enables automatic recovery from temporary failures caused by noise, etc., which improves system maintainability. is obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

Claims (1)

[Claims] a CPU for configuring a multiprocessor processing system in which multiple processing systems use a single system bus;
A memory circuit, a system bus interface circuit, a watchdog timer for detecting runaway of the CPU, and a reset signal for sensing a reset signal from the system bus and an abnormality detection signal generated by the watchdog timer to generate a reset pulse. In a bus master unit having a generator, when the reset signal generator generates a reset pulse to the CPU in response to the abnormality detection signal generated by the watchdog timer, the CPU monitors the abnormality detection signal of the watchdog timer and outputs the watchdog timer. In the case of a restart caused by a system bus interface circuit, before enabling the system bus interface circuit, check for a hardware failure according to a self-diagnosis program, and only if no abnormality is detected, restart processing and enable the system bus interface circuit. A method for recovering when a bus master unit runs out of control.