JPH01306932A - Method for testing data processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a testing method for a data processing device, and in particular, for a pre-control function consisting of a plurality of streams, by also executing a test instruction on the side of an unsuccessful branch. , relates to a testing method for data processing equipment that allows the maximum performance to be demonstrated under all environments.

[Conventional technology]

The processing speed of data processing devices is becoming increasingly faster due to specification requirements. As one element for achieving this increase in processing speed, there has been a shift from advance control of a single stream to advance control of multiple streams, and the number of streams is likely to increase in the future. Here, a single stream is a program routine without branch instructions,
When branching to two instructions, there are two streams of program routines, and when branching to three instructions, there are three streams of program routines.

For example, "
In "Pipeline Mechanism Test Method", we conduct a preliminary control function test with multiple streams. Now, if a conditional branch instruction is selected when generating a test instruction, and it is certain that the conditional branch instruction will cause a branch, the branch failure side is an invalid instruction that will not be executed. I haven't. Therefore, in the above method, an exception generation instruction, etc. is set on the branch failure side, and when the advance control function malfunctions and the branch does not follow the conditions,
Malfunctions were detected by causing an exception to occur.

[Problem to be solved by the invention]

As described above, in the conventional method, when a branch instruction, especially a conditional branch instruction, is selected when generating a test instruction for performing an operation test in an operation test of a preceding control function having multiple i-streams, An invalid instruction, such as an exception generation instruction, is provided on the side that would not be executed if the branch operation is normal. As a result, until the branch is finalized, the preceding operation of the implicitly executed branch failure side stream is interrupted due to exception detection, and the operation test is performed with the load on the preceding control function reduced. Therefore, an effective advance control function test cannot be performed. In this way, if an instruction is set to interrupt processing on the side where the branch fails, it does not mean that the test has been conducted under all environments including the case where the branch fails. Therefore, in order to conduct an effective advance control test, it is necessary to demonstrate the maximum capacity under all environments.

The purpose of the present invention is to solve such conventional problems, and to perform an advance control test with advance control working on all of the multiple streams when performing an operation test of a advance control function having multiple streams. The object of the present invention is to provide a data processing device testing method that allows for the following.

[Means to solve the problem]

In order to achieve the above object, a data processing device testing method according to the present invention generates a test instruction using random number data as input, calculates the expected value of the execution result of the test instruction by simulation, and streams the above test instruction in multiple streams. In a test method for a data processing device in which a pre-controlled data processing device under test with After generating an instruction to set, a process is performed to increase the frequency of generation of a branch instruction as an instruction following the instruction, and significant test instructions are generated for both the branch success side and the branch failure side of the branch instruction. , is characterized by allowing advance control to work for multiple streams.

[For production]

In the present invention, if the test instruction generated by inputting random number data is an instruction that sets a condition code, the frequency of generation of a branch instruction, particularly a conditional branch instruction, as a subsequent instruction is increased. In other words, by using the information in the instruction parameter table, a branch instruction is generated preferentially, conditions are established for preemptive control to work on multiple streams, and if a condition code has determined that a branch will occur, preemptive control is applied to multiple streams. In order to generate an instruction sequence that works, the original test instruction generation is continued for the stream on the branch success side, and the instruction that will not be executed within the range where the preemption control is activated, that is, the instruction that implicitly performs preemption, is added to the branch failure stream. generate.

In this way, the present invention uses random number data and information in the instruction parameter table to generate a conditional branch instruction with priority as a subsequent instruction of the instruction that sets the condition code, and also to confirm the branch using the condition code. If the branch fails, a test instruction is also generated on the side where the branch fails, thereby creating a state in which multiple streams work. By testing these, the hardware of the data processing device can determine the decoding storage operation, association operation, and
In order to perform cancellation processing such as load operations and execution operations, tests that combine the advance control function, the status of various buffer memories and registers inside the hardware, and the operation of each stage of advance calculation are performed. This can be done in an environment that allows you to reach your maximum potential.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a data processing device that performs a test showing one embodiment of the present invention.

In FIG. 1, 1 is a data processing device that executes a test;
Reference numeral 2 denotes a preceding control function unit that performs pipeline control of the data processing device, etc.; 3 an address translation mechanism unit that converts a logical address into a real address; and 4, a part of the copy of the main memory is stored. , a buffer memory to which writing and reading are performed with high-speed access; 5 is various registers; 6 is a main memory; 7 is a random number program stored in the main memory 6;
8 is an external storage device storing a test program library.

As shown in FIG. 1, in the test method of the present invention, a data processing device 1 executes the test. This data processing device 1
It is composed of a advance control function section 2, an address conversion section 3, a buffer memory 4 inside the hardware, a register 5, and a main storage device 6.

The test method of the present invention uses the data processing device 1 as a test object, loads a random number program 7 from a test program library in an external storage device 8 into the main storage device 6, and generates a test instruction sequence using the random number program 7. This is to test the advance control function section 2.

FIGS. 2(a) and 2(b) are explanatory diagrams in the case of executing an instruction of a advance control function having a plurality of streams.

As shown in FIG. 2(a), the advance control function unit 2 performs instruction decoding D and address conversion A for the generated test instruction sequence 9.
, in the order of operand data reading OF, execution E,
Each stage is operated according to the machine cycle 1o, and each instruction of the generated test instruction sequence is sequentially processed. A conditional branch instruction ■ is provided next to the condition code setting instruction ■, and if the branch is successful, a branch is made to the instruction [phase].
As shown in b), the instructions following instruction (2) are normally not executed as indicated by diagonal lines.

FIG. 3 is an overall operation flowchart of a test method showing one embodiment of the present invention.

In the present invention, the advance control function section 2 is tested by processing the test instruction sequence generated by the random number program 7 as described above.

(i) A random number is generated by the random number program 7, and a test command is generated using this random number as input (step 13.
14).

The main storage device 6 stores a test instruction generation information table and an instruction parameter table.

FIG. 11 is an explanatory diagram of the contents of the test instruction generation information table, FIG. 6 is a diagram showing the detailed contents of the instruction information in the table in FIG. 11, and FIG.
FIG. 6 is an explanatory diagram of the contents of an instruction parameter table stored in No. 6;

(...) Reads the test instruction generation information table 40 (see FIG. 11) provided in the main storage device 6, checks the type format from the instruction information 400 of the generated test instruction, and generates a plurality of test instructions in multiple streams. In order to effectively test the advance control function with
(See Figure 5) to make adjustments by re-creating or adding test instructions. Then, corresponding to the generated test instruction, the test instruction generation information table 4o
information regarding the generated test command is stored in (steps 15 to 18). As shown in FIG. 6, the instruction information 400 in the test instruction generation information table 4o shown in FIG. 11 stores an instruction format 70, OPI information 72, and OP2 information 74.

(ni) Next, the expected value for the execution result of the test instruction is obtained by simulating it (step 19). The simulation is performed independently for each test instruction so as not to be affected by advance control, and the test instructions and data existing in the buffer memory 3 in the hardware are flushed out in response to the execution of the generated test instruction. and clear buffer memory 3.

(iy) Check whether the expected value obtained by the above-mentioned simulation and the result value obtained by executing the generated test command match, and if they do not match, output an error message (steps 20 and 21). ).

(v) If the expected value and the result value match in step 20, and if an error message is output in step 21, check whether the same test instruction has been executed n times in a row. Check (step 22).

(vi) If the number of executions of the test instruction has not reached n times, the process returns to step 19 and the same instruction is executed. At this time, the instructions and data from the previous test instruction execution remain in the buffer memory 3, so the execution of the test instruction this time will result in a difference from the first execution. The advance control function unit 2 is tested with respect to the states of the buffer memory 4 and registers 5 in the hardware, and the state of advance operations in a plurality of streams under different environmental conditions (steps 19, 20, 21).

(Information) In step 22, if the same test command has been executed n times, it is checked whether the test command has been executed a predetermined number of times to completely test all functions of the advance control function section 2. (Step 23).

If the predetermined number of times has not been reached, the entire flow described above is repeated, and if the predetermined number of times has been reached, the series of test commands by the random number program 7 is terminated.

FIG. 4 is a detailed operational flowchart of test instruction generation in FIG. 3.

In the test instruction execution process of FIG.
In step 17, test commands are generated to effectively test the advance control function having multiple streams, and the details thereof will be described in detail with reference to FIG. Note that it is not necessary to re-create or additionally create a test command each time a test command is generated in order to effectively test a preceding control function that has multiple streams.In the example shown in Figure 4, the preceding test command is a condition code. Executed only if the instruction sets .

FIG. 7 is a diagram showing an example of instruction format information in the instruction parameter table shown in FIG. 6.

(b) In the flow shown in FIG. 3, when a test instruction is generated, it is checked whether it is in the branch instruction creation mode or not (step 24), and if it is not in the creation mode, the
Information such as the type and format of the preceding test command is extracted from the test command generation information cheaple 40 shown in the figure (step 2).
5) Check whether the preceding instruction is an instruction to set a condition code (step 26). This check is performed using the information of the condition code setting flag 701 shown in FIG. It shows. If the preceding test instruction is not an instruction for setting a condition code, the process moves to step 18 in FIG.

(b) If the preceding test instruction in step 26 is an instruction to set a condition code, check whether the number of consecutive tests in the entire flow shown in FIG. 3 is a multiple of m. ), if the number of tests is not a multiple of m, the process moves to step 18 of the flow in FIG. Step 27
Processing is when the preceding instruction is a test instruction that sets a conditional code.

This process is to prevent all subsequent test instructions from becoming branch instructions, and in the example shown in Figure 4, proceeding to the next process is permitted only when the number of executions of the test instruction is a multiple of m. are doing.

(c) In step 27, if the number of test executions is a multiple of m, set the branch instruction creation mode, and use the information of the branch instruction 702 in FIG. 7 in the instruction parameter table 50 in FIG. Read the pointer of the defined branch instruction parameter group 500 in FIG. 5 (step 28
).

(d) If the mode is branch instruction creation mode in step 24, and if the process in step 28 (c) is completed, use random number data to branch from the branch instruction parameter group 500 in FIG. An instruction, especially a conditional branch instruction, is selected as a test instruction (step 29), and whether or not the test instruction is a successful branch instruction is checked based on the information of the successful branch instruction 703 in FIG. 7 (step 30).
). If the test instruction is not a successful branch instruction, the branch instruction creation mode is reset and the process moves to step 18 of the flowchart in FIG. 3 (step 31).

(E) In step 30, if the test instruction is a successful branch instruction, the test instruction on the unsuccessful branch side is selected from the random number data and the branch unsuccessful side instruction parameter table in order to generate a test instruction that works with multiple streams. (step 32).

FIG. 10 is an explanatory diagram showing a method of creating a subsequent instruction on the branch failure side of a branch instruction according to the present invention, and FIG. 9 is a table showing the numbers of general-purpose registers that are effective as pace registers during test instruction generation. FIG. 8 is a diagram showing an example of ○P1 information in the instruction parameter table of FIG. 6.

In FIG. 10, 36 is a register, 6 is a main memory,
37 is a register in which the pace register number is stored, 50
is the instruction parameter table.

First, the random number data in the register 36 is set in the instruction storage location 38 at the address on the branch failure side, and further, using the random number data as input, the instruction parameters to be set on the branch failure side are set from the instruction parameter table 50 shown in FIG. Select the instruction format 70 in the instruction parameter table 50, ○
A branch failure test instruction is generated using the P1 information 72 and the P2 information 74 as control information. To do this, first, a control command 70 in the command format 70 shown in FIG.
If the information in 4 is referenced and the flag is '1', the selected instruction is a control instruction, so the random number data is set again without generating the instruction, and the instruction parameters are selected. , this process is repeated until an instruction parameter whose control flag 704 information is IO+ is selected.

When an instruction parameter whose control instruction flag 704 is IO+ is selected, the selected instruction parameter table 5
The instruction code 71 from 0 to the instruction storage location 38 in FIG.
, and further refers to the OPI information 72 and OP2 information 74. For example, if the operand of the selected instruction is a memory type, the register set 726 of the operand information 72 shown in FIG. 8 is set to 10'. In order to prevent an exception from occurring in the operand, the information of the effective pace register 80 in FIG. =15- Set to position 38. As a result, a meaningful test instruction was generated for the preceding operation. Note that the instruction generation method for preventing the occurrence of this exception is based on the instruction parameter table 50 in FIG.
This is achieved by coded rules stored in advance. That is, the information in the instruction parameter table 50 is a collection of rules that are coded instructions from the instruction specifications described in the specifications.

Here, if the above-described operation is not performed, the preceding operation will be interrupted on the branch failure side, so that the effects of the present invention cannot be expected. That is, when generating an instruction on the side of an unsuccessful branch, if an instruction is generated in which the control instruction 704 of the instruction format 70 of the instruction parameter table 50 is '1', the control instruction is an instruction controlled by the system,
For example, in an instruction to switch between 24 bits and 31 bits,
At the time when the control instruction is decoded, the subsequent preceding calculation is stopped. This is based on the fact that it is not possible to perform look-ahead operations since the state of the system is not determined until the execution of the control instructions is complete. Therefore,
The control instruction is excluded from generation because it is not an instruction that is not pre-operated and therefore is not valid as an instruction on the side of an unsuccessful branch.

In this way, after the branch failure instruction is generated, the next random number data is set (step 33).

(F) On the unsuccessful branch side, when executing a branch instruction, check whether the maximum number of instructions to be pre-computed has been selected (step 34), and if the specified number has not been reached, perform the processing from step 32 onwards. Repeat, if the specified number is reached, 1
To generate a normal branch success side test instruction, set the branch destination address to the next instruction address (Step 35)
, the process moves to step 18 in FIG. 3, and the flow in FIG. 4 ends.

Next, the differences in operation between the present invention and the conventional method will be explained in detail.

That is, in the advance control function having multiple streams in the present invention, the advance operation when a test instruction on the branch failure side is generated with a conditional branch instruction that increases the factors that disturb the advance control function (see Fig. 2 (a) (see FIG. 2(b)) and a conventional conditional branch instruction in which the instruction on the side of branch failure is not generated as a valid instruction (see FIG. 2(b)).

In FIG. 2(a), in the generation of the test instruction 9 according to the present invention,
A conditional branch instruction ■ is set as the instruction following the condition code setting instruction ■. In this case, the conditional branch instruction (2) is a branch success instruction, and the next instruction to be executed is instruction [phase].

When the test instruction 9 is executed by the data processing device 1 having a multi-stream advance control function, 1 of the machine cycle 10
In the second stage, the instruction ``■'' is decoded, and in the second stage, the address conversion A of the instruction ``■'' and the condition code setting instruction ``■'' are performed.
In the third stage, the operand read OF of instruction ■, the address conversion A of condition code setting instruction ■, and the conditional branch instruction ■ are decoded, and in the fourth stage, the instructions of The condition code for the condition code setting instruction ■ is not set, so the conditional branch instruction ■
Since the branch condition has not been determined, the preceding operation that starts with the decoding of the instruction (3) on the side of the branch failure is performed until the instruction in the sixth stage is decoded. However, at this point (7th stage), the branch of the conditional branch instruction ■ is determined by the condition code determined by the condition code setting instruction in the 5th stage, the stream is switched, and the branch destination instruction [
The decoding of the command of [phase] is executed.

Here, due to the address conversion and operand data read performed in the preceding operations performed for instructions ■ to ■, the registers, buffers, and memories that have already been changed are canceled, and the preceding control function is disturbed. cause the The present invention can also test for this disturbance of function.

In contrast, the conventional operation, that is, the operation of the advance control function when the test instruction according to the present invention is not generated, is
The result is as shown in Figure (b). That is, the order in which the test instructions 11 are executed by the data processing device 1 is shown in FIG.
), except that execution of the instruction on the unsuccessful branch side is interrupted. In other words, since the instruction on the unsuccessful branch side of the conditional branch instruction ■ is an invalid instruction that will not be executed, =19- Normally, arbitrary data that is not particularly conscious is set,
The execution result of test instruction 11 is the same as the execution result of test instruction 9 in FIG. 2(a). At this time, in the fourth stage of machine cycle 12, since the condition code of condition 2 1 - general instruction ■ has not been determined, the branch condition of conditional branch instruction ■ is also not determined, and an exception occurs on the side of unsuccessful branching. The instruction ■ is decoded, but if an exception is detected by decoding the exception generating instruction ■ in the 4th stage, the pre-operation from the 5th stage after the exception generating instruction ■ is stopped, and the pre-control is stopped. Since the decoding of the instruction of the branch destination instruction [phase] is waited for without causing any disturbance to the function, the test becomes a test with a reduced load as a test of the advance control function having multiple streams.

In this way, in this embodiment, in a pre-control function test with multiple streams, a branch instruction, especially a conditional branch instruction, is selected as a subsequent instruction of an instruction that sets a condition code using random number data and information in the instruction parameter table. Furthermore, if the branch is confirmed by the condition code, a test instruction is also generated on the successful side of the branch, so it is possible to generate a test instruction that works on multiple streams. As a result, by having the data processing device under test execute these test instructions, the prefetch execution results of the stream on the side of branch failure are cancelled. Tests that combine the status of registers and the operation of each stage of advance calculation can be performed in an environment that maximizes the potential of the advance control function.

〔Effect of the invention〕

As explained above, according to the present invention, in a preliminary control function test having multiple streams, a test that combines the states of various buffers, memories, and registers inside the hardware, and the operation of each stage of preliminary calculations is performed. Since instructions on the unsuccessful side of conditional branches are also executed, tests can be performed in an environment that maximizes the potential of the advance control function.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing device showing an embodiment of the present invention, and FIG. 2 is a sequence chart 1. FIG. 3 is a flowchart of a test instruction execution operation showing an embodiment of the present invention, FIG. 4 is a detailed operation flowchart of the test instruction generation process in FIG. 3, and FIG. 5 is a parameter group for generating a test instruction. Figure shown, No. 6
The figure shows the entry items of the instruction parameter table of FIG. 5, FIG. 7 shows an example of the instruction format information of the instruction parameter table of FIG. 6, and FIG. ○A diagram showing an example of P1 information, FIG. 9 is a table showing the numbers of general-purpose registers that are valid as pace registers during test instruction generation, and FIG. FIG. 11, which is a diagram showing the creation method, is a diagram showing a test instruction generation information table. 1: data processing device, 2: advance control function section, 3 near address translation mechanism section, 4: buffer memory, 5: register,
6: Main memory, 7: Random number program, 8: External storage, 9, 1.1: Test instruction, 10: 12: Machine cycle, 50: Instruction parameter table, 500: Branch instruction parameter group, 501: Other Instruction parameter group, 7
0: Instruction format, 71: Instruction code, 72: OP1 information,
74: OP2 information, 36: Register where random number data is stored, 38: Address where branch unsuccessful instruction is stored,
37: Register storing pace register number, 40
: Instruction information table. Patent applicant: Hitachi, Ltd. (1 idiot)
-1 9 Figure ○ 2 Unusable as base register 1: Valid as base register Figure 10 Figure 11 Figure Random number data 36 [47-5° to door inspector O1

Claims (1)

[Claims] 1. Generate a test command using random number data as input, calculate the expected value of the execution result of the test command through simulation, execute the test command on a pre-controlled data processing device under test having multiple streams, and calculate the execution result. In a test method for a data processing device that compares the expected value with the above expected value, when generating a test instruction using random number data as input, after generating an instruction to set a condition code, a branch instruction is generated as an instruction following the instruction. Data characterized by performing processing to increase the generation frequency and generating significant test instructions on both the branch success side and the branch failure side of the branch instruction so that advance control works on multiple streams. Processing equipment testing methods.