JPH01307260A - semiconductor memory cell - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor memory cells, and particularly to semiconductor memory cells used in dynamic access memories (hereinafter referred to as DRAMs).

BACKGROUND OF THE INVENTION Conventional semiconductor memory cells have 21 memory cells per memory cell.
By digging individual trenches and forming capacitor sections therein, the area occupied by the capacitor sections was reduced, and the memory cells were miniaturized.

For example, in the configuration shown in FIG. 5, a trench 27 is dug in a p-type semiconductor substrate 21, a capacitor insulating film 30 and a cell plate 29 are laminated in the trench, and a capacitor portion is formed on the side and bottom surfaces of the trench. There is. 22 is a transistor region, and 29 is an element isolation region.

Problems to be Solved by the Invention However, in the above configuration, the field effect transistor, the charge storage capacitor formed in the trench, and the adjacent element isolation region are formed in a planar area for each memory cell, so that additional memory is required. It was difficult to miniaturize cells.

In view of these points, it is an object of the present invention to provide a semiconductor memory cell having a configuration that allows further miniaturization compared to conventional memory cells.

Means for Solving the Problems In order to solve the above problems, the semiconductor memory cell of the present invention is provided by forming a plurality of grooves in a semiconductor substrate in which word lines can be completely buried, and disposing the word lines along the grooves. The memory cell region includes a field effect transistor formed at the bottom of the trench and a charge storage capacitor formed at the top of the trench, a drain region of the transistor being formed at the bottom of the trench, and a field effect transistor formed at the bottom of the trench. A source region of the transistor is connected to one electrode of the capacitor, and the other electrode of the capacitor is connected to a bit line.

According to the present invention, with the above-described configuration, a memory cell having a structure in which a field effect transistor and a charge storage capacitor are vertically formed in a groove can be obtained, so that the area occupied by the memory cell can be reduced. This makes it possible to realize an even larger capacity DRAM using this memory cell.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

1 to 3 show the structure of a semiconductor memory cell in an embodiment of the present invention. 1 is a plan view of the memory cell, FIG. 2 is a sectional view taken along line AA' in FIG. 1, and FIG. 3 is a sectional view taken along line BB' in FIG. 1. FIG. 4 is an equivalent circuit diagram of one memory cell.

A groove 2 as shown in FIG. 1, in which a word line 7 can be completely buried, is formed in a p-type Si substrate 1 by anisotropic etching. When poIySi3 is deposited on the bottom of this groove 2 and phosphorus is doped using vapor phase diffusion technology,
A heavily doped n++ diffused drain 4 is formed. This pol
Since the y S i 3 and the n medium diffusion layer drain 4 are formed on the entire bottom surface of the trench and connected to the end of the memory array, any bias can be applied to the drain 4 from the outside.

Next, an oxide film 5 and a gate oxide film 6 are formed by thermal oxidation, and polysilicon is filled to form a word line 7. Next, after depositing a thick oxide film in the trench 2 and above the Si substrate 1 by CVD or the like, the trench 9 is etched by anisotropic etching.
Dig at the location shown in Figure 1 and to the depth shown in Figure 2. After this step, an oxide film 5' and an isolation oxide film 8 are formed.

Next, as shown in FIGS. 1 to 3, a potyst capacitor electrode 10 is formed on the bottom surface, side surfaces, and around the opening of the trench 9, and by doping with phosphorus, the lower side surface of the trench 9 is raised. An n+ type diffused layer source 1 is formed. Further, thermal oxidation is performed to form a capacitor oxide film 12, and polysilicon is deposited so as to fill and cover the trench 9, thereby forming a bit line 13 which is also another electrode of the capacitor. In this way, a vertical MOS transistor 14 is formed with 11 as the source, 4 as the drain, 7 as the gate, and 6 as the gate oxide film, and 10 and 13 as the capacitor electrodes and 12 as the capacitor oxide film. A charge storage capacitor 15 is formed above the MOS
The source 11 of the transistor 14 and one electrode 10 of the capacitor 15 are connected.

As described in detail, according to the present invention, in a memory cell region arranged along a trench dug so that a word line is completely buried, a field effect transistor is placed at the bottom of the trench, By forming the field effect capacitor in the vertical direction on the upper part, it is possible to obtain a memory cell having a structure in which the occupied area can be extremely small and the density can be increased, and the practical effects thereof are extremely large.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor memory cell according to an embodiment of the present invention;
Figure 2 is a cross-sectional view taken along the line AA' in Figure 1, Figure 3 is a cross-sectional view taken along the line B-B' in Figure 1, and Figure 4 is an equivalent circuit of one memory cell. It is a diagram. FIG. 5 is a cross-sectional view of a conventional semiconductor memory cell. 1...p-type Si substrate, 2...groove, 4...
...Drain, 7...Word line, 10.
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Claims (5)

[Claims] (1) A plurality of trenches capable of completely burying word lines are formed in a semiconductor substrate, and in a memory cell region arranged in the trenches along the trenches, an electric field effect is formed under the trenches. a transistor and a charge storage capacitor formed on the top of the trench, a drain region of the transistor being formed at the bottom of the trench, and a source region of the transistor connected to one electrode of the capacitor; A semiconductor memory cell characterized in that the other electrode of the capacitor is connected to a bit line. (2) As the drain region of the field effect transistor, use a part of the high concentration diffusion layer of the opposite conductivity type to the substrate formed on the entire bottom of the trench, or 2. The semiconductor memory cell according to claim 1, wherein a portion of a heavily doped diffusion layer formed by contacting a conductor doped with an opposite conductivity type is used. (3) Doped polycrystalline S as a doped conductor
3. The semiconductor memory cell according to claim 2, wherein i is used. (4) As the element isolation region of the memory cell, at least a thick insulating film is formed on the top of the groove, or at least a high concentration diffusion layer of the same conductivity type as the substrate is formed on the top of the groove. A semiconductor memory cell according to claim 1. (5) As a source region of a field effect transistor, a highly concentrated diffusion layer of a conductivity type opposite to that of the substrate is formed on the side surface of the groove, and as a charge storage capacitor, it is used as a charge storage capacitor in contact with the diffusion layer on the side surface of the groove. Claim 1, characterized in that an insulating film and a conductor cell plate electrode are stacked on the conductor, and the cell node electrode is formed as a conductor, and the cell plate simultaneously serves as a bit line. semiconductor memory cell.