JPH01307261A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and in particular to a dynamic RA
This relates to the wiring structure of signal lines in M.

[Conventional technology]

Semiconductor memory device 1 For example, in a dynamic RAM, the bit line method (fold line system) is used as a wiring structure for signal lines that transmit information from each bit of storage element to a sense amplifier. There is a rad bit line method), and an example thereof will be explained with reference to FIG.

FIG. 3 is a schematic diagram of the equivalent circuit configuration of a conventional fold-delay pit line. As shown in FIG.
BLo, 8 mouths) + (BLl s kite), ..., (8
531 bits)...) are arranged in pairs, and a plurality of bits are connected to each bit line. At this time, for example, if another wire A is placed close to one bit line BLo, when some potential is applied to this wire A, the capacitance C between these wires A and bit line BLo
When it is large, it becomes noise and the potential of the bit line BL fluctuates. On the other hand, since the bit line 10 is far away, the wiring A
Not easily affected by electric potential. As a result, the sense amplifier S
When attempting to compare and detect the potential difference between each bit line BL and BL at A, the potential of one bit line iBL is fluctuating, so the result of comparison with the other bit line BLo is reversed. , so-called malfunctions occur.

To address this problem, a so-called twisted bit line system has been proposed in which two bit lines alternately cross each other multiple times, as shown in FIG. Taking as an example the wiring A which is also nearby, the noise from wiring A is caused by the noise from the wiring A which is nearby (in this case, the bit lines BL, ,
(both bit lines BL and BL are arranged with the same number of crossings, distances, etc. so that the additional capacitance C is the same), that is, the bit lines BL.

Affects BLo K equally. As a result, bit line B
When comparing and detecting the potential difference between Lo and BLo, the influence of noise can be almost ignored, so there is an advantage that malfunctions are less likely to occur.

[Problems that the invention attempts to solve]

Incidentally, in recent years, as memories have become more highly integrated, elements have become smaller and smaller, and the pitch of signal lines such as bit lines has also been reduced. In the conventional twisted pit line system described above, as shown in Figure 4,
Generally, the main bit lines BLo(3")*ate(3b) are formed in the same layer, and the bit line spacing d in this case is limited by the microfabrication limit. Therefore, 1. Dynamic RAM As memory signal lines become smaller, errors in information transmission due to noise from other lines occur.

The problem of so-called malfunctions has become apparent.

In view of the above points, the present invention has been made to solve these problems.The purpose of the present invention is to miniaturize the interval between two signal lines and to reduce the distance between adjacent wiring lines. An object of the present invention is to provide a semiconductor memory device that can suppress malfunctions in information transmission by equally distributing noise to each of two signal lines.

[Means to solve the problem]

In order to achieve the above object, a semiconductor memory device according to the present invention has a plurality of signal lines that transmit information from a storage element of each bit to a circuit such as a sense amplifier, and connects these signal lines to one sense amplifier. In a semiconductor memory device having a wiring structure in which two signal lines are arranged in parallel in the same direction, the two signal lines are made of different materials or different layers of the same material, and the two signal lines are arranged in parallel in the same direction. They are electrically separated and arranged in a manner that crosses each other once or multiple times, and 1 and 2.
The present invention is characterized in that the layers of the signal lines are arranged to be interchanged with each other through contact holes.

[Effect]

Therefore, in the present invention, the two signal lines are formed in different layers, and the two signal lines are electrically separated and crossed alternately once or multiple times. The spacing between lines can be made finer, and the influence of noise from one adjacent wiring can be minimized.

〔Example〕

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.

FIGS. 1(a) and 1) are a top view and a sectional view taken along line I-1' of a bit line intersection according to an embodiment of the present invention, and here, for convenience of explanation, two bit lines BL and , BL
・The case where it is applied is shown.

In this embodiment, two bit lines BL are arranged in parallel in the same direction from one sense amplifier.

1; After forming one of the bit lines BLo (3a), for example, with a first polycrystalline silicon layer, on the surface of the silicon oxide film 20 formed on the silicon substrate 1 including memory elements and peripheral circuits, An interlayer insulating film 4 such as 5i02 is formed. Then, the other bit line Bto (3b) is formed on this glabellar insulating film 4 using a second polycrystalline silicon layer. At this time, the interval d between each bit line can be reduced because it is separated into upper and lower layers, and d<0. Two bit lines BLo (3m), BLo (3b)
It is also possible to have 6 matches that overlap. Next, these two bit lines (
3m.

3b), the layers are exchanged with each other via the contact holes 5m and 5b on the interlayer insulating film 4. That is, when one bit line BL (1 (3 m)) is formed of the first polycrystalline polysilicon layer, after crossing, it is connected to the upper second polycrystalline polysilicon layer via the contact hole 5a. , the bit line shoal (3b) formed of the other second polycrystalline silicon layer is inserted into the contact hole 5b after crossing.
The first polycrystalline silicon layer is connected to the lower first polycrystalline silicon layer through the first polycrystalline silicon layer.

In this way, according to the above embodiment, the two bit lines BL,
, BLo are formed of different layers consisting of first and second polycrystalline silicon layers and alternately intersect multiple times in an electrically isolated state, and the two bit lines BLo are formed before and after this intersection. , BL (10 layers in each contact hole 5a, 5b)
By creating a wiring structure in which the wires are exchanged with each other via the
The equivalent circuit is shown in FIG. As a result, as shown in FIG. 2, the influence of noise from the adjacent wiring A can be equally distributed to each bit line BLo, no matter which layer it is influenced by. Therefore, the influence of noise from adjacent wiring can be suppressed to a minimum, and miniaturization between bit lines can be realized.

Note that in the above embodiment, one set of bit lines (BLo aBL
Although we have explained the case where o) is applied, multiple sets (BL
n, BLn)K can of course be applied to dynamic RA
A similar effect can be expected not only for the M bit line but also for wiring that combines two signal lines such as a reference line and a comparison line, and can be applied to memory buses other than dynamic RAM or all signal lines in logic devices. Needless to say, it can be applied.

In addition to the single polycrystalline silicon, the two signal lines are
Of course, the polycrystalline silicon TFC may be composed of a high melting point metal or a composite film thereof, or a combination of the same or different low melting point metals.

〔Effect of the invention〕

As explained above, according to the present invention, two signal lines are formed in different layers, and the two signal lines are made to alternately cross at least once or more while being electrically separated. Therefore, the interval between two signal lines can be made finer, and the influence of noise from adjacent wiring can be minimized, which has an excellent effect on improving the reliability of information transmission in a semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 (, ) and 弽) are a top view of a bit line intersection according to an embodiment of the present invention and a sectional view thereof taken along the line I-I', and FIG. 2 is an equivalent circuit configuration for explaining the embodiment of the present invention. Schematic diagram of
FIG. 3 is a schematic diagram of a circuit configuration according to a conventional example, and FIG. 4 is a top view of two bit lines for explaining the drawbacks of the conventional example. 1・00. Silicon base L2..., silicon oxide film,
3a...Bit line (BLO), 3b...
Bit line (-15), 4... interlayer insulating film, 5a,
5b...Contact hole.

Claims (1)

[Claims] It has a wiring structure that has multiple signal lines that transmit information from the memory element of each bit to a circuit such as a sense amplifier, and arranges two signal lines from one sense amplifier in parallel in the same direction. In the semiconductor memory device, the two signal lines are made of different materials or different layers of the same material, and the two signal lines are electrically separated and arranged so as to alternately cross once or multiple times. A semiconductor memory device characterized in that the layers of the two signal lines are configured to be exchanged with each other via contact holes.