JPH01310560A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH01310560A
JPH01310560A JP63142121A JP14212188A JPH01310560A JP H01310560 A JPH01310560 A JP H01310560A JP 63142121 A JP63142121 A JP 63142121A JP 14212188 A JP14212188 A JP 14212188A JP H01310560 A JPH01310560 A JP H01310560A
Authority
JP
Japan
Prior art keywords
insulating film
metal wiring
wiring
metal
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63142121A
Other languages
Japanese (ja)
Inventor
Osamu Ishikawa
修 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63142121A priority Critical patent/JPH01310560A/en
Publication of JPH01310560A publication Critical patent/JPH01310560A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To lessen an inter-wiring capacity and to minimize an inter-wiring crosstalk by a method wherein the film thickness of a first insulating film at a region other than metal wiring regions is made thinner than that of the first insulating film positioned right under the metal wirings. CONSTITUTION:The film thickness of a first insulating film 2 at a region other than metal wiring regions 3-1 and 3-2 is made thinner than that of the first insulating layer 2 positioned right under the wirings 3-1 and 3-2 or the film 2 is left only right under the wirings 3-1 and 3-2 and the film 2 at the region other than the wiring regions 3-1 and 3-2 is removed. Accordingly, part or the whole part of the film 2 positioned between a plurality of the wirings 3-1 and 3-2 parallel to each other can be substituted for the air of permittivity lower than that of the layer 2 or an atmosphere equivalent to that. Thereby, a line-to-line capacity is reduced by the amount of permittivity difference and a line-to-line crosstalk can be inhibited.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、高速の集積回路において、互いに平行な複数
の金属配線間のクロストークを低減するための構成及び
その形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a structure and a method for forming the same for reducing crosstalk between a plurality of parallel metal lines in a high-speed integrated circuit.

従来の技術 集積回路の高速化及び小型化は、トランジスタの縮小化
による性能向上と共に、配線の線路幅及び配線間隔の縮
小によりもたらされてきた。しかしながら、配線の線路
幅及び配線間隔の縮小により、新たに抵抗の増大による
信号伝搬遅延及び線路間容量の増大によるクロストーク
の問題が発生してきた。特に高速のデジタル集積回路に
おいては、互いに平行な複数の金属配線を引き回して用
いることが多く、配線間のクロストークにより誤動作し
たりノイズが乗ってくるな・ど非常に大きな問題となっ
ている。配線間のクロストークは配線間の容、量により
決定されるので如何にこの配線間の容量を低減するかが
重要なポイントである。
BACKGROUND OF THE INVENTION The speeding up and miniaturization of integrated circuits has been brought about by reducing the width of interconnects and spacing between interconnects, as well as improving performance by reducing the size of transistors. However, with the reduction in line width and line spacing, new problems have arisen, such as signal propagation delay due to increased resistance and crosstalk due to increased capacitance between lines. Particularly in high-speed digital integrated circuits, multiple metal wires are often routed in parallel to each other, which poses serious problems such as malfunctions and noise caused by crosstalk between the wires. Crosstalk between wires is determined by the capacitance and amount between wires, so how to reduce the capacitance between wires is an important point.

第5図は、従来の半導体装置を示す第1の例である。第
5図において、半導体基板として半絶縁性GaAa基板
1を用い、この半絶縁性GaAa基板1上に直接互いに
平行な第1金属配線3−1及び第2金属配線3−2を形
成したものである。
FIG. 5 is a first example showing a conventional semiconductor device. In FIG. 5, a semi-insulating GaAa substrate 1 is used as a semiconductor substrate, and a first metal wiring 3-1 and a second metal wiring 3-2 are directly formed in parallel to each other on this semi-insulating GaAa substrate 1. be.

第5図に示した構成において互いに平行な第1金属配線
3−1と第2金属記線3−2との間の容量は、配線間隔
及び配線幅をそれぞれ1μmとした場合80 f F/
mmから100fF/mm程度と非常に大きな値を示し
た。この大きな配線間容量は半絶縁性GaAa基板1の
持っている大きな誘 ・電率(例えば半絶縁性GaAa
基板の場合には、誘電率は12.9程度)に起因してい
る。
In the configuration shown in FIG. 5, the capacitance between the first metal wiring 3-1 and the second metal marking line 3-2 that are parallel to each other is 80 f F/ when the wiring spacing and wiring width are each 1 μm.
It showed a very large value of about 100 fF/mm to 100 fF/mm. This large inter-wiring capacitance is due to the large permittivity and electric constant of the semi-insulating GaAa substrate 1 (for example, the semi-insulating GaAa
In the case of the substrate, the dielectric constant is approximately 12.9).

第6図は、従来の半導体装置を示す第2の例である。第
6図においても、半導体基板として半絶縁性GaAa基
板1を用いる。この半絶縁性GaAa基板1上に第1絶
縁膜2を堆積したのち第5図と同様に互いに平行な第1
金属配線3−1及び第2金属配線3−2を形成したもの
である。第1絶縁膜2としては5i02を通常用いる。
FIG. 6 shows a second example of a conventional semiconductor device. Also in FIG. 6, a semi-insulating GaAa substrate 1 is used as the semiconductor substrate. After depositing a first insulating film 2 on this semi-insulating GaAa substrate 1, first insulating films 2 are deposited parallel to each other as shown in FIG.
A metal wiring 3-1 and a second metal wiring 3-2 are formed. As the first insulating film 2, 5i02 is usually used.

互いに平行な第1金属配線3−1及び第2金属配線3−
2の下に、半絶縁性GaAa基板1より誘電率の小さい
第1絶縁膜2を用いたことにより、互いに平行な第1金
属配線3−1と第2金属配線3−2との間の容量は、第
1絶縁M2の膜厚を1μmとし、配線間隔及び配線幅を
それぞれ1μmとした場合10 f F/mmから20
 f F/mm程度と第5図に示した従来の半導体装置
の第1の例に比べ大きく減少はしているものの配線間の
、クロストークを極小とする為には不十分である。第1
絶縁膜2の膜厚が1μm以下と薄くなるとこの容量は増
加する。
First metal wiring 3-1 and second metal wiring 3- parallel to each other
By using the first insulating film 2, which has a dielectric constant lower than that of the semi-insulating GaAa substrate 1, under the semi-insulating GaAa substrate 1, the capacitance between the first metal wiring 3-1 and the second metal wiring 3-2, which are parallel to each other, is reduced. is 10 f F/mm to 20 when the film thickness of the first insulating M2 is 1 μm and the wiring spacing and wiring width are each 1 μm.
Although it is approximately f F/mm, which is a large decrease compared to the first example of the conventional semiconductor device shown in FIG. 5, it is not sufficient to minimize the crosstalk between wiring lines. 1st
This capacitance increases when the thickness of the insulating film 2 is reduced to 1 μm or less.

発明が解決しようとする課題 第5図及び第6図に示した従来の半導体装置においては
、互いに平行な第1金属配線3−1と第2金属配線3−
2との間の容量は、配線間隔及び配線幅をそれぞれ1μ
mとした場合10 f F/mmから100 f F/
mm程度もあり配線間のクロストークを極小とする為に
は不十分である。配線間隔が狭くなれば配線間容量は更
に増加しクロストークも増える。
Problems to be Solved by the Invention In the conventional semiconductor device shown in FIGS. 5 and 6, the first metal wiring 3-1 and the second metal wiring 3- are parallel to each other.
2, the wiring spacing and wiring width are each 1 μm.
m, from 10 f F/mm to 100 f F/
It is about mm, which is insufficient to minimize crosstalk between wiring lines. If the wiring spacing becomes narrower, the capacitance between the wirings will further increase and crosstalk will also increase.

本発明は、かかる点に鑑みてなされたもので、互いに平
行な複数の金属配線が形成された構成において、配線間
容量が小さく配線間のクロストークを極小とすることが
できる優れた半導体装置及びその製造方法を提供するこ
とを目的としている。
The present invention has been made in view of the above, and provides an excellent semiconductor device and a device capable of minimizing inter-wiring capacitance and minimizing crosstalk between wirings in a configuration in which a plurality of parallel metal wirings are formed. The purpose of this invention is to provide a manufacturing method for the same.

課題を解決するための手段 本発明は上記課題を解決する為、半導体基板上に、第1
絶縁膜とこの第1絶縁膜上に互いに平行な複数の金属配
線が形成された構成において、金属配線領域以外の第1
絶縁膜の膜厚を、金属配線の直下に位置する第1絶縁膜
の膜厚より薄くするか、もしくは第1絶縁膜を金属配線
の直下にのみ残し、金属配線領域以外の領域の第1絶縁
膜を除去する。製造方法は、半導体基板上に、第1絶縁
膜とこの第1絶縁膜上に互いに平行な複数の金属配線を
形成した後、金属配線をマスク材として第1絶縁膜をエ
ツチングし金属配線領域以外の第1絶縁膜の膜厚を薄く
するか、もしくは完全に除去する。
Means for Solving the Problems In order to solve the above problems, the present invention provides a method for solving the problems described above.
In a configuration in which a plurality of metal interconnects parallel to each other are formed on an insulating film and the first insulating film, the first insulating film other than the metal interconnect region
Either the thickness of the insulating film is made thinner than the thickness of the first insulating film located directly under the metal wiring, or the first insulating film is left only directly under the metal wiring, and the first insulating film is removed in areas other than the metal wiring area. Remove membrane. The manufacturing method is to form a first insulating film and a plurality of metal wirings parallel to each other on the first insulating film on a semiconductor substrate, and then to etch the first insulating film using the metal wiring as a mask material to remove the area other than the metal wiring area. The thickness of the first insulating film is reduced or completely removed.

作用 本発明は上記した構成により、互いに平行な複数の金属
配線の間に位置している第1絶縁膜の一部分又はその全
部分を、第1絶縁膜より誘電率の低い空気又はそれと等
価な雰囲気で置き換えることができるので線路間容量を
誘電率の差分だけ更に低減でき、線路間のクロストーク
を抑えることが出来る。又、本発明は上記した製造方法
により、第1絶縁膜上に形成した金属配線をマスク材と
して第1絶縁膜をエツチングするのでエツチングが金属
配線に整合して行われマスクずれ等の問題もなく安定で
あり、新たなマスクの作製及びマスク合わせの工程も不
用である。
Effect of the present invention With the above-described configuration, a portion or the entire portion of the first insulating film located between a plurality of metal wirings parallel to each other is covered with air having a lower dielectric constant than the first insulating film or an atmosphere equivalent thereto. Since it can be replaced by , the inter-line capacitance can be further reduced by the difference in dielectric constant, and crosstalk between the lines can be suppressed. Further, according to the present invention, the first insulating film is etched using the metal wiring formed on the first insulating film as a mask material by the above-described manufacturing method, so that etching is performed in alignment with the metal wiring, and there is no problem such as mask displacement. It is stable and does not require the process of creating a new mask or matching the masks.

実施例 第1図は、本発明の半導体装置を示す第1の実施例の断
面図である。第1図に示した本発明の半導体装置におい
て、第5図及び第6図と等価な部分については同一の参
照番号を付して示すものとする。第1図は、半導体基板
として半絶縁性GaAa基板1を用い、この半絶縁性G
aAa基板1上に第1絶縁膜2及び互いに平行な第1金
属配線3−1及び第2金属配線3−2を形成したもので
ある。第1絶縁膜2としてはSiO2を用いる。互いに
平行な第1金属配線3−1及び第2金属配線3−2の下
に、半絶縁性GaAa基板1より誘電率の小さい第1絶
縁膜2を用いたこと及び互いに平行な第1金属配線3−
1及び第2金属配線3−2の間に位置する第1絶縁膜2
を一部分エッチング除去しであるので第1絶縁11X2
の堆積膜厚を1”μmとし、配線間隔及び配線幅をそれ
ぞれ1μmとした場合5fF/mmから8 f F/m
m程度と従来の約半分の配線間容量にまで低減できる。
Embodiment FIG. 1 is a sectional view of a first embodiment of the semiconductor device of the present invention. In the semiconductor device of the present invention shown in FIG. 1, parts equivalent to those in FIGS. 5 and 6 are designated by the same reference numerals. In FIG. 1, a semi-insulating GaAa substrate 1 is used as a semiconductor substrate, and this semi-insulating G
A first insulating film 2 and a first metal wiring 3-1 and a second metal wiring 3-2 which are parallel to each other are formed on an aAa substrate 1. As the first insulating film 2, SiO2 is used. The first insulating film 2 having a lower dielectric constant than the semi-insulating GaAa substrate 1 is used under the first metal wiring 3-1 and the second metal wiring 3-2 which are parallel to each other, and the first metal wiring which is parallel to each other. 3-
1 and the second metal wiring 3-2.
Since the first insulation is partially etched away, the first insulation 11X2
5 fF/mm to 8 fF/m when the deposited film thickness is 1” μm, and the wiring spacing and wire width are each 1 μm.
The inter-wiring capacitance can be reduced to approximately half of that of the conventional method.

第2図は、本発明の半導体装置を示す第2の実施例の断
面図である。第2図において、互いに平行な第1金属配
線3−1及び第2金属配線3−2の間に位置する第1絶
縁膜2は完全にエツチング除去されており半絶縁性Ga
As基板1は表面に露出した状態になっている。従って
第1絶縁膜2の堆積膜厚を1μmとし、配線間°隔及び
配線幅をそれぞれ1μmとした場合3 f F/mmか
ら6fF/mm程度の配線間容量にまで更に低減できる
FIG. 2 is a sectional view of a second embodiment of the semiconductor device of the present invention. In FIG. 2, the first insulating film 2 located between the first metal wiring 3-1 and the second metal wiring 3-2, which are parallel to each other, has been completely etched away and is made of semi-insulating Ga.
The As substrate 1 is exposed on the surface. Therefore, when the deposited film thickness of the first insulating film 2 is 1 μm, and the wire spacing and wire width are each 1 μm, the inter-wire capacitance can be further reduced from 3 fF/mm to about 6 fF/mm.

第3図は、本発明の半導体装置を示す第3の実施例の断
面図である。表面保護のために第2絶縁膜4を半絶縁性
GaAs基板1及び第1金属配線3−1及び第2金属配
線3−2の上に全面堆積した例である。第2絶縁膜4の
膜厚は、0.1μm程度で十分ある。第3図に示した本
発明の第3の実施例においても第1絶縁膜2は完全にエ
ツチング除去されており半絶縁性GaAs基板1は表面
に露出させた状態のあと第2絶縁膜4が薄く堆積されて
おり配線間容量の増加もあるが金属配線の表面を保護で
きる。
FIG. 3 is a sectional view of a third embodiment of the semiconductor device of the present invention. This is an example in which a second insulating film 4 is deposited over the entire surface of the semi-insulating GaAs substrate 1, the first metal wiring 3-1, and the second metal wiring 3-2 for surface protection. The thickness of the second insulating film 4 is approximately 0.1 μm, which is sufficient. Also in the third embodiment of the present invention shown in FIG. 3, the first insulating film 2 is completely etched away, and the semi-insulating GaAs substrate 1 is left exposed on the surface, and then the second insulating film 4 is removed. Although it is deposited thinly and increases inter-wiring capacitance, it can protect the surface of metal wiring.

第4図は、本発明の半導体装置を具体的に実現できる半
導体装置の製造方法を示す工程断面図である。第4図a
)は半絶縁性GaAs基板1の上に第1絶縁膜2を堆積
する工程である。第4図b)は、第1絶縁膜2の上に互
いに平行な第1金属配線3−1及び第2金属配線3−2
を形・成する工程である。第4図C〉は、第1金属配線
3−1及び第2金属配線3−2をマスクに用いて、第1
絶縁膜2をエツチング5をする工程である。この第4図
C)に示した工程により、互いに平行な第1金属配線3
−1及び第2金属配線3−2に被われた領域以外の第1
絶縁膜2がエツチングされ配線間容量が低減されるので
ある。エツチングは、通常用いられるプラズマイオンを
用いる。第4図d)は、第4図C)に示したエツチング
工程により第1絶縁膜2を完全に除去した結果を示して
おり、互いに平行な第1金属配線3−1及び第2金属配
線3−2の直下のみに第1絶縁膜2が残される。第4図
に示した本発明の製造方法では、互いに平行な第1金属
配線3−1及び第2金属配線3−2の直下のみに第1絶
゛縁膜2が残される例を用いたが、第4図C)に示した
ように線間に位置する第1絶縁膜2を半分程度エツチン
グ除去した状態でも線間容量を低減できることは、本発
明の詳細な説明したのと同じである。
FIG. 4 is a process cross-sectional view showing a method of manufacturing a semiconductor device that can specifically realize the semiconductor device of the present invention. Figure 4a
) is a step of depositing a first insulating film 2 on a semi-insulating GaAs substrate 1. FIG. 4b) shows a first metal wiring 3-1 and a second metal wiring 3-2 parallel to each other on the first insulating film 2.
It is a process of forming and forming. In FIG. 4C, the first metal wiring 3-1 and the second metal wiring 3-2 are used as masks to
This is a step of etching 5 the insulating film 2. By the process shown in FIG. 4C), the first metal wirings 3 parallel to each other are
-1 and the first area other than the area covered by the second metal wiring 3-2.
The insulating film 2 is etched and the inter-wiring capacitance is reduced. Etching uses commonly used plasma ions. FIG. 4 d) shows the result of completely removing the first insulating film 2 by the etching process shown in FIG. The first insulating film 2 is left only directly under -2. In the manufacturing method of the present invention shown in FIG. 4, an example is used in which the first insulating film 2 is left only directly under the first metal wiring 3-1 and the second metal wiring 3-2 which are parallel to each other. As shown in FIG. 4C, the line capacitance can be reduced even when about half of the first insulating film 2 located between the lines is removed by etching, which is the same as the detailed explanation of the present invention.

以上説明したように、本発明の半導体装置及びその製造
方法を用いることで、例えば第1絶縁膜2の膜厚を1μ
mとし、配線間隔及び配線幅をそれぞれ1μmとした場
合4 fF/mmから6fF/mm程度の配線間容量と
なり従来の半分以下に低減することができる。また、第
1絶縁膜上に形成した金属配線をマスク材として第1絶
縁膜をエツチングするので、エツチングが金属配線に整
合して行われマスクずれ等の問題もな(安定であり、新
たなマスクの作製及びマスク合わせの工程も不用である
As explained above, by using the semiconductor device and the manufacturing method thereof of the present invention, the thickness of the first insulating film 2 can be reduced to 1 μm, for example.
m, and when the wiring spacing and wiring width are each 1 μm, the inter-wiring capacitance is about 4 fF/mm to 6 fF/mm, which can be reduced to less than half of the conventional value. In addition, since the first insulating film is etched using the metal wiring formed on the first insulating film as a mask material, the etching is performed in alignment with the metal wiring, and there is no problem such as mask displacement (it is stable and requires a new mask). The steps of manufacturing and mask matching are also unnecessary.

発明の効果 以上述べてきた様に、本発明により次の効果がもたらさ
れる。
Effects of the Invention As described above, the present invention brings about the following effects.

1)互いに平行な金属配線の間の線間容量が、例えば第
1絶縁膜2の膜厚を1μmとし、配線間隔及び配線幅を
それぞれ1μmとした場合4fF/mmから6 fF/
mm程度の値となり従来の半分以下に低減することがで
きる。従って、クロストーク等の問題が軽減され高速の
信号処理が正確に行うことができる。
1) The line capacitance between parallel metal wirings ranges from 4 fF/mm to 6 fF/mm, for example, when the thickness of the first insulating film 2 is 1 μm, and the wire spacing and width are each 1 μm.
It becomes a value of about mm, which can be reduced to less than half of the conventional value. Therefore, problems such as crosstalk are reduced, and high-speed signal processing can be performed accurately.

2)第1絶縁膜上に形成した金属配線をマスク材として
第1絶縁膜をエツチングするのでエツチングが金属配線
に整合して行われマスクずれ等の問題もなく安定であり
、新たなマスクの作製及びマスク合わせの工程も不用で
ある。
2) Since the first insulating film is etched using the metal wiring formed on the first insulating film as a mask material, the etching is performed in alignment with the metal wiring and is stable without problems such as mask displacement, making it possible to create a new mask. Also, the process of mask alignment is unnecessary.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図、第3図はそれぞれ本発明の半導体装置
の第1、第2、第3の実施例を示す半導体装置の断面図
、第4図は本発明の半導体装置の製造方法を示す工程断
面図、第5図及び第6図は従来の半導体装置を示す断面
図である。 1会・φ半絶縁性GaAs基板、2・・・第1絶縁膜、
3−1−・魯第1金属配線、3−2◆会・第2金属配線
、4・・・第2絶縁膜、5・・・エツチング。 代理人の氏名 弁理士 中尾敏男 ほか1名I千屑9券
と江セハJ−女
1, 2, and 3 are cross-sectional views of semiconductor devices showing first, second, and third embodiments of the semiconductor device of the present invention, respectively, and FIG. 4 is a method for manufacturing the semiconductor device of the present invention. FIGS. 5 and 6 are cross-sectional views showing conventional semiconductor devices. 1. φ semi-insulating GaAs substrate, 2... first insulating film,
3-1--first metal wiring, 3-2◆-second metal wiring, 4--second insulating film, 5--etching. Name of agent: Patent attorney Toshio Nakao and 1 other person I Senku 9 and Eseha J-Female

Claims (4)

【特許請求の範囲】[Claims] (1)半導体基板上に、第1絶縁膜とこの第1絶縁膜上
に互いに平行な複数の金属配線が形成された構成におい
て、前記金属配線領域以外の第1絶縁膜の膜厚が、金属
配線の直下に位置する第1絶縁膜の膜厚より薄くなって
いることを特徴とする半導体装置。
(1) In a structure in which a first insulating film and a plurality of metal wirings parallel to each other are formed on the first insulating film on a semiconductor substrate, the film thickness of the first insulating film other than the metal wiring region is A semiconductor device characterized in that the thickness of the first insulating film is thinner than that of a first insulating film located directly below a wiring.
(2)第1絶縁膜が金属配線の直下にのみ残され、金属
配線領域以外に位置する第1絶縁膜が除去されているこ
とを特徴とする特許請求の範囲第1項記載の半導体装置
(2) The semiconductor device according to claim 1, wherein the first insulating film is left only directly under the metal wiring, and the first insulating film located outside the metal wiring area is removed.
(3)半導体基板上の第1絶縁膜、及び金属配線上の全
面に第2絶縁膜を有していることを特徴とする特許請求
の範囲第1項又は第2項記載の半導体装置。
(3) The semiconductor device according to claim 1 or 2, further comprising a first insulating film on the semiconductor substrate and a second insulating film all over the metal wiring.
(4)半導体基板上に、第1絶縁膜とこの第1絶縁膜上
に互いに平行な複数の金属配線を形成した後、金属配線
をマスク材として第1絶縁膜をエッチングすることを特
徴とする半導体装置の製造方法。
(4) After forming a first insulating film and a plurality of metal wirings parallel to each other on the first insulating film on the semiconductor substrate, the first insulating film is etched using the metal wiring as a mask material. A method for manufacturing a semiconductor device.
JP63142121A 1988-06-09 1988-06-09 Semiconductor device and manufacture thereof Pending JPH01310560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63142121A JPH01310560A (en) 1988-06-09 1988-06-09 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63142121A JPH01310560A (en) 1988-06-09 1988-06-09 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH01310560A true JPH01310560A (en) 1989-12-14

Family

ID=15307886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63142121A Pending JPH01310560A (en) 1988-06-09 1988-06-09 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH01310560A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0614221A1 (en) * 1993-03-05 1994-09-07 Fujitsu Limited Integrated transmission line structure
US6340798B1 (en) 1999-11-30 2002-01-22 Fujitsu Limited Printed circuit board with reduced crosstalk noise and method of forming wiring lines on a board to form such a printed circuit board
JP2009212481A (en) * 2007-04-27 2009-09-17 Sharp Corp Semiconductor device and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0614221A1 (en) * 1993-03-05 1994-09-07 Fujitsu Limited Integrated transmission line structure
US6340798B1 (en) 1999-11-30 2002-01-22 Fujitsu Limited Printed circuit board with reduced crosstalk noise and method of forming wiring lines on a board to form such a printed circuit board
JP2009212481A (en) * 2007-04-27 2009-09-17 Sharp Corp Semiconductor device and manufacturing method thereof
US7906856B2 (en) 2007-04-27 2011-03-15 Sharp Kabushiki Kaisha Semiconductor device and method for manufacturing semiconductor device

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