JPH01311475A - Recorder, reproducing device, and tape like recording medium for pcm data - Google Patents

Abstract

PURPOSE:To prevent the deterioration of a signal from being prominent after correction by separating data to even-th data and odd-th data at every unit hour/minute of PCM data, and recording them at positions separated from each other in a direction of tape width. CONSTITUTION:Audio signals SL and SR on a left channel and a right channel are inputted from input terminals 21 and 22, and are converted to a PCM signal So by an A/D converter 21. The signal So is written on RAMs (31-33) sequentially via a switch 25. Next, the signal in the RAMs (31-33) is read out sequentially via a switch 29, and is recorded on tracks 4A and 4B by forming the tracks on a magnetic tape 2 alternately by rotary heads 1A and 1B. In other words, at the first halves of the tracks 4A and 4B, the even-th data 0E, 1E, 2E... are recorded, and at the latter halves, the odd-th data 1O, 2O, 3O... are recorded. In such a way, it is possible to obtain the data successively without missing the data when the data is recovered to the one of original time sequence at the time of reproduction even when the data of one track is missed at the time of reproduction.

Description

[Detailed Description of the Invention] When recording and reproducing information signals, for example audio signals,
By converting this audio signal into PCM, high-quality recording and playback can be achieved.

There are fixed head methods and rotating head methods for converting information signals into PCM and recording and reproducing them on magnetic tape.
The rotating head method is advantageous in that the relative speed of the head to the tape is fast and the recording density can be easily increased.

In this rotary head system, for example, when a plurality of rotary heads, for example two, are used, the rotary heads are usually placed in the same angular range (18
0°), and two rotating heads alternately form one track each to record PCM data.

By the way, when recording this PCM data, data for a unit time (one segment of data), which is conventionally recorded as one track each, is recorded directly on the tape.
Since it is recorded as a track, part 1
If a track's worth of reproduced data is lost due to dropout or the like, a state will occur in which no data exists for a period of time equivalent to this one track. Even if this happens, in the so-called error correction circuit, for example, the previous one
Although it is possible to correct errors using error correction methods such as so-called pre-hold, which interpolates using track data,
Since completely missing data is interpolated with previous data, etc., there is a drawback that signal deterioration is inevitable.

In view of the above points, this invention is designed so that even if 1' track worth of data is lost during playback, when the original time series data is restored during playback, the data can be obtained continuously without almost any loss. The present invention aims to provide a system that is capable of strengthening against bust errors, easily using advanced methods for error correction, and making it possible to make signal deterioration almost inconspicuous after correction. It is something to do.

Hereinafter, an example of the present invention will be explained with reference to the drawings, taking as an example a case where an audio signal is converted into PCM and recorded.

By the way, when a PCM signal is recorded by a rotary head device, as in the case of a conventional rotary head device, for example, there are two rotary heads and the angular interval between them is 180°.
The tape wraps around the guide drum at the same 180° angle.
In the case of audio PCM, the two heads alternately and continuously scan the tape, forming tracks continuously without any time gaps.
There is no longer enough time to add redundant data such as parity for error correction to the signal. Therefore, a large amount of buffer memory for signal delay must be used, and signal processing tends to become complicated.

Therefore, in this example, a new device is used which is particularly designed to avoid the above-mentioned drawbacks as the rotary head type recording and reproducing device.

FIG. 1 shows an example of a rotary head device used in this new device, and this is a case where there are two rotary magnetic heads. In this case, these two rotating heads (18) are placed together. on the other hand,
The magnetic tape (2) is wound around the circumferential surface of the tape guide drum (3) in an angular range section smaller than its 180° angular range, for example 90'. Then, the rotating heads (1^) and (IB) are rotated at a rate of 30 revolutions per second in the direction shown by the arrow (5■) in the figure, and
The tape (2) is run at a predetermined speed in the direction shown by the arrow (5T), and the rotary heads (IA) and (IB) perform the two rotations on the magnetic tape (2) as shown in FIG. one diagonal magnetic track (4
^) and (4B) are formed alternately to record the signal. In this case, heads (IA) and (IB)
The width directions of the gaps are different from each other with respect to the direction orthogonal to the scanning direction. In other words,
The so-called azimuth angles are made different.

According to the above rotary head device, two rotary heads (L
A period (this is the period of the 90° angular range bone in this example) occurs during which A) and (IB) are not in contact with the magnetic tape (2), and this period is used to calculate the PCM data. By adding redundant data such as parity, the number of buffer circuits in the recording apparatus can be reduced and the configuration can be simplified.

Next, an embodiment of a recording device and a reproducing device thereof according to the present invention using this rotary head device will be described.

FIG. 3 shows an example of a recording system.

The example shown in FIG. 3 is an example in which an audio signal is recorded as a two-channel signal of a right channel and a left channel.

In this case, the rotating magnetic heads (IA) and (IB) are rotated at 30 Hz as described above, and the rotational phase is controlled as follows.

That is, in the control signal generation circuit (10), the reference signal CT of 301(z) generated based on the master clock signal from the master clock generation circuit (9) is supplied to the phase comparator circuit (8). Ru.

Further, a signal PC from a pulse generator (6) that generates one pulse per rotation of the rotary heads (IA) and (IB) is supplied to this phase comparator circuit (8), from which signal CT and signal A voltage corresponding to the phase error with the PC is supplied to the rotary head driving drum motor (7) so that the phase of the signal CT and the rotational phases of the rotary heads (18) and (IB) have a predetermined relationship. controlled by.

The control signal generating circuit (10) also generates various control signals as described below in addition to the signal CT based on this master clock signal.

Therefore, the phase of the various control signals is the signal C
It is synchronized with the phase of T, that is, the rotational phase of heads (IA) and (IB).

The left channel and right channel audio signals SL and SR are supplied to one and the other input ends of the switch circuit (23) through input terminals (21) and (22).

This switch circuit (23) is alternately switched to one and the other input terminal by a switching signal SW of, for example, 44.1 kHz (FIG. 4A) from the control signal generating circuit (10). Therefore, as shown in FIGS. 4A and 4B, this switch circuit (23) outputs the left channel signal when the switching signal SW is at a high level, and the right channel signal when the signal SW is at a low level. The signals are respectively taken out and this is A/
It is supplied to the D converter (24). In this A/D converter (24), sampling is performed at a sampling frequency of 44.1 kHz per channel. The signal SP from the control signal generation circuit (10) is this sampling signal, and the left and right channel audio signals are each sampled by this signal SP, and the sampled data is converted into a PCM of, for example, 16 bits per sample. It is converted into a signal So.

FIG. 4B shows the output signal S0 of this A/D converter, Lo, L, L2, etc. each indicate one data word of the audio PCM signal of the left channel, and R
o, R1, Rz... are right channel audio P
Each shows one data word of the CM signal.

Output signal S of the A/D converter (24). is connected to three RAMs (31), (
32) and (33), but as described later, two of the three RAMs are not in the write state, and the two RAMs that are not in the write state are not used to add redundant data or Data to which redundant data is added is read out.

3 RAMs from the control signal generation circuit (10)
The control signal RW for controlling the writing of (31), (32), (33) is sent to the three RAMs (31), (32), (
33) is supplied to the control terminal.

Then, the switch circuits (25) and (26) use the switching signal SWW from the control signal generation circuit (10) to switch the three RAMs (31
).

(32) and (33) are sequentially switched every □ seconds. In other words, 3 RAM (31) ~ (
33) can be switched.

Therefore, 3 RAM (31), (32)
, (33), PCM audio data for a unit time of □ seconds is sequentially written as shown in Figure 4 C, D, and H. That is, RAM (31)
The data group (1) for unit time is stored in RAM (32)
The data group [2] for the next unit time is stored in RAM (3
In addition to 3), the data group [3] for the next unit time is
In this way, the data group for a period of □ seconds is divided into three RAs.
It is sequentially written to M (31), (32), and (33).

Here, the number of samples included in the period of □ seconds is 1470
As shown in FIG. 4B, these are 735 words of words L0 to L1,4 of the left channel audio signal and words L0 to L7 of the right channel audio signal.
, 4 corresponds to 735 words, and the code corresponds to a total of 1470 words. In this example, data corresponding to this one second period is taken as data for a unit time, and each of the RAMs (31) to (33) has a capacity capable of storing 1470 words.

Thus, 3 RAM (3
1), (32), and (33) are parity P for error correction.
.

Q is added, and it is divided into odd number data and even number data, and parity EP and EQ, parity OP and OQ, and a CRC code for error detection are added to the odd number data and even number data, respectively. Each added odd-numbered data and each even-numbered data is time-axis compressed and read from each RAM.

■Here, the odd data is the odd data word of the left channel and the right channel among the multiple data words for the unit period of one second, and as shown in Figure 4B, the data word of the left channel is LI+ Right channel data word R1, left channel data word L! +Right channel data word R3, for example, a total of 734 data words of left and right channel word pairs with suffixes of 1, 3.5, . . . 733. On the other hand, even data refers to the even data words of the left channel and the right channel among the plurality of data words for this unit period, and FIG.
The left and right channel words L L+ R as shown in
O+L! There are a total of 736 data words of left and right channel word pairs with suffixes of 0.2, 4.6, . . . 734, such as +RZ+....

Parity is added to and read from data written in each RAM as follows.

That is, the control signal generation circuit (10) determines whether to generate parity for data for a unit period and add it to the data, or to generate parity only for odd data among them and add it to the odd data. A control signal RAO for controlling is obtained, and this is transmitted through the switch circuit (27) to the three RAM (
31), (32), and (33). Also, it is possible to generate parity for even data of data for a unit period and add it.
A signal RER for controlling whether to sweep data from the three RAMs (31) to (33) is obtained from the generation circuit (10), and this signal is sent to the three RAMs (31) through the switch circuit (28). ) , (32) , (
33). On the other hand, these three RA
The output data of M (31), (32), and (33) are supplied to the parity addition circuit (37) for the unit period branch data through the switch circuit (29), and the odd data of the data for the unit period is It is also supplied to the parity and CRC code addition circuit (38) for the three RAMs (31), (32),
The output data of (33) is supplied to a parity and CRC code addition circuit (39) for even data using the switch circuit (30).

Then, the output data of the additional circuits (37) and (38) is sent to the three RAMs via the switch circuits (34) and (35).
(31).

(32) and (33) are supplied to the input terminals, and
The output data of the additional circuit (39) is sent to the switch circuit (36)
3 RAMs (31), (32),
(33) is supplied to the input end.

And switch circuits (27), (29) and (3
5) is the switching signal swp from the control signal generation circuit (10).

The three RAMs (
31), (32), and (33), and the switch circuits (28) and (30)
and (36) three RAMs (31) in the order shown in FIG. 4H by the switching signal 5WER from the control signal generating circuit (10).

(32) and (33) are switched.

In this case, three RAMs (31), (32),
(33) is in a readable state when it is not in a write state, and data is output.

Further, the control signal AP (FIG. 4 I) of the additional circuit (37) is obtained from the control signal generation circuit (10), and is supplied to the additional circuit (37) so that it is in the state at its high level. There is. Further, a signal OPC having the opposite polarity to this signal AP is obtained from the control signal generation circuit (10), and this signal OPC is supplied to the additional circuit (38).
During the high level period, this additional circuit (38
) is brought into operation. Furthermore, the signal RPC is shifted in phase by 90'' with respect to the signal AP (Fig. 4J).
) is obtained from the control signal generating circuit (10), and is supplied to the additional circuit (39), and during the high level period, this additional circuit (39) becomes operational.

The signal AP has three RAMs (31), (32)
, (33) is a signal that exactly matches the switching timing for one period, and this signal AP corresponds to the one-second level written in RAMs (31), (32), and (33), respectively. It is something like this.

The signal EPC is a signal whose phase is delayed by 90' with respect to the signal AP, and has periods T, T, T of each □ seconds.

This is a signal that remains at a low level for a period of .

The phase of this signal RPC is synchronized with the rotational phase of the heads (18) and (IB) controlled by the phase servo, and during the period when this signal EP is at a high level, the heads (IA) and (IB) During the period when either of the heads (l^) and (IB) scans the tape (2) and is at a low level, neither the head (l^) nor the head (IB) come into contact with the tape (2).

From the above, for example, in period T, RAM (31)
The unit period bone data written in period T2 and T
, J, parity is generated, added, and read for all data, and parity is generated, added, and read for each of odd and even data.

That is, in period T2, the switch circuits (27), (29), (3
5) is switched to select RAM (31), and this RAM (31) generates and adds parity P and Q to all data, generates and adds parity OP and OQ to odd data, and adds generation to CRC code. mode. That is, in the first half of this period T2, when the signal AP becomes high level, the additional circuit (37) enters the operating state, and the parity P and Q for all the bone data for the unit period R'h M (31) is set to the additional circuit (37). 37) and appended to all the data. The data with the parities P and Q added thereto is returned to a predetermined address of RAM (31) through switch circuits (34) and (35) and written therein. The switch circuit (34) is configured to be switched by a signal similar to the signal AP to the state shown in the figure during its high level period, and to the state opposite to the state shown in the figure during its low level period.

Next, in the latter half of period T2, the signal AP becomes low level, and therefore the signal OPC becomes high level, and the odd data parity and CRC code generation/addition circuit (38)
At the same time, the switch circuit (34) is switched to the state opposite to that shown in the figure, and RAM (3
1) Parity OP and OQ and CRC for only odd data among the unit time data written in
A code is generated and appended to the data,
The data of the added state is written to a predetermined address of RAM (31) through switch circuits (34) and (35).

Next, in period T3, the switch circuits (28), (30), and (36) are switched to the RAM (31) side by the switching signal 5WER, and the RAM (3
1) is a mode for reading or generating and adding parity and CRC codes to even data. and,
Since the signal is the EPC level, the additional circuit (39) is in an inactive state, and the control signal RER causes the RAM (31) to output parity P and Q for all data, parity OP and OQ for odd data, and CRC code. Read out.

After that, when the signal RPC becomes high level, the additional circuit (3
9) becomes operational, even data is read from RAM (31), parity EP and EQ for this and a CRC code are generated in the addition circuit (39), and these are added to the even data. The added data is sent to the RA via the switch circuit (36).
It is written again to the predetermined address of M (31). Since this even number data is at the -level during this period, it is read out.

Similarly, in the period T2, the unit time worth of data written to RAM (32) is generated and added with parity P and Q for all data in the first half of the period T3, and in the second half, the parity is added to the odd data among them. Generation and addition of parity OP, OQ and CRC codes are performed. Then, the next period parity P, Qt op, OQ
and CRC Near-FcD added odd data is read out, and in the middle of this period T+, parity EP, EQ and CRC codes are generated and added to the even data, and parity P, Q, EP, EQ and CRC Even-numbered data to which a code is added is set so that the period is 7°.

Similarly, the data read out to RAM (33) in the period T is set to parity P for all data in the period of parity and CRC code seconds.

Q, parity OP, OQ and CRC for odd data
Reading of odd number data with added code Tee P, Q,
Even data to which EP, EQ, and CRC codes are added is read.

The above RAM (31), (32), (33
) modes are as shown in FIG. 4 C, D, and E. Further, the timing of the read data is as shown in FIG.

As can be seen from this figure, a data group for a unit time, for example, a data group (13 odd number data (1)) is read out respectively, and the odd number data (2) of the data group [2] following the data group (1) is read out. 200) are read out each time after period T.

Similarly, data groups (3), (4), (5), etc.
Odd number data (300) (40) (50) ...
and odd number data (3E), (4E), (5E), . . . are read out after being set aside for -second periods T, T, T, respectively. Then, when viewed as a continuous data flow, each period T,,T,.

becomes. Therefore, the first half of the data in this example is even data, and the second half is odd data, and the even data and odd data tend to be data from data groups for different unit periods.

Here, the read odd number data and even number data have the following configuration. That is, in the process of generating and adding parity and CRC codes, PCM audio data is divided into blocks of 8 data words as shown in FIG. P, Q are added, and when the data word is even data, parity words EP, EQ and a CRC code are added,
On the other hand, when the data word is odd data, parity words OP, OQ and a CRC code are added.

In this case, the eight data words that constitute one block are R
The read addresses of A M (31) to (33) are controlled and interleaved so that the data words are distributed. In this case, the l block is made up of 8 data words, so as shown in the figure, it is made up of 92 blocks made up of even data blocks B0 to odd data blocks B0 to B91.

In this way, the odd number data and even number data read from each RAM (31) to (33) are sent to the recording processor (4).
0) to two rotating heads (18) and (IB). The rotating heads (IA) and (IB) are phase servoed by the signal CT from the control signal generating circuit (10) as described above, and each scans the tape (2) during a period in which the signal RPC is at a low level. It's like that. Therefore, data for a period of seconds as shown in FIG. 4B) are alternately formed and recorded on the tape (2). That is, as shown in FIG. 2, tracks (4A) and (4B) include even number data (OE) of bone data for a certain unit period in the first half of the tracks (4A) and (4B).
(IE) (2E) (3E)... are recorded,
In the second half of the track, odd number data (100) (200) (3
0)(40)... will be recorded. Therefore, data recorded on one track spans two unit sections in terms of time. However, since the amount of data recorded on one track consists of odd number data and even number data, this is exactly equal to the data amount of a unit section bone.

In this case, the PCM written to each RAM during a period of - seconds
Odd number data and even number data become ■, and the time axis of the data is compressed almost to -.

In the recording processor (40), a block synchronization signal 5YNC and block address data ADS are added to one block of data as shown in FIG. 6A. Further, a preamble signal and a postamble signal are added to blocks B0 to B91 recorded as even data and odd data, respectively. The preamble signal is a signal for generating a clock for extracting data during reproduction, and the postamble signal is a signal indicating the end of even or odd data.

In the recording processor (40), further processing is performed in which the PCM data is modulated into a signal suitable for recording, for example, a signal in which the DC component is as small as possible.

Next, reproduction of audio PCM data recorded in this manner will be explained.

This is an example of the reproduction system, and FIG. 6 shows its timing chart.

In the reproduction system shown in FIG. 5, the control signal generating circuit (1) is based on the output of the master clock generating circuit (9).
1) 30 Hz signal SH (Fig. 6B)
), phase servo is applied to the rotating heads (IA) and (1B). A control signal during reproduction obtained from this control signal generation circuit (11), that is, a switching signal for the reproduction output of the head,
Control signals such as write and read signals for this reproduction output are arranged to have a constant phase relationship with the reference signal SH of 3011Z.

The playback output from the heads (IA) and (IB) is output from the amplifier (
Switch circuit (42) through (41A) and (41B)
supplied to This switch circuit (42) is alternately switched between the amplifier (41A) side and the amplifier (41B) side by a 30 Hz signal SH for phase servo. Therefore, from this switch circuit (42), a data string as shown in FIG. 6C is obtained in which the output of the head (1^) and the output of the head (IB) are alternately successive.

The data obtained by this switch circuit (42) is supplied to a digital signal restoration circuit (43), restored to a digital signal, and supplied to an error detection and RAM write control signal generation circuit (44). This error detection and RAM
Data S0 with error detection is obtained from the write control signal generation circuit (44), and three RAM
The write address and write timing signal RW for (51), (52), and (53) are obtained.

The switch circuit (45) includes RAM (51), (
52) Input the error-detected data SD from the circuit (44) into (53), or use the error-corrected data for odd data from the error correction circuit (46). This is a switch to control whether the

First, the import of data S0 will be explained.

The switch circuit (45) is connected to the control signal generation circuit (1
Switching signal W for switching write and correction modes in RAM (51) to (53) from 1)
Switched by O. In other words, this switching signal WO is a 60 Hz signal as shown in FIG. This is a period in which neither of the two heads (IA) and (IB) is in contact with the tape (2), in which no reproduction output is obtained. Then, there is a period P during which this signal WO is at a high level. Then, the switch circuit (45) is in the state shown in the figure during a period P in which the signal WO is at a low level.

In this case, the switch circuits (45) are each switched to a state opposite to that shown in the figure.

Further, the write address and write timing signal RW from the circuit (44) are transmitted to the switch circuit (49) and (
50) via RAM (51), (52),
(53) is supplied to the control terminal. Also, data S for which error detection has been output from the circuit (44) through the switch circuit (45).

is connected to three RAMs (51) through a switch circuit (54).
).

The signals are supplied to input terminals (52) and (53), respectively. And RAM (51)
, (52), and (53) are supplied to the input end of an odd data error correction circuit (46) via a switch circuit (55). The output signal of the odd data error correction circuit (46) is supplied to the other input terminal of the switch circuit (45).

and switch circuits (50), (54) (55)
The three RAMs (51), (52), (53) are generated every □ seconds in the order shown in FIG. 6G by the control signal 5WWO from the control signal generation circuit (11).
) can be switched sequentially.

In this case, three RAMs (51) with signal S40.

The switching timing of (52) and (53) is approximately at the center of the period P8 in which the signal WO is at a high level.

Further, a signal C0 for controlling the correction mode for odd number data is obtained from the control signal generation circuit (11), and this is supplied to the other input terminal of the switch circuit (49) and is passed through the switch circuit (50). 3 RAs
It is supplied to the control terminals of M (51), (52), and (53). Then, the switch circuit (49) receives the signal W
It is switched by O in synchronization with the switch circuit (45).

Therefore, the period P during which the signal WO is at high level is:
The three RAMs (51) to (53) are in the write mode, and during this period P8, the switch circuits (50), (54) and (55) are switched on by the switching signal SWWO.
are RAM (51), RAM (52), and RAM (
53) is switched to select the period TA of □ seconds.
,T.

Po is the second half of period Pw (head tape (2)
(equivalent to the second half of the above scanning period), and this period P. As is clear from FIGS. 6C and 6J, the playback head output is odd data (10).

(2OL(30)... are obtained. Therefore, in this period P0, each RAM (51), (5
2) , (53) has odd number data (10), (200),
(300)... is the write address and timing signal RW from the circuit (44).

is written to a predetermined address by

The period P of seconds is the first half of the period P8 (corresponding to the first half of the scanning period of the head on the tape (2)), and as is clear from FIG. The playback head output is even data (IE).

(2E), (3E), etc. are obtained. therefore,
During this period PE, each RAM (51), (
52), even data (IE) in (53), (2E)
, (3E), etc. are written under the control of the signal RW from the circuit (44).

Each period when the signal WO is at low level T A, T g,
The Tcch circuits (45) and (49) are switched to a state opposite to that shown, so that the corrected data from the correction circuit (46) is transferred to each RAM (51), (5
2) The state will be written to (53). In other words, it becomes an odd data correction mode. Note that this odd data correction circuit (4) is connected to the control signal generation circuit (11).
6) is supplied with the control signal OC. This signal O
C is a signal with the opposite polarity to the signal WO, and during its high level period (this is period P), the correction circuit (46)
is made operational.

Therefore, the switch circuit (50
), (54), and (55) are switched to each RAM (51).

Periods TA and TI during which (52) and (53) are selected, respectively.

During the period P of Tc, each RAM (51), (52), (53) is controlled by the control signal C0.
The odd data read from the correction circuit (46) uses parity OP and OQ to correct the error-detected data, and the corrected data is sent to the switch circuits (45) and (54). The original RAM (
51), (52).

It is returned to (53).

Error correction for even-numbered data written in a period of seconds and error correction for all data are performed as follows.

That is, the control signal CtA for that purpose is transmitted from the control signal generation circuit (11) to the three RAMs (51), (52), (53) through the switch circuit (56).
is supplied to the control terminal. Also 3 RAM (51)
, (52), and (53) are sent through the switch circuit (56) to the even data correction circuit (47).
) and is also supplied to a unit period total data correction circuit (48). The output signal of the even data correction circuit (47) and the output signal of the total data correction circuit (48) are switched by the switch circuit (58), and the output is sent to the three RAMs through the switch circuit (59).
It is supplied to the input ends of (51), (52), and (53). And switch circuits (56), (57
), and (59) are the control signal generation circuit (11
), the three RAMs (51), (52
), (53).

Further, the even number data correction circuit (47) is supplied with the control signal EC (Fig. 6K) from the control signal generation circuit (11).
) is supplied, and this correction circuit (47) is operated during the period when it is at a high level.

Further, the correction circuit (48) is supplied with a signal AC having a polarity opposite to that of the signal EC, and the correction circuit (48) is enabled to operate during the period when the signal AC is at a high level. This signal EC has a period T AIT m,
A signal that is high level in the first half of Tc and low level in the second half. Therefore, the correction circuit (4
7), the correction circuit (48) in the first half of the period 'ra, T, T, and the circuit (58) in the second half of the period T A + T I + T c are switched by a signal in phase with the signal EC, and its high level During a period when the level is low, the state is switched to the state shown in the figure, and during a period when the level is low, the state is switched to the state opposite to the state shown in the figure.

Therefore, as is clear from FIG. 6, during the period Tm in which RAM (51) is selected by the signal S, the circuit (11) is
Even data read from the RAM (51) by a control signal CEA from ) is supplied to an even data correction circuit (47) and a total data correction circuit (48) through a switch circuit (57). During this first half period, the even data correction circuit (47) becomes operational, so the parity EP and EQ for the even data are used to perform error correction on the even data, and the corrected data is Switch circuit (5 days)
and (59) through RAM (51), (52)
, (53) is written to the original predetermined address.

Then, in the second half of this period T, all the data correction circuits (48) become operational, so the parity P,
Q is used to correct data errors for all data corresponding to a unit period.

The error-corrected data is then written to a predetermined address of RAM (51) through switch circuits (58) and (59).

Similarly, in period Tc, for even data among the data written in RAM (52),
Correction using parity EP and EQ is performed, and correction of all data using parity P and Q is performed in circuits (47) and (48), respectively, and RAM
It returns to the original address of (52).

Furthermore, during the period TA, parity EP and EQ are used to correct even data written in RAM (53), and parity P and Q are applied to all data.
Corrections are made in circuits (47) and (48), respectively, and the corrected data is stored in RAM (
53).

From the above, in the period TA, T, ,T, RAM
The data written to (51), (52), and (53), respectively, is stored in RAM (51) (52) after a period of - seconds has elapsed after the respective write period.
The data written in (53) is a PCM in which all the data that can be corrected within the error correction capability has been corrected.
The data will be written.

The data written and corrected in this way is read out in a period of one second after one second has elapsed from the end of writing.

That is, the read control signal RR from the control signal generation circuit (11) is sent to RA through the switch circuit (60).
It is supplied to the control terminals of M (51), (52), and (53). Also, R A M (51), (52
), (53) are supplied to the modification circuit (62) through the switch circuit (6I). These switch circuits (60) and (61) are operated by the switching signal SWR from the control signal generating circuit (11).
The three RAMs are switched in the order shown in FIG. That is, even data and odd data written in RAM (51) during period TA are read out during period Tc, and RAM (52) is written in period T8.
) is read out in period TA, and data written in RAM (53) in period Tc is read out in period T8. In this case, even-numbered and odd-numbered data for each unit interval are read out alternately through address processing, and the data for that unit time, which is combined with the original time series, is expanded to the original time axis of □ seconds. The data is read out as shown in Figure 6. The thus read signal is supplied to a correction circuit (62) through a switch circuit (61), and error correction is performed on the data that could not be completely corrected. Error correction circuit (
The output of 62) is supplied to a D/A converter (63). Each sample of the PCM signal converted back to an analog signal in the D/A converter (63) is sent to the switch circuit (64).
) is a signal with the same frequency as the signal SW during recording (44,1k
Hz), the amplifier (6
5L), the left channel audio signal SL is
The right channel audio signal SR is taken out to output terminals (66L) and (66R) through an amplifier (65R), respectively.

According to the apparatus of the present invention as described above, audio data for a unit time corresponding to one track is divided into even-numbered data and odd-numbered data and recorded over two tracks. Therefore, data for a unit time of the PCM signal is spread over two tracks.

According to the present invention, even if the data for l trough 0 is missing and cannot be obtained during playback, if the tracks before and after it are being played, the even or odd number of data for the missing segment is Since the data of one of the two tracks is always recorded on the previous or next track, there is no possibility that the data will be lost even though it is number two in terms of information. Therefore, for example, in the error correction circuit (62), the missing data in this □ is used to interpolate the data in between, that is, the even-numbered or odd-numbered data is used to calculate the odd-numbered or even-numbered data by means of average value interpolation, etc. Since data words can be interpolated, data with an extremely good S/N ratio can be obtained as reproduced data after signal processing. Moreover, there is an effect that the configuration for this purpose can be made very easily.

Also, when you start recording continuously from a previously recorded part, only the even or odd numbered data of the old and new data will remain at the joint. It is possible to perform interpolation processing using the same method as the error correction described above for signal processing at joints, and it is possible to realize highly effective methods such as being able to smoothly connect signal joints. There are also advantages.

Furthermore, in this invention, even (odd) data is recorded in the first half of one track, and odd (even) data is recorded in the second half. Therefore, the interleave length is the conventional □, It will be divided into two parts. However, as is clear from Figures 4 and 6, the time required for error correction is very long, and the correction process can be performed for each even or odd data as well as for the entire data. It has the effect of greatly increasing your abilities.

Furthermore, as mentioned above, the tape is wound around the guide drum by making the corners smaller and the number of rotating heads N being smaller.
) is not in contact with the tape (2), and by using this period, it is possible to easily add parity and CRC code name to the data of each channel during recording, and during playback. Since errors can be corrected,
As in the conventional case where the corners of the tape are wound and the distance between the corners of the head is set equal to the interval between the corners, complicated signals are created in order to create time margins for adding redundant data during recording and for error correction during playback. The advantage is that there is no need for processing or the use of large delay buffers.

However, according to the present invention, error correction can take a very long time for correction of all data, correction of even number data, and correction of odd number data. This is not corrected, and head installation like this is not limited to the case where the corner spacing and tape wrapping are made smaller, and the head installation is not limited to cases where the corner spacing and tape wrapping are the same when the corner spacing is the same. Also, a sufficient correction time can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining an example of a rotary head device used in this invention, FIG. 2 is a diagram showing its recording track pattern, FIG. 3 is a system diagram of an example of this invention device, and FIG. 4 is its diagram. FIG. 5 is a diagram showing a timing chart for explanation, FIG. 5 is a system diagram of an example of a reproduction system, and FIG. 6 is a diagram showing a timing chart for explanation. (18) and (1B) are rotating heads, (2) is a magnetic tape, (3) is a guide drum, (31), (32),
(33) is RAM, (37). (3B) and (39) are parity or CRC addition circuits.

Claims (1)

[Claims] 1. In an apparatus for recording PCM data by forming diagonal tracks on a tape-shaped recording medium using a rotating head, the data is divided into even-numbered data and odd-numbered data every unit time of the PCM data. The PCM data recording apparatus records the even-numbered data and odd-numbered data on the track at positions separated from each other in the tape width direction. 2. A diagonal track is formed by the rotating head, and P
In a tape-shaped recording medium on which CM data is recorded,
A tape-shaped recording medium in which even-numbered data and odd-numbered data of PCM data divided into units of time are recorded at positions separated from each other in the tape width direction on the track. 3. In an apparatus for reproducing recorded PCM data by forming diagonal tracks on a tape-shaped recording medium by a rotating head, even-numbered PCM data recorded at positions apart from each other in the tape width direction on the track A PCM data reproducing device which reproduces the data and the odd numbered data using a rotary head, and reproduces the recorded PCM data from the reproduced even numbered data and the odd numbered data.