JPH01314487A - Treatment of video signal - Google Patents

Abstract

PURPOSE:To remove the influence of crosstalk by sampling the specific frequency component of a reference signal recorded on a recording medium so that its frequencies in adjacent tracks can be different with each other and fetching the reference signal from a reproduced video signal. CONSTITUTION:A monostable-multivibrator 68 obtains timing from its vertical synchronizing signal and outputs a gate pulse to be 'H' in a period from the preceding line of a line in which a character broadcasting signal exists to another line in which the last character broadcasting signal exists in every field. A reference signal sampling gate 70 turns on when the gate pulse from an AND circuit 69 is 'H', and only the reference signal is fetched from the output of an LPF 59 and inputted to BPFs 71 and 72 respectively. In the BPF 71, a 1/10fsc as the crosstalk can be sufficiently attenuated in sampling a 1/5fsc, and in the BPF 72, the 1/5fsc as the crosstalk can be sufficiently attenuated in sampling the 1/10fsc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal processing method that enables good decoding of teletext signals.

[Conventional technology]

2. Description of the Related Art Conventionally, there is a video signal processing system, which has been adopted particularly for home videos, in which a luminance signal and a color signal that constitute a video signal are processed by separate signal processing systems.

In this method, in order to save recording bandwidth, the recording luminance signal processing system performs FM modulation on the recording luminance signal, and the recording color signal processing system modulates the recording color signal at a frequency lower than the FM band.
Low-frequency conversion (low-frequency color conversion) is performed to around 0kHz, and this low-frequency conversion color signal and the FM modulated wave of the recording luminance signal are superimposed and recorded, and during reproduction, the reproduction luminance signal processing system
The M luminance signal is demodulated, and the reproduced luminance signal is converted to a low frequency converted color signal of 3.58 MIIz (color burst (hereinafter referred to as
It's called CB. A typical example is a home video recording and reproducing system using a low-frequency conversion color method, in which the frequency of the signal is converted to () signal frequency) and the two are synthesized to obtain the above-mentioned reproduced composite video signal.

Incidentally, in recent years, teletext broadcasting has been started that utilizes the horizontal scanning period, which is part of the vertical retrace period of the video signal and on which the carrier color signal is not superimposed.

In this teletext broadcast, the broadcasting station sends out a video signal by superimposing a teletext signal representing codes corresponding to predetermined characters, figures, sounds, etc. during the horizontal scanning period, and the receiver side converts the video signal into a video signal. It is possible to extract the teletext signal, decode the code it represents, display characters, graphics, sounds, etc. corresponding to the code on the screen, and obtain various information from them.

The development of video signal recording and reproducing devices such as video tape recorders has been remarkable, and some products have been commercialized with a horizontal resolution of 400 lines or more (luminance signal band of 5 MHz or more). For example, if the signal is from Japan, its spectrum distribution is such that it can be sufficiently transmitted in terms of band, and therefore, technological development is underway regarding the application of teletext signals to VTR reproduction.

FIG. 6 shows the circuit configuration of a conventional teletext signal decoder.

In this figure, first, the frequency of the sampling clock for extracting character signal data is, for example, 5.7272.
7 (hereinafter abbreviated as 5.72 MHz) MHz, and this clock frequency is a color burst signal (hereinafter referred to as CB signal) in a video signal.

), the first and second PLL circuits 1.2
Created by That is, the reproduced composite video signal inputted from the terminal 3 is passed through a 3.58 MIIz bandpass filter 4 and a burst gate 5 to extract a CB signal. This CB signal is sent to the first PLL circuit 1.
Add to. In this first PLL circuit 1, 3.58Ml
VXO7 using 1z crystal oscillator 6 and phase detector (
3, 5 synchronized with the phase of the CB signal by P/D) 8.
A signal of 8 Mtlz is created and sent to the second PLL circuit 2.

The second PLL circuit 2 has a clock frequency of 5.72M.
Using the relationship that Hz is 815 times the color subcarrier frequency 3.579 MHz and 364 times the horizontal scanning frequency fH, VXOlo using a 5.72 MIIz crystal oscillator 9 and a 1/8 counter 11, a phase detector (P/D) 12, and a 115 counter 13 that frequency-divides the output of the first PLL circuit, forming a sampling clock having a frequency of 5.72 MHz.

This sampling clock is input to a frame pulse flywheel circuit 16 as a framing code detection circuit via a delay line 15 controlled by the sub CPU 14.

On the other hand, the reproduced composite video signal is input to a synchronization signal separation circuit 17, where the synchronization signal is separated. This synchronization signal is inputted to the control terminal of the burst gate 5 described above via a pulse delay circuit (not shown), inputted to the shift register 18, and further inputted to the vertical synchronization signal separation circuit 19. The vertical synchronization signal separation circuit 1
At 9, only the vertical synchronization signal is taken out and input to a pulse generator 20 including a monostable multi-by-break. This pulse generator 20 generates a pulse for a period including the line on which the teletext signal is superimposed from the synchronization signal from the synchronization signal separation circuit 17 and the vertical synchronization signal from one vertical synchronization signal separation circuit. The pulse is input to a fuse blowing type ROM 21 which will be described later. This pulse is generated only during the period in which the framing code is included from the horizontal synchronizing signal.

Separately, character data is extracted from the video signal by an AGC/data slice circuit 22. The character data is stored in the shift register 18 in accordance with the sampling clock applied via the delay line 15 mentioned above. The data stored in the fuse blowing type ROM 21 is read out in accordance with the address designated by the output of the shift register 18 and in response to the output pulse from the pulse generator 20. In other words, only address values that match the framing code pattern are stored in the ROM21.
1'' is stored in advance, and a pulse is output only when the address specified by the output of the shift register 18 matches the framing code in the ROM 21.
21 outputs a framing code detection pulse to the frame pulse flywheel circuit 16. The frame pulse flywheel circuit 16 outputs a correct framing pulse depending on the presence or absence of frame synchronization.

Further, in order to correct errors in the character data extracted by the AGC/data slice circuit 23, an error correction circuit 22 is provided at the next stage of the shift register 18. In order to perform error correction, this error correction circuit 22 receives a synchronization signal from the synchronization signal separation circuit 17, a vertical synchronization signal from the vertical synchronization signal separation circuit 19, and a delay line 15.
The sampling clock from is input. Then, the delay amount of the delay line 15 is changed by the sub CPU 14 so as to minimize the error amount, thereby realizing the minimum error amount. The error-corrected data is stored in buffer memory 24.

In this way, in the conventional decoder shown in FIG.
The 3.58 MHz VXO7 of the PLL circuit 1 is operated so as to lock to the CB signal extracted from the reproduced video signal, and then this 3. '5.72MHz, which is the sampling clock, is created using VXOlo so that it is locked to 58MHz. The phase of the above clock CK is delay line 1.
The delay amount of the delay line 15 is adjusted by moving the delay line 15 so that the data can pass through most easily. More specifically, the delay amount of the delay line 15 is adjusted so that the error in the error correction circuit 22 is minimized. ) 14.

The decoder described above has a problem in that it is difficult to decode character signals obtained by VTR playback for the following reasons. That is, the CB signal and the luminance signal (
Looking at the relationship with
While the frequency is converted to 58 MHz in the color signal processing system, the signal that has passed through the luminance signal processing system still has jitter and is not locked to the CB signal.

Therefore, in the signal processing method using the decoder, as mentioned above, the 5.72 MHz sampling clock is created to lock to the CB signal with such jitter compensated, whereas character information is created to follow the jitter. It's moving.

Therefore, in the character information, the optimum locking phase is completely different for each field.

The phase adjustment is performed by the delay line 15, but the phase adjustment by the delay line 15 does not have a fast response that can be adjusted within the clock run-in range of each data bucket section DP. Therefore, if the optimum clock phase differs for each field, it is assumed that the broadcast is not teletext. For this reason, as described above, it is difficult for the conventional decoder shown in FIG. 6 to decode a teletext signal from a reproduced video signal obtained by VTR reproduction.

Therefore, in the past, a signal that would serve as a reference for teletext signal decoding was added in a way that did not adversely affect other video signal components, such as by using an empty period in the vertical blanking period of the video signal. It is thought that it will.

This method improves the jitter followability of the reference clock for sampling clock generation by making the reference signal as high in frequency as possible or making its continuous period as long as possible to facilitate synchronization. It would be very advantageous if this method could be adopted.

[Problem to be solved by the invention]

However, depending on the frequency of this reference signal, it may not be possible to fully expect an azimuth effect when reading it with a head, and in such cases, the reference signal may not be able to be extracted in good condition due to crosstalk. As a result, there is a problem in that a stable sampling clock cannot be obtained.

The present invention has been made in view of the above circumstances, and its purpose is to improve the quality of the reference signal even if the reference signal has a frequency at which no azimuth effect can be expected when read by the head. It is an object of the present invention to provide a video signal processing method that enables reproduction without deteriorating as much as possible.

[Means to solve the problem]

In the video signal processing method of the present invention, the sampling clock for teletext signal decoding is applied during a period other than the period in which the color burst signal of at least one line is superimposed in the vertical blanking period of the recorded video signal. A reference signal used as a reference for generation is made to have different frequencies between adjacent tracks, and is frequency-multiplexed with the FM luminance signal of the recorded video signal and recorded on a recording medium, and from the reproduced video signal from the recording medium. The present invention is characterized in that the reference position and number recorded on each track are extracted by extracting a specific frequency component.

[For production]

According to the video signal processing method of the present invention, a reference signal recorded on a recording medium with different frequencies between adjacent tracks is extracted from a reproduced video signal by extracting only a specific frequency component. Therefore, even if there is crosstalk at the stage of reading by the head, other frequency components can be removed at the stage of extraction, so the influence of that crosstalk can be eliminated.

Furthermore, since the reference signal is frequency-multiplexed with the FM luminance signal and recorded on the recording medium, it does not adversely affect the processing of the luminance signal.

(Example) Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a video signal recording system according to an embodiment of the method of the present invention, FIG. 2 is a block diagram of a video signal reproducing system according to the same embodiment, and FIG. 3 is a phase correction circuit shown in FIG. 2. 4 is a block diagram showing details of the variable delay line shown in FIG. 3, and FIG. 5 is a time chart for explaining the operation of the recording system shown in FIG. 1.

In FIG. 1, 25 is a luminance signal/color signal separation circuit (hereinafter referred to as YC separation circuit), and the video signal shown in FIG. 5(a) from a broadcasting station or other video cassette player is It is input to the YC separation circuit 25. YC
The separation circuit 25 separates the video signal into a luminance signal and a color signal using a comb filter or the like.

26 is a luminance signal processing circuit, and the luminance signal from the YC separation circuit 25 is input to this luminance signal processing circuit 26. The luminance signal processing circuit 26 is the pre-emphasis circuit 2
7 and an FM modulation circuit 28, the luminance signal is subjected to pre-emphasis by a pre-emphasis circuit 27, and its output is frequency-modulated to become an FM luminance signal.

29 is a synchronization signal separation circuit, 30 is a half upper killer circuit,
31 is a gate pulse generation circuit. The same video signal that is input to the YC separation circuit 25 is input to the two synchronization signal separation circuits, and the synchronization signal separation circuit 29 extracts the synchronization signal from the video signal. The upper half killer circuit 30 extracts a horizontal synchronization signal from the synchronization signal from the synchronization signal separation circuit 29. The gate pulse 31 is timed by the horizontal synchronizing signal, and generates and outputs a gate pulse that becomes "H" only during the period when the color burst signal in the video signal is superimposed.

32 is a color signal processing circuit, and this color signal processing circuit 32 includes an automatic frequency control circuit (hereinafter referred to as AFC direction) 33, an automatic phase control circuit (hereinafter referred to as AFC direction) 34, and a sub-converter 35. Main converter 3
6 and a low pass filter (hereinafter referred to as LPF) 37.

This AFC circuit 33 generates and outputs a 4OfH low frequency converted color subcarrier signal based on the horizontal synchronizing signal from the half upper killer circuit 30.

The APC circuit 34 includes a burst gate 38 and a phase comparator circuit 3.
9 and the operating center frequency is 3.579545MHz (hereinafter referred to as
It's called tsa. ) voltage controlled oscillator (hereinafter referred to as VXO) 40.

The color signal from the YC separation circuit 25 and the gate pulse from the gate pulse generation circuit 31 are input to the burst gate 38, and the burst gate 38 is controlled to open and close by the gate pulse, and only the color burst signal is extracted from the color signal. It is now possible to The phase comparator 39 outputs the output signal of the VXO 40 and the CB from the burst gate 38.
A phase difference detection signal with a voltage value corresponding to the phase difference with the signal is output. This phase difference detection signal is input to the VXO 40.

Therefore, this VXO 40 outputs an fsc color subcarrier signal locked to the CB signal.

The sub-converter 35 receives the low frequency conversion color signal subcarrier signal from the AFC circuit 33 and the fsc signal from the APC circuit 34.
A color subcarrier signal is input, and a signal of 40fH-f'sc is output from the subconverter 35.

The main converter 36 receives the color signal from the YC separation circuit 25, that is, the fsc±df (variation amount) signal, and the 40fH-fsc signal from the sub-converter 35.
A low frequency converted color signal is output.

This low frequency converted color signal is passed through an LPF 37 to remove noise components and is sent out.

Sate, fsc from VXO40 in APC circuit 34
The output signal is also used as a reference signal for generating a sampling clock for extracting the teletext signal from the video signal in decoding the teletext signal, and 41 is a 115 frequency divider, and 42 is an LPF.

43 is a 1/10 frequency divider, 44 is an LPF, and 115
This VXO40 is used for frequency divider 41 and 1/10 frequency divider 42.
The fsc reference signals from the respective terminals are inputted. 17
A 115 fsc standard signal is output from the 5 frequency divider 41,
The high frequency band is cut by the LPF 42 and a sine wave is generated. 1/10fsc from 1/10 frequency divider 43
The reference signal is output from the reference column, and its high frequency is cut off by the LPF 44 to be generated as a sine wave.

45 is a vertical synchronizing signal separation circuit, and 46 is a monomulti. The vertical synchronization signal separation circuit 45 extracts a vertical synchronization signal from the output signal of the synchronization signal separation circuit 29, and the monomulti 46 takes timing based on the vertical synchronization signal.
A period from the line one line before the teletext signal in each field to the last line where the teletext signal is located, that is, the period from line 13 to line 21;
A gate pulse as shown in FIG. 5(c) which becomes "H" during the period from the 226th line to the 284th line is output.

The inverting amplifier 47 inverts the output of the gate pulse generating circuit 31, so that the output from the inverting amplifier 47 becomes "L" only during the period when the CB signal is superimposed on the video signal, as shown in FIG. 5(b). Output the gate pulse as shown.

The inverting amplifier 48 includes a drum flip-flop (hereinafter referred to as D
It's called FF. ) is being input. This DFF indicates the rotational phase of the head drum in a two-head helical scan VTR, and indicates "L°~" when recording on a track corresponding to an odd field, and "H" when recording on a track corresponding to an even field. This is what is output. Therefore, the output of the inverting amplifier 48 becomes "H" when recording to a track corresponding to an odd field, and "L" when recording to a track corresponding to an even field.
” becomes.

The outputs of the monomulti 46, the inverting amplifier 47, and the inverting amplifier 48 are input to the AND circuit 49. During this period, "H" is output when recording on odd field tracks.

The outputs of the monomulti 46, the inverting amplifier 47, and the inverting amplifier 48 are input to the AND circuit 50. During this period, "H" is output when recording on an even field track.

Therefore, gate pulses as shown in FIG. 5(d) are outputted from these AND circuits 49 and 50, respectively.

52 is a reference signal insertion gate, and 53 is a mixer. This mixer 53 is located before the recording amplifier 54 and the head 55 and combines the FM luminance signal and the low frequency conversion color signal. , and the 1/10 fsc reference signal from the LPF 44 is input to the mixer 53 via the reference signal insertion gate 52.

The reference signal insertion gate 51 receives the output of the AND circuit 49 “H”.
It is turned on when . Therefore, a reference signal as shown in FIG. 5(e) is input to the mixer 53, and as shown in FIG. The color burst signal in the erasing period is superimposed on a period other than the superimposed period, and is recorded on the recording medium. Similarly, the 1/10 fse reference signal is superimposed on the even field of the reference image signal in a period other than the period in which the color burst signal is superimposed in the vertical blanking period, and is recorded on the recording medium. In addition, Figure 5 ([
) does not correspond to any of the outputs of the circuit elements in Figure 1, and is intended to clearly indicate the reference signal insertion period in relation to other signal components of the video signal. be.

Next, in FIG. 2, the video signal read from the recording medium by the head 56 is input to the luminance signal processing circuit 58, and is also input to the LPF 59 and the reference signal removal gate 60.
The signal is input to the color signal processing circuit 61 via. In the luminance signal processing circuit 58, only the FM luminance signal is extracted from the reproduced video signal, and this is FM demodulated. Only the low-frequency converted color signal is extracted by the LPF 59 and the reference signal removal gate 60 and input to the color signal processing circuit 61. In this color signal processing circuit 61, the low-frequency converted color signal has its subcarrier acid component extracted. Returned to fsc.

These luminance signal processing circuit 58 and color signal processing circuit 6
The outputs of 1 are combined by a mixer 62 and made into a reproduced video signal.

63 is a synchronizing signal separation circuit, and 64 is a half H killer circuit. The sync signal separation circuit 63 extracts a sync signal from the reproduced video signal from the mixer 62, and the half H killer circuit 64 extracts a horizontal sync signal from the sync signal. This horizontal synchronization signal is transmitted to the color signal processing circuit 6.
1 as an AFC signal.

65 is a gate pulse generation circuit. This gate pulse generation circuit 65 generates and outputs a gate pulse that becomes "H" during the period when the color burst signal of the video signal is superimposed from the horizontal synchronization signal from the half H killer circuit 64. is input to the color signal processing circuit 61 as a signal for extracting color burst signals.

67 is a vertical synchronization signal detection circuit, and 68 is a monomulti. The vertical synchronization signal detection circuit 67 extracts only the vertical synchronization signal from the synchronization signal from the synchronization signal separation circuit 63.

The monomulti 68 takes timing based on this vertical synchronization signal and performs the period from the line immediately before the teletext signal in each field to the last line in which the teletext signal is located, that is, from line 13 to the last line where the teletext signal is located. A gate pulse that becomes "H" is output during the period up to the 21st line and the period from the 226th line to the 284th line. This gate pulse corresponds to the output of the monomulti 46 in the recording system.

The gate pulse from the gate pulse generation circuit 65 is inputted to the AND circuit 69 via the inverting amplifier 66 as corresponding to the output of the inverting amplifier 47 in the recording system, and the gate pulse from the monomulti 68 is inputted. It has been entered. Therefore, this AND circuit 69 outputs a gate pulse that becomes "H" during a period other than the period in which the color burst signal is superimposed in the vertical blanking period of the video signal.This output is output from the AND circuit in the recording system. It corresponds to the output of four circuits or the AND circuit 50.

70 is a reference signal extraction gate, 71 and 72 are band pass filters (hereinafter referred to as BPF), and 73 is a field-specific switching gate. BPF71.72 has LPF5
9 is input through a reference signal extraction gate 70. This reference signal extraction gate 70 is connected to the AND circuit 6
9 is turned on when the gate pulse is H2, so that only the reference signal is taken out from the output of the LPF 59 and input to the BPFs 71 and 72, respectively. BPF71 allows 115 fsc to pass through but does not allow 1/10 fsc to pass through.
72 allows 1/10 fsc to pass but does not allow 115 fsc to pass. Field switching gate 73
is the DF on the BPF71 side when the DFF output is 'H'.
When the output of F is "L", it is switched to the BPF 72 side. This field, - field switching gate 7
3, a 1154sc reference signal is output when odd fields of a video signal are reproduced, and a 1/10fsc reference signal is output when the same even fields are reproduced. In this way, by using BPF71.72, the specific frequency component 1 is extracted from the video signal.
15 fsc and 1/10 fsc are respectively taken out. Therefore, when extracting 115fsc with BPF71, 1/10fsc, which is crosstalk, can be sufficiently attenuated, and with BPF72, 1/10fsc can be sufficiently attenuated.
115fS which is crosstalk when extracting fsc
This means that C can be sufficiently attenuated.

74 is a sampling clock generation circuit.

This sampling clock generation circuit 74 includes a phase comparison circuit 76, an LPF 77, a gate 78, a vCO 79, and a 1/1
It has a 6 frequency divider 80, a 178 frequency divider 81, a switching gate 82 for each field, and a capacitor 83, and is basically a PLL.
It is of composition. In other words, the output of VCO79 is 1/
The frequency is divided by a 16 frequency divider 80 and a 1/8 frequency divider 81,
The field-specific switching gate 82 switches to the 1/8 frequency divider 81 side when the output of the DFF is "H", and to the 1/16 frequency divider 82 side when the output of the DFF is "L". 815fsc is input to the phase comparator circuit 76, and as a result, the output of the VCO 79 is 815fsc. AND circuit 6
The gate pulse from 9 is inverted by an inverting amplifier 75, and this is input as a control signal to the gate 78.

Therefore, the gate 78 is turned off during a period in which the reference signal is not superimposed on the video signal, and the voltage value immediately before this is held by the capacitor 83 located in parallel on the output end side. In this way, the VCO
79 outputs a stable sampling clock.

84 is a phase correction circuit, and this phase correction circuit 84, as shown in FIG.
It includes a multiplier circuit 88, a phase comparator 89, an LPF 90, a hold circuit 91, and a variable delay line 93.

The counter 84 counts up at the rise of the horizontal synchronization signal from the half-H killer circuit 64 and is reset at the rise of the vertical synchronization signal from the vertical synchronization signal detection circuit 67. Based on the output of the counter 84, the sampling pulse generation circuit 85 generates and outputs a gate pulse that becomes "H" only during the period when the teletext signal is superimposed on the video signal. The teletext signal extraction gate 86 is turned on when the gate pulse is "Ho" and extracts the teletext signal by passing the reproduced video signal only during that period.The teletext signal is passed through the BPF 87. te 8/10
Only the fsc component, that is, the clock run-in, is extracted, and this is further increased to 815 fsc by the doubling circuit 88.

The phase comparator circuit 89 detects a phase difference between the sampling clock from the VCO 79 and the 815 output from the doubler circuit 88, and a voltage value signal corresponding to the phase difference is generated from the LPF 90.

The output of the LPF 90 and the output of the delay circuit 92 are input to the hold circuit 91 . The delay circuit 92 delays the gate pulse from the sampling pulse generation circuit 85,
This is caused to rise near the end of the teletext signal extraction position, and upon receiving this, the hold circuit 91 holds the voltage value from the LPF 90. In other words, this hold circuit 91 is designed to hold the phase comparison output for portions other than the clock run-in of the teletext signal.

The variable delay line 93 is connected to an inductor 94- as shown in FIG.
1 to 94-6 and varicaps 95-1 to 95-6, which constitute an LC delay line.
Its capacity is changed by the output of the circuit, and thereby the amount of delay can be changed. Therefore, the output of vCO 79 is delayed and controlled according to the phase of the clock run-in.

For example, in the case of the decoder shown in FIG. 6, the sampling clock whose phase has been controlled by the variable delay line 93 is input directly to the frame pulse flywheel circuit 16, shift register 18, and error correction circuit 22, and is used to generate the teletext signal. Can be used for decoding.

〔Effect of the invention〕

As explained above, according to the present invention, a reference signal recorded on a recording medium with different frequencies between adjacent tracks is extracted from a reproduced video signal by extracting only a specific frequency component. Therefore, even if there is crosstalk at the reading stage by the head, other frequency components can be removed at the sampling stage, so the influence of this crosstalk can be eliminated, and the reference signal is Even if the head has a frequency at which no azimuth effect can be expected when reading,
Since this reference signal can be reproduced without deteriorating its quality as much as possible, the reproduced teletext signal can be decoded satisfactorily.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a recording system in an embodiment of the method of the present invention, FIG. 2 is a block diagram of a reproduction system in the same embodiment, and FIG. 3 is a detailed diagram of a phase correction circuit in the reproduction system shown in FIG. Figure 4 is a detailed diagram of the variable delay line in the phase correction circuit shown in Figure 3, Figure 5 is an output waveform diagram of the main part of the recording system shown in Figure 1, and Figure 6 is a block of the teletext signal decoder. It is a diagram. 25... YC separation circuit, 26... Recording system luminance signal processing circuit, 29.63... Synchronization signal separation circuit, 30.6
4...Half H killer circuit, 31.65...Gate pulse generation circuit, 32...Recording system color signal processing circuit, 41...175 frequency divider, 42,44°59...L
PF, 43...1/10 frequency divider, 44...LPF,
45.67... Vertical synchronization signal detection circuit, 46.68.
...Mono multi, 47.48.66...Inverting amplifier,
49.50.69...AND circuit, 51.52.70
... Reference signal extraction gate, 53.62 ... Mixer, 54 ... Recording amplifier, 55.56 ... Head, 5
7...Reproduction amplifier, 58...Reproduction system luminance signal processing circuit, 60...Reference signal removal gate, 61...Reproduction system color signal processing circuit, 71.72...BPF, 7B
. . . Field-specific switching gate, 74 . . . Sampling clock generation circuit.

Claims (1)

[Claims] 1. A period other than the period in which the color burst signal of at least one line is superimposed in the vertical blanking period of the recorded video signal is used as a reference for generating the sampling clock for decoding the teletext signal. The reference signal is made to have different frequencies between adjacent tracks, is frequency-multiplexed with the FM luminance signal of the recorded video signal, and is recorded on a recording medium, and a specific frequency component is extracted from the reproduced video signal from the recording medium. A video signal processing method comprising: extracting a reference signal recorded on each track.