JPH01316970A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

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Publication number
JPH01316970A
JPH01316970A JP63146967A JP14696788A JPH01316970A JP H01316970 A JPH01316970 A JP H01316970A JP 63146967 A JP63146967 A JP 63146967A JP 14696788 A JP14696788 A JP 14696788A JP H01316970 A JPH01316970 A JP H01316970A
Authority
JP
Japan
Prior art keywords
reference voltage
pin scan
circuits
scan circuits
pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63146967A
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Japanese (ja)
Other versions
JP2809278B2 (en
Inventor
Hiroyuki Kadoi
角井　広幸
Mitsuaki Natsume
夏目　光章
Eiji Sugiyama
英治 杉山
Yasuhiko Tando
丹藤　安彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
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Fujitsu Ltd
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Filing date
Publication date
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Priority to JP63146967A priority Critical patent/JP2809278B2/en
Publication of JPH01316970A publication Critical patent/JPH01316970A/en
Application granted granted Critical
Publication of JP2809278B2 publication Critical patent/JP2809278B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To make an error of a reference voltage, which is supplied to the whole pin scan circuits, small by a method wherein reference voltage feeders are provided extending from a reference voltage source in two or more directions to supply the reference voltage to two or more pin scan circuits respectively. CONSTITUTION:Reference voltage feeder 221 and 222 are extended from a reference voltage source 21 in two or more directions to supply a reference voltage to pin scan circuits 201-20n which total 2n in number, where the circuits 201 and 202 amount to (n) respectively. Here, provided that the resistance value of the feeder 221 and 222 corresponding to the space between the adjacent pin scan circuits and the current flowing through each pin scan circuit are represented by (r) and (i) respectively, a voltage drop VD2 at terminals 221a and 222a the most distant from the voltage source 21 is expressed by a formula I. Then, the error of the reference voltage supplied to the circuits 201 and 202n is made small.

Description

【発明の詳細な説明】 （ＩＩ！要〕 ピンスキャン回路を内蔵する半導体集積装置に関し、 全てのピンスキャン回路に供給される基準電圧の異差を
小さくすることを目的とし、 半導体チップの複数の外部端子夫々に対応して該複数の
外部端子夫々のレベルを基準電圧源よりの基準レベルと
比較し、比較結果を専用の外部端子から出力する複数の
ピンスキャン回路を内蔵する半導体集積装置において、
該基準電圧源より複数方向に延在して該複数のピンスキ
ャン回路夫々に基準電圧を供給する基準電圧供給線を有
し構成する。[Detailed Description of the Invention] (II! Required) Regarding a semiconductor integrated device incorporating a pin scan circuit, the purpose of this invention is to reduce differences in reference voltages supplied to all pin scan circuits, and to In a semiconductor integrated device that includes a plurality of pin scan circuits that compare the level of each of the plurality of external terminals with a reference level from a reference voltage source corresponding to each external terminal, and output the comparison result from a dedicated external terminal,
The reference voltage supply line extends in a plurality of directions from the reference voltage source and supplies a reference voltage to each of the plurality of pin scan circuits.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体集積装置に関し、ピンスキャン回路を内
蔵する半導体集積装置に関する。The present invention relates to a semiconductor integrated device, and more particularly, to a semiconductor integrated device incorporating a pin scan circuit.

近年、プリント基板等における半導体集積装置の実装密
度が高くなり、各集積装置間の間隔が狭くなって、実装
されている各集積装置の全てのリード端子にテスターの
プローブを当接させることが困烈となっている。In recent years, the mounting density of semiconductor integrated devices on printed circuit boards has increased, and the spacing between each integrated device has become narrower, making it difficult to contact the tester's probe with all the lead terminals of each integrated device mounted. It has become intense.

このため、集積装置の各リード端子レベルを基準レベル
と比較してその比較結果を専用のリード端子から出力す
るピンスキャン回路を集積回路に内蔵させ、上記専用の
リード端子をプリント基板のプリント配線によってプリ
ント基板上の所定位置に設けたテスト用端子に接続し、
テスト用端子にテスターのプローブを当接させる構成が
開発されている。For this reason, a pin scan circuit that compares the level of each lead terminal of the integrated device with a reference level and outputs the comparison result from a dedicated lead terminal is built into the integrated circuit. Connect to the test terminal provided at the specified position on the printed circuit board,
A configuration has been developed in which a tester probe is brought into contact with a test terminal.

（従来の技術） ピンスキャン回路はリード端子毎に設けられ第７図に示
す如き構成である。同図中、端子１０はリード端子に接
続され、端子１１に基準電圧が供給され、リード端子電
圧はコンパレータ１２により基準電圧と比較される。コ
ンパレータ１２の出力は端子１５より専用リード端子に
出力される。(Prior Art) A pin scan circuit is provided for each lead terminal and has a configuration as shown in FIG. In the figure, a terminal 10 is connected to a lead terminal, a reference voltage is supplied to a terminal 11, and a comparator 12 compares the lead terminal voltage with the reference voltage. The output of the comparator 12 is output from the terminal 15 to a dedicated lead terminal.

従来の半導体集積装置は第８図に示す如く、リード端子
の近傍に設けられたピンスキャン回路１６１〜１６２１
夫々に基準電圧発生回路１７で発生したり準電圧を基準
電圧供給８１１８を介して供給している。As shown in FIG. 8, a conventional semiconductor integrated device has pin scan circuits 161 to 1621 provided near lead terminals.
A quasi-voltage generated by the reference voltage generation circuit 17 or supplied to each of them via a reference voltage supply 8118.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の構成では基準電圧発生回路１７は基１１！電圧供
給線１８の一端に配置されている。またピンスキャン回
路１６〜１６２ｏは集積装置の周縁に配置された複数の
リード端子の近傍に設けられているため、集積装置の大
型化に伴なって基準電圧供給線１８の長さが大となる。In the conventional configuration, the reference voltage generation circuit 17 has base 11! It is arranged at one end of the voltage supply line 18. Furthermore, since the pin scan circuits 16 to 162o are provided near a plurality of lead terminals arranged around the periphery of the integrated device, the length of the reference voltage supply line 18 increases as the integrated device becomes larger. .

ここで、隣接するピンスキャン回路間の距離に対応する
長さの基準電圧供給線１８の抵抗値をｒとし、ピンスキ
ャン回路の総数を２ｎとし、各ピンスキャン回路に流れ
る電流をｉとすると、基準電圧発生回路１７より最も離
間したピンスキャン回路１６２ｎに供給される基準電圧
の電圧降下量ＭＤＩは次式の如く表わされる。Here, if the resistance value of the reference voltage supply line 18 with a length corresponding to the distance between adjacent pin scan circuits is r, the total number of pin scan circuits is 2n, and the current flowing through each pin scan circuit is i, then The amount of voltage drop MDI of the reference voltage supplied from the reference voltage generation circuit 17 to the pin scan circuit 162n that is farthest apart is expressed by the following equation.

Ｖ、１−ｎ−（２ｎ＋１）−ｒ−ｉ−・・巾このように
、基準電圧供給線１８の電圧降下によってピンスキャン
回路１６　と１６２ｎとでは基準電圧が大きく異なって
しまうという問題があった。V, 1-n-(2n+1)-r-i-...width As described above, there was a problem in that the reference voltages of the pin scan circuits 16 and 162n differed greatly due to the voltage drop of the reference voltage supply line 18. .

本発明は上記の点に鑑みなされたもので、全てのピンス
キャン回路に供給される基準電圧の異差を小さくする半
導体集積装置を提供することを目的とする。The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor integrated device that reduces differences in reference voltages supplied to all pin scan circuits.

〔課題を解決するための手段〕[Means to solve the problem]

第１図は本発明装置の原理ブロック図を示す。 FIG. 1 shows a block diagram of the principle of the apparatus of the present invention.

同図中、ピンスキャン回路２０１〜２０２ｎは、半導体
チップの複数の外部端子夫々に対応して複数の外部端子
夫々のレベルをＵ＊を圧源２１よりの基準レベルと比較
し、比較結果を専用の外部端子から出力する。In the figure, pin scan circuits 201 to 202n compare the level of each of the plurality of external terminals U* with the reference level from the pressure source 21 corresponding to each of the plurality of external terminals of the semiconductor chip, and use the comparison results for exclusive use. output from the external terminal.

基準電圧供給線２２１．２２２夫々は、基準電圧源２１
より複数方向に延在して該複数のピンスキャン回路２０
１〜２０２１夫々に基準電圧を供給する。Each of the reference voltage supply lines 221 and 222 is connected to the reference voltage source 21
The plurality of pin scan circuits 20 extend in a plurality of directions.
A reference voltage is supplied to each of 1 to 2021.

〔作用〕[Effect]

本発明装置においては、基準電圧源２１より基準電圧供
給線２２．２２２が複数方向に延在して夫々ｎＩｆＪＡ
で総数２ｎ個のピンスキャン回路２０１〜２０２１夫々
に基準電圧を供給している。In the device of the present invention, the reference voltage supply lines 22 and 222 extend from the reference voltage source 21 in a plurality of directions, and each nIfJA
A reference voltage is supplied to each of a total of 2n pin scan circuits 201 to 2021.

ここで、隣接するピンスキャン回路間の距離に対応する
基準電圧供給線２２１，２２２夫々の抵抗値をｒとし、
各ピンスキャン回路に流れる電流をｉとすると、基準電
圧供給線２２１．２２２夫々基準電圧１１ｊ２１から最
も離れた端部２２１８゜２２　における電圧降下ｖＤ２
は次式の如く表わさａ れる。Here, the resistance value of each of the reference voltage supply lines 221 and 222 corresponding to the distance between adjacent pin scan circuits is r,
If the current flowing through each pin scan circuit is i, then the voltage drop vD2 at the end 2218°22 of each reference voltage supply line 221, 222 farthest from the reference voltage 11j21 is
is expressed as the following equation.

■　＝　ゴ’　　　（ｎ＋１）ｏｒ−ｉ−・・■この電
圧降下量Ｖ。２は従来の電圧降下ωＶＤＩに比して（ｎ
＋’ｌ　）／　（２ｎ＋１　）・２となり、各ピンスキ
ャン回路２０１〜２０２１夫々に供給される基準電圧の
周差を小さくできる。■=Go' (n+1)or-i-...■This voltage drop amount V. 2 is (n
+'l)/(2n+1)·2, and the difference in frequency between the reference voltages supplied to each pin scan circuit 201 to 2021 can be reduced.

〔実施例〕〔Example〕

第２図は本発明装置の第１実施例の平面図を示す。 FIG. 2 shows a plan view of a first embodiment of the device according to the invention.

同図中、半導体チップ３０Ａの周縁近傍にはリード端子
が接続される外部端子としての複数のパッド（図示せず
）夫々に隣接してピンスキャン回路（ＰＳ）３１　〜３
１３２が略等間隔に配設されている。In the figure, near the periphery of the semiconductor chip 30A, pin scan circuits (PS) 31 to 3 are adjacent to each of a plurality of pads (not shown) as external terminals to which lead terminals are connected.
132 are arranged at approximately equal intervals.

また、ピンスキャン回路３１　．３１５間、３１　．３
１２１間夫々の近傍に基準電圧源としての基準電圧発生
回路（ＰＧ）３２　．３２２が設置 けられ、この基準電圧発生回路３２１．３２２夫々から
は半導体チップ３０Ａの周縁と平行にピンスキャン回路
３１２９〜３１１２．３１１３〜３１２８夫々に沿って
基準電圧供給線３３１と３３２．及び３３３と３３４が
延在している。Also, the pin scan circuit 31. 315, 31. 3
A reference voltage generating circuit (PG) 32 . 322 are installed, and reference voltage supply lines 331 and 332 . and 333 and 334 extend.

ピンスキャン回路３１２９〜３１４．３１５〜３１１２
夫々は枝配線３４によって基準電圧供給線３３　　３３
２夫々に接続され、同様にビンスキ１　・ ヤン回路３１３〜３１２゜、３１２１〜３１２８夫々は
枝配線３４によって基準電圧供給１１３３３゜３３４夫
々に接続されている。Pin scan circuit 3129-314.315-3112
Reference voltage supply lines 33 and 33 are connected by branch wiring 34, respectively.
Similarly, the Binski 1-Yang circuits 313-312° and 3121-3128 are connected to reference voltage supplies 11333-334, respectively, by branch wiring 34.

このため、基準電圧発生回路３２１夫々の出力する基準
電圧は基準電圧供給線３３１．．３３□夫々でピンスキ
ャン回路３１　．３１１２側夫々の両方向に分配され、
ピンスキャン回路３１２９゜３１１２夫々における基準
電圧の電圧降下量が小さくて済む。これは基準電圧発生
回路３２□で発生された基準電圧についても同様でピン
スキャン回路３１１３，３１２８夫々における基準電圧
の電圧降下量が小さくて済む。Therefore, the reference voltage output from each of the reference voltage generation circuits 321 is applied to the reference voltage supply line 331. ．． 33□ Pin scan circuit 31. distributed in both directions on each of the 3112 sides,
The amount of voltage drop of the reference voltage in each of the pin scan circuits 3129 and 3112 can be small. This also applies to the reference voltage generated by the reference voltage generation circuit 32□, and the amount of voltage drop in the reference voltage in each of the pin scan circuits 3113 and 3128 can be small.

ここで、半導体チップ３０Ａにおける信号のＨレベルが
−０，９Ｖ、Ｌレベルが−１，７５Ｖであるとき、基準
電圧は−１，３２Ｖとされ、ピンスキャン回路３１　．
３１　　３１　．３１２８夫々に供給される基準電圧は
−１，３２Ｖから数１０−Ｖの周差範囲内とされている
。Here, when the H level of the signal in the semiconductor chip 30A is -0.9V and the L level is -1.75V, the reference voltage is set to -1.32V, and the pin scan circuit 31.
31 31. The reference voltage supplied to each of the 3128 is within the range of -1.32V to several 10-V.

第３図は本発明装置の第１実施例の変形例の平面図を示
す。FIG. 3 shows a plan view of a modification of the first embodiment of the device of the invention.

同図中、ピンスキャン回路３１２５〜３１８゜３１９〜
３１２４夫々は技装置１１３４によって基準電圧供給線
３５１〜３５４夫々に接続されている。In the same figure, pin scan circuits 3125~318°319~
3124 are connected to each of the reference voltage supply lines 351 to 354 by a technical device 1134.

基準電圧発生装置３２１，３２２夫々は半導体チップ３
０Ｂの互いに対向する角部に配置され、枝配線３４によ
って基準電圧供給線３５１と３５２゜３５３と３５４夫
々に基準電圧を供給している。Each of the reference voltage generators 321 and 322 is connected to a semiconductor chip 3.
The reference voltage supply lines 351 and 352, 353 and 354 are supplied with a reference voltage through branch wirings 34, respectively.

この変形例においても第１実施例と同様に基準電圧供給
線３５〜３５４夫々の端部に接続されま たピンスキャン回路３１　．３１　．３１９゜３１２４
夫々における基準電圧の電圧降下量が小さくて済む。In this modification, as in the first embodiment, the pin scan circuits 31 . 31. 319°3124
The amount of voltage drop in each reference voltage can be small.

第４図は本発明の第２実施例の平面図を示す。FIG. 4 shows a plan view of a second embodiment of the invention.

同図中、半導体チップ３０ｃの各辺の中央部に基準電圧
発生回路３２〜３２４が配設されていす る。これらは半導体チップ３０ｃの各辺に平行に延在す
る基準電圧供給線３７１〜３７８夫々を介してピンスキ
ャン回路３１１〜３１８．３１９〜３１．６，３１１．
〜３１２４．３１２５〜３１３２夫々に基準電圧を供給
している。In the figure, reference voltage generating circuits 32 to 324 are arranged at the center of each side of the semiconductor chip 30c. These pin scan circuits 311-318, 319-31.6, 311.
3124, 3125 to 3132, respectively.

この実施例では基準電圧発生回路３２１〜３２４夫々か
ら基準電圧供給線３７１〜３７８夫々の端部までの距離
が第１実施例の略１／２であり、上記端部のピンスキャ
ン回路３１　．３１８゜３１９．３１１６，３１１７，
３１２４，３１２５゜３１３２夫々における基準電圧の
電圧降下量が第１実施例よりも更に小さくて済む。In this embodiment, the distance from each of the reference voltage generation circuits 321 to 324 to the end of each of the reference voltage supply lines 371 to 378 is approximately 1/2 of that in the first embodiment, and the distance between the pin scan circuits 31 . 318°319.3116,3117,
The amount of voltage drop of the reference voltage at each of 3124, 3125° and 3132 can be smaller than in the first embodiment.

第５図は本発明装置の第２実施例の変形例の平面図を示
す。FIG. 5 shows a plan view of a modification of the second embodiment of the device of the invention.

同図中、ピンスキャン回路３１２．〜３１４゜３１５〜
３１１２．３１１３〜３１２ｏ、３１２１〜３１２８夫
々は枝配線３４によって基準電圧供給線３８１〜３８８
夫々に接続されている。基準電圧発生回路３２１〜３２
４夫々は半導体チップ３０００４つの角部に配置され、
枝配線３４によって基準電圧供給線３８１〜３８８夫々
に基準電圧を供給している。In the figure, pin scan circuit 312. ~314°315~
3112.3113 to 312o, 3121 to 3128 are connected to reference voltage supply lines 381 to 388 by branch wiring 34, respectively.
connected to each other. Reference voltage generation circuits 321-32
4 are placed at the four corners of the semiconductor chip 3000,
A reference voltage is supplied to each of the reference voltage supply lines 381 to 388 by the branch wiring 34.

この変形例においても第２実施例と同様に基準電圧供給
線３８１〜３８８夫々の端部に接続されたピンスキャン
回路３１２０．３１４．３１．。In this modification, as in the second embodiment, pin scan circuits 3120, 314, 31. .

３１１２．３１１３，３１２ｏ、３１２１，３１２８夫
々における基準電圧の電圧降下量が第１実施例より更に
小さくて済む。The amount of voltage drop of the reference voltage at each of 3112, 3113, 312o, 3121, and 3128 can be smaller than that of the first embodiment.

第６図は本発明装置の第３実施例の平面図を示す。同図
中、半導体チップ３０Ｅはフリップチップ方式のもので
全面にリード端子が接続される外部端子としての複数の
バンプが設けられ、このバンプに隣接してピンスキャン
回路３１１〜３１３２が設けられている。ピンスキャン
回路３１１〜３１１６．３１１７〜３１３２夫々の略中
央位置には基準電圧発生回路３９１．３９２夫々が設け
られ、ここから図中上下両方向に基準電圧供給線４０１
と４０２．４０３と４０４夫々が延在している。FIG. 6 shows a plan view of a third embodiment of the device according to the invention. In the same figure, the semiconductor chip 30E is of a flip-chip type and has a plurality of bumps as external terminals to which lead terminals are connected on the entire surface, and pin scan circuits 311 to 3132 are provided adjacent to the bumps. . Reference voltage generation circuits 391 and 392 are provided approximately at the center of each of the pin scan circuits 311 to 3116 and 3117 to 3132, and a reference voltage supply line 401 is connected from there to both the upper and lower directions in the figure.
and 402, 403 and 404 respectively extend.

ピンスキャン回路３１１〜３１４及び３１９〜３１１２
．３１５〜３１８及び３１１３〜３１１６゜３１１１〜
３１２ｏ及び３１２５〜３１２８．３１２１〜３１２４
及び３１２９〜３１３２夫々は基準電圧供給線４０、〜
４０４に直交する方向に延在する枝配線４１によって基
準電圧供給線４０．〜４ｏ４夫々に接続されている。Pin scan circuits 311-314 and 319-3112
．． 315~318 and 3113~3116°3111~
312o and 3125-3128.3121-3124
and 3129 to 3132 are reference voltage supply lines 40, to 3132, respectively.
Reference voltage supply line 40 . ~4o4 are connected to each other.

この実施例においても、基準電圧発生回路３９１．３９
２夫々から上下両方向に延在する基準電圧供給線４０．
．４０２，４０３．４０４夫々の端部に接続されたピン
スキャン回路３１１゜３１９．３１８，３１１６，３１
１７，３１２５゜３１２４．３１３２夫々における基準
電圧の電圧降下量が小さ（て済む。Also in this embodiment, the reference voltage generation circuit 391.39
A reference voltage supply line 40 extending both upward and downward from each of the reference voltage supply lines 40.
．． 402, 403, 404 Pin scan circuit 311° 319.318, 3116, 31 connected to each end
The amount of voltage drop of the reference voltage at each of 17, 3125°, 3124, and 3132 is small.

なお、基準電圧源２１としては基準電圧発生回路３２１
〜３２４，３９１．３９．の他に外部がら基準電圧を供
給する基準電圧外部供給端子であっても良く、上記実施
例に限定されない。Note that the reference voltage source 21 is a reference voltage generation circuit 321.
~324,391.39. In addition, a reference voltage external supply terminal that supplies a reference voltage from the outside may be used, and the present invention is not limited to the above embodiment.

〔発明の効果〕〔Effect of the invention〕

上述の如く、本発明装置によれば基準電圧供給線端部に
あるピンスキャン回路に供給される基準電圧の電圧降下
量が小さくて済み、全てのピンスキャン回路に供給され
る基準電圧の周差を小さくでき、実用上きわめて有用で
ある。As described above, according to the device of the present invention, the amount of voltage drop in the reference voltage supplied to the pin scan circuit at the end of the reference voltage supply line is small, and the difference in frequency between the reference voltages supplied to all pin scan circuits can be reduced. can be made small, making it extremely useful in practice.

【図面の簡単な説明】 第１図は本発明装置の原理図、 第２図乃至第６図は本発明装置の各実施例の平面図、 第７図はピンスキャン回路の回路構成図、第８図は従来
装置の一例のブロック図である。 図において、 ２０、〜２０２ｏ、３１１〜３１２８はピンスキャン回
路、 ２１は基準電圧源、 ２２　　２２　　３３　〜３３　　３５１〜１′　　２
°　　１　　４・ ３５４．３７．〜３７８，３８１〜３８８゜４０１〜４
０４は基準電圧供給線、 ３２１．３２２．３９３．３９２は基準電圧発生回路 を示す。 特許出願人　富　士　通　株式会社 ′）１、 同　　　弁理士　片　山　修　平　　　、゛、′くノ 第１図 第７図 虞庫褒５！のブ亡−ｖ２蘭 １１３図 キリヒ畔１１腎の箒２大えら僻１のキ恒■れ第４図[Brief Description of the Drawings] Fig. 1 is a principle diagram of the device of the present invention, Figs. 2 to 6 are plan views of each embodiment of the device of the present invention, Fig. 7 is a circuit configuration diagram of a pin scan circuit, and Fig. 7 is a diagram of the circuit configuration of the pin scan circuit. FIG. 8 is a block diagram of an example of a conventional device. In the figure, 20, ~202o, 311~3128 are pin scan circuits, 21 is a reference voltage source, 22 22 33 ~33 351~1' 2
° 1 4・ 354.37. ~378,381~388°401~4
04 is a reference voltage supply line, and 321.322.393.392 is a reference voltage generation circuit. Patent applicant: Fujitsu Limited') 1 Patent attorney: Shuhei Katayama Nobu Death - v2 Orchid 113 Diagrams Kirihi ridge 11 Kidney broom 2 Large gills 1 No Ki permanent Figure 4

Claims (1)

【特許請求の範囲】 　半導体チップの複数の外部端子夫々に対応して該複数
の外部端子夫々のレベルを基準電圧源（２１）よりの基
準レベルと比較し、比較結果を専用の外部端子から出力
する複数のピンスキャン回路（２０＿１〜２０＿２＿ｎ
）を内蔵する半導体集積装置において、 該基準電圧源（２１）より複数方向に延在して該複数の
ピンスキャン回路（２０＿１〜２０＿２＿ｎ）夫々に基
準電圧を供給する基準電圧供給線（２２＿１、２２＿２
）を有することを特徴とする半導体集積装置。[Claims] Compare the level of each of the plurality of external terminals corresponding to each of the plurality of external terminals of the semiconductor chip with a reference level from a reference voltage source (21), and output the comparison result from a dedicated external terminal. Multiple pin scan circuits (20_1 to 20_2_n
), reference voltage supply lines (22_1, 22_2) extending in a plurality of directions from the reference voltage source (21) and supplying a reference voltage to each of the plurality of pin scan circuits (20_1 to 20_2_n).
) A semiconductor integrated device characterized by having:
JP63146967A 1988-06-16 1988-06-16 Semiconductor integrated device Expired - Fee Related JP2809278B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63146967A JP2809278B2 (en) 1988-06-16 1988-06-16 Semiconductor integrated device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63146967A JP2809278B2 (en) 1988-06-16 1988-06-16 Semiconductor integrated device

Publications (2)

Publication Number Publication Date
JPH01316970A true JPH01316970A (en) 1989-12-21
JP2809278B2 JP2809278B2 (en) 1998-10-08

Family

ID=15419629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63146967A Expired - Fee Related JP2809278B2 (en) 1988-06-16 1988-06-16 Semiconductor integrated device

Country Status (1)

Country Link
JP (1) JP2809278B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03253060A (en) * 1990-03-02 1991-11-12 Nec Corp Semiconductor integrated circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54101281A (en) * 1978-01-26 1979-08-09 Nec Corp Logic circuit
JPS5651354U (en) * 1979-09-26 1981-05-07
JPS594153A (en) * 1982-06-30 1984-01-10 Matsushita Electric Ind Co Ltd Manufacturing method of semiconductor device
JPS62260355A (en) * 1986-05-06 1987-11-12 Toshiba Corp Semiconductor integrated circuit device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54101281A (en) * 1978-01-26 1979-08-09 Nec Corp Logic circuit
JPS5651354U (en) * 1979-09-26 1981-05-07
JPS594153A (en) * 1982-06-30 1984-01-10 Matsushita Electric Ind Co Ltd Manufacturing method of semiconductor device
JPS62260355A (en) * 1986-05-06 1987-11-12 Toshiba Corp Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03253060A (en) * 1990-03-02 1991-11-12 Nec Corp Semiconductor integrated circuit

Also Published As

Publication number Publication date
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