JPH0131837B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a chroma signal recording/reproduction method, and is particularly suitable for reducing noise mixed in chroma signals having low-level sidebands, and is suitable for both recording and reproduction. Concerning an advantageous chroma emphasis/de-emphasis circuit.

[Prior art]

As a conventional video tape recorder (hereinafter referred to as VTR) technology, there is the Philips V-2000 system that improves tracking performance.As a technology to improve sound quality, the audio signal is frequency modulated and frequency multiplexed on the video track. Recording has been known for a long time.

A spectrum diagram of a signal recorded on a video track in the above method is shown in FIG. The problem here is that the pilot signal 23 and FM audio signal 24 interfere with the chroma signal 22, degrading the chroma image quality.

In FIG. 1, 21 is an FM luminance signal, 22 is a low frequency conversion chroma signal, 23 is a tracking control pilot signal, and 24 is an FM audio signal.

The problem is that the pilot signal 23 and FM audio signal 24 are reproduced as sideband signals of the chroma signal 22, causing beat disturbance on the screen, and spurious fc±2fp ( fc: chroma frequency, fp: pilot frequency), which also causes beat disturbance on the screen.

The above interference is caused by (1) that the chroma signal is an AM recording, (2) that the pilot frequency and FM audio frequency are close to the chroma signal band, and (3) that the pilot signal and FM audio signal recording level are not low enough. This is due to this.

Therefore, it would be possible to record by separating the respective frequencies sufficiently or by converting the chroma signal to an FM signal, but in this case, a wide bandwidth would be required, which would reduce the recording density and make it impractical. It won't happen. Alternatively, it is possible to sufficiently lower the recording level of the pilot signal and FM audio signal, but this would cause problems with tracking control characteristics and sound quality, making it impractical.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a chroma emphasis de-emphasis circuit that can eliminate the drawbacks of the prior art, reduce noise mixed into chroma signals, and is suitable for both recording and reproduction.

[Summary of the invention]

In order to achieve the above purpose, a circuit is provided to perform sideband emphasis and sideband de-emphasis on the small amplitude input of the chroma signal during recording and playback, respectively. It consists of an element and a trap circuit consisting of L and C. Also,
In order to make it easier for the emphasis circuit and the de-emphasis circuit to have opposite characteristics, feedback technology is used to make both circuits compatible, thereby saving the circuit scale.

[Embodiments of the invention]

FIG. 2 is a block diagram showing one embodiment of the chroma enhancement circuit of the present invention. In Figure 2, 1 is a signal voltage source, 2 is an input terminal of the chroma emphasis circuit, and 3 is a voltage controlled voltage source (hereinafter referred to as VCV
It is called. ), 4 is a resistor, 5 is an emphasis nonlinear circuit, 6 is a buffer circuit, 7 is an adder circuit, and 8 is an output terminal of the chroma emphasis circuit.

The emphasis nonlinear circuit 5 has a point where the AC impedance is zero at the chroma subcarrier frequency fsc (approximately 3.58MHz for NTSC and approximately 4.43MHz for PAL), and when the input level is high to a certain extent, the input impedance is almost zero. This is a circuit in which the input impedance increases as the level decreases. Such a circuit can be realized, for example, by the circuit shown in FIG. In Fig. 5, 11 is an input terminal, D ₁ and D ₂ are diodes, L ₁ is an inductance, and C ₁ is a capacitance. The resonant frequency of L ₁ and C ₁ is
It is fsc. For the diodes D ₁ and D ₂ , it is advantageous to use Schottky type diodes whose input impedance approaches zero at a relatively small input level, in order to reduce the signal level of the circuit. The operation of the circuit shown in FIG. 2 will be explained. The signal voltage source 1 produces a voltage of Ae ₁ on the VCV3. A is the amplification factor of VCV3. The resistor 4 nonlinear circuit 5 acts as a load for this voltage Ae ₁ and generates the following voltage at the input of the buffer circuit 6. This is a chroma signal in which the chroma subcarrier frequency components are suppressed, leaving only sideband components, and the maximum level is limited. Such a signal is taken out through a buffer circuit 6 and added to the original signal in an adder circuit 7. As a result, the signal obtained at the output terminal 8 is a signal with sidebands emphasized, and the degree of emphasis increases as the sideband level of the original signal becomes smaller. In other words, the chroma signal is dynamically sideband emphasized depending on the sideband level. By passing the signal that has been emphasized in this way through a de-emphasis circuit having an inverse characteristic in a reproduction circuit, it is possible to improve the S/N of a chroma signal with a small sideband level.

In Fig. 2, the resistor 4 (value R) serves as the driving impedance of the nonlinear circuit 5, and is a series resonant element.
Determine the Q (=wL ₁ /R) of L ₁ C ₁ . FIG. 7 shows an example of the frequency characteristics of the emphasis circuit shown in FIG. 2.

According to this characteristic diagram, the chroma emphasis circuit continuously increases the amount of emphasis for each input level as the frequency of the input recording chroma signal moves away from the resonance frequency in the frequency band of 3.58MHz ± 500KHz. Emphasize the recording chroma signal so that Furthermore, at each frequency except for the resonant frequency of 3.58MHz, the amount of emphasis increases as the level of the input signal decreases, and the amount of increase is 0 dB because there is no increase at the resonant frequency, but continues from 0 dB as you move away from the resonant frequency. increases to

The nonlinear circuit 5 can also be constructed as shown in FIG. In Fig. 6, C ₂ is a capacitor for cutting the DC component, R ₁ to _{R 5} are resistors, and Q ₁ and Q ₂ are transistors L ₂
is the inductance for DC component conduction. In FIG. 6, elements shown with the same symbols as in FIG. 5 indicate the same things. In this circuit, R ₃ /R ₄ should be approximately 3. This makes it possible to obtain the effect of changing the impedance of the diode even if the input signal level does not change significantly, which is advantageous for lowering the input level of the circuit.

FIG. 3 shows a different embodiment from that shown in FIG. Second
The difference from the figure is that a voltage controlled current source (hereinafter referred to as VCC) 9 is used instead of VCV3.
Other parts are exactly the same. In FIG. 3, signal voltage source 1 produces a current of gmv ₁ in VCC9.
gm is the conversion conductance of VCC9. Here, if gm=A/R, it can be explained that VCC 9 and resistor 4 are completely equivalent to VCV 3 and resistor 4 in FIG. 2, according to the equivalent power supply law. Therefore, the circuit operation is exactly the same as the embodiment shown in FIG.

FIG. 4 shows an embodiment different from those shown in FIGS. 2 and 3. In Figure 4, 10 is the second resistor (value is R'), 16
is a buffer circuit. In this circuit, choose gm=A/R R'=R/A. As a result, the voltage v ^R ' across the resistor 10 becomes as follows.

v ^R ′=gm・e ₁・R′=A/Re ₁ R/A=e ₁ Therefore, the signal obtained at the output terminal 8 is the voltage generated across the resistor 4 plus e ₁ , and The result is exactly the same as the example in Figure 3. In this way, in the example of FIG. 4, the adder circuit 7 is not required, and the circuit becomes simpler.

FIG. 8 is a block diagram showing one embodiment of the chroma de-emphasis circuit of the present invention. In FIG. 8, 31 is a signal voltage source (input to the de-emphasis circuit), 32 is an input terminal of the chroma de-emphasis circuit, 33 is a subtraction circuit, and 34 is an output terminal of the chroma de-emphasis circuit. It can be seen that the transfer functions of the circuit of FIG. 8 are mutually inverse to those of the circuit of FIG. Assuming that the transfer function from the input of VCV3 to the output of buffer circuit 6 is G(sa) (where a is the input level), the transfer function of the circuit in Figure 2 is: 1+G(s, a). This is because the circuit transfer function: 1/1+G(s, a).

In this way, the transmission path (VCV
(path from the input of 3 to the output of buffer circuit 6)
is used as a feedback path during playback, the transfer functions become completely inverse functions of each other, so the emphasis effect during recording is accurately canceled by the de-emphasis effect during playback, and the effects of emphasis and de-emphasis are completely eliminated. chroma signal is played back.

FIG. 9 shows an embodiment of a de-emphasis circuit different from that shown in FIG. FIG. 9 shows a feedback type version of the emphasis circuit shown in FIG. 3, and its operation is exactly the same as that of the embodiment shown in FIG.

FIG. 10 is a block diagram showing an embodiment of the chroma emphasis/de-emphasis circuit of the present invention. In FIG. 10, 35 is a recording/reproduction switching switch. The illustrated switching position indicates the time of reproduction (when the de-emphasis circuit is used). FIG. 10 combines the emphasis circuit of FIG. 2 with the de-emphasis circuit of FIG. 8, and the only additional component is the switch 35. FIG. 11 shows an embodiment of a chroma emphasis/de-emphasis circuit different from that shown in FIG. 10. 11 is a combination of the emphasis circuit of FIG. 3 and the de-emphasis circuit of FIG. 9, and the only additional component is the switch 35.

In FIGS. 10 and 11, the output point to the output terminal 34 can also be the output of the switch 35. Further, the path from the output of the switch 35 to the adder circuit 7 may be drawn out from the b input side of the switch 35 to reach the adder circuit 7.

FIG. 12 shows an embodiment of a chroma emphasis/de-emphasis circuit different from those shown in FIGS. 10 and 11. FIG. 12 shows a combination of the emphasis circuit of FIG. 4 and the de-emphasis circuit of FIG. 9. In this example, FIG.
Compared to the embodiment shown in FIG. 1, the adder circuit 7 is not required, and the circuit can be simplified. The buffer circuit is the 10th
Although there is one more buffer circuit than in the examples shown in FIGS. and 11, the buffer circuit 6 can be easily integrated with the subtraction circuit 33 and does not become substantially complicated.

In FIG. 12, the output point to the output terminal 34 can also be the output of the switch 35.

Next, a burst signal amplitude detection point to ACC in a chroma signal processing system using the chroma emphasis/de-emphasis circuit of the embodiment shown in FIGS. 10, 11, and 12 will be described. Since the chroma emphasis/de-emphasis circuit as seen in these embodiments is a nonlinear circuit whose frequency characteristics change depending on the input level, it is necessary to prevent the input burst level from varying. Therefore, during recording, the input level of the chroma emphasis circuit is adjusted by using the input side of the chroma emphasis circuit as the birth signal amplitude detection point for the ACC. This allows you to emphasize the chroma signal with the correct dynamic characteristics.

Furthermore, during playback, the order of signal processing should be completely reversed from that during recording, so the output of the chroma de-emphasis circuit is used as the burst signal amplitude detection point for the ACC. This allows de-emphasis of the chroma signal with the correct dynamic characteristics.

FIG. 13 shows a specific embodiment of the chroma emphasis/de-emphasis circuit of the present invention. In the same figure, Q ₁₁ to Q ₃₉ are transistors R ₁₁
~R ₄₀ is a resistor, D ₁₁ and D ₁₂ are Schottky diodes, C ₁₁ to _{C 14} are capacitors, L ₁₃ and L ₁₄ are inductances, S ₁ and S ₂ are recording/reproduction switching circuits,
E ₁ is the voltage source, 41, 42, 43 are the first,
These are pins of the second and third integrated circuits. The system shown in FIG. 13 is based on the embodiment shown in FIG. 12.

The operation during recording will be explained. During recording, the switching positions of switch circuits S ₁ and S ₂ are reversed from those shown. This turns Q ₂₆ ON, Q ₂₅ OFF, and input terminal 2.
The signal from the Q ₂₄ base is guided to the same emitters Q ₂₃ and Q ₂₇ base. Furthermore, it leads to the Q ₂₇ emitter, R ₂₅ , Q ₂₉ base, the same emitter, and the Q ₃₁ base. At the same time, the signal voltage-divided by R ₂₆ and R ₃₇ from the Q ₂₇ emitter is guided to the Q ₃₄ base, the same emitter, and the Q ₃₂ base. ( _C12 is an AC cut bypass capacitor.)
Therefore, as an input to the differential pair Q ₃₁ and Q ₃₂ ,
(1-R ₃₇ /R ₃₇ +R ₂₆ ) times as many signals are guided. The differential pair Q ₃₁ and Q ₃₂ are voltage controlled current sources, and R ₃₀ is the 12th
The resistor 10 in the figure, R ₂₈ +R ₂₉ , corresponds to the resistor 4 in FIG. 12. Externally connected to the first pin 41 is the nonlinear circuit 5 . Therefore, the signal generated at the collector of Q ₃₁ may be guided to the emitter follower (hereinafter referred to as EF) of Q ₃₆ and then to the output terminal 8. Equivalently, gm (or A) can be adjusted by the value of _R37 .

The operation during playback will be explained. Switch circuit S ₁ , S ₂
is in the position shown. The signal from the input terminal 32 is guided to the EF of Q ₁₁ and fed back to Q ₁₂
The signal led to the EF is attenuated and added by R ₁₁ and R ₁₂ . This signal passes through the EF of Q ₁₅ and the level shift of Q ₁₆ , and is further transferred from R ₁₅ and R ₁₆ to the differential pair Q ₁₈ ,
Entered in Q ₁₉ . The output of the differential amplifier constituted by the differential pair Q ₁₈ and Q ₁₉ is obtained at the collector of Q ₁₉ . Adjust with R ₃₆ so that the gain is 0dB in the attenuation → amplification process up to this point. The effectiveness of C ₁₁ will be discussed later. The signal is then routed to the Q ₂₁ base, the same emitter, Q ₂₂ and Q ₂₇ bases. The operation from here to the differential pair Q ₃₁ and Q ₃₂ is the same as that during recording. As the feedback signal, a signal attenuated by _R28 and _R29 is used to match the level with the input signal. Attenuation may be eliminated by appropriately setting the input signal level to the de-emphasis circuit. The output during playback is obtained from the _Q21 emitter to the output terminal 34.

Generally, if the circuit shown in FIG. 12 can be ideally realized, the emphasis circuit and de-emphasis circuit will have completely opposite characteristics. However, the first
When an actual circuit is made and operated as shown in FIG. 3, a phenomenon occurs in which the centers of the frequency characteristics of the emphasis circuit and the de-emphasis circuit are shifted. This is because a slight phase delay occurs in the feedback path due to the collector capacitance of the transistor. Therefore, some kind of correction that substantially corrects the phase delay is required.
In the embodiment shown in FIG. 13, the following correction can be made.
The purpose is to make the differential amplifier of Q ₁₈ and Q ₁₉ into an amplifier with a phase lead by choosing a slightly smaller value for C ₁₁ rather than using it as a complete bypass capacitor.
This makes it possible to create an emphasis/de-emphasis circuit that corrects the phase delay that occurs in the feed path and is compatible with recording and playback.

In this way, C ₁₁ , R ₃₆ and as mentioned above
It is better to make C ₁₂ and R ₃₇ external to the integrated circuit as well. However, if there is no need for adjustment, these may be built into the integrated circuit.

In the example shown in Fig. 13, in order to save power,
It is sufficient to design the collector current of each transistor to be reduced. However, the values of R ₂₈ and R ₂₉ serve as the driving impedance of the series resonant circuits C ₁₃ and L ₁₃ , and there is a limit to how high the impedance can be made in order not to reduce the value of Q too much. For this reason
As for Q ₃₁ , Q ₃₂ , and Q ₃₃ , the design should not reduce the collector current too much. Further, as in the embodiment shown in FIG. 13, switching between recording and reproduction and turning off transistors unnecessary for circuit operation is effective in further reducing power consumption.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the noise mixed into the chroma signal, which is effective in improving the chroma S/N of the reproduced image. Furthermore, the emphasis circuit and the de-emphasis circuit can be easily combined, and an increase in circuit scale can be suppressed. Moreover, it is easy to make the emphasis circuit and the de-emphasis circuit opposite to each other.

[Brief explanation of drawings]

FIG. 1 is a characteristic diagram showing an example of the spectrum of a signal written on a video track, FIG. 2 is a block diagram showing an example of a chroma emphasis circuit according to the present invention, and FIGS. A block diagram showing another embodiment of the chroma emphasis circuit by
5 and 6 are circuit diagrams showing an example of the nonlinear circuit for emphasis used in the present invention, FIG. 7 is a characteristic diagram showing an example of the emphasis characteristic, and FIGS. 8 and 9 are circuit diagrams showing an example of the nonlinear circuit for emphasis used in the present invention. Block diagrams showing one embodiment of the emphasis circuit, FIGS. 10 and 11
12 is a block diagram showing an example of the chroma emphasis/de-emphasis circuit according to the present invention, and FIG. 13 is a block diagram showing an example of the chroma emphasis/de-emphasis circuit according to the present invention
FIG. 2 is a circuit diagram showing a specific example of a circuit that also serves as day-emphasis. Explanation of symbols 3... Voltage controlled voltage source, 5... Nonlinear circuit for emphasis, 7... Addition circuit, 9... Voltage controlled current source, 33... Subtraction circuit, 35... Recording/reproduction switching switch.

Claims (1)

[Claims] 1 A nonlinear trap circuit including a limiter and a resonant circuit; a first transmission path for passing the recording chroma signal through the nonlinear trap circuit to extract its sideband signal during recording; A chroma emphasis circuit is formed which consists of a second transmission path for transmission and an adder circuit that adds the outputs of the first and second transmission paths. In the frequency band, the amount of emphasis increases continuously as the frequency of the recorded chroma signal moves away from the resonant frequency, and the amount of emphasis increases as the level of the recorded chroma signal decreases, and the amount of increase reaches the resonant frequency at 0 dB at the resonant frequency. 0dB as you move away from
A third transmission line that emphasizes the recorded chroma signal so that it increases continuously from the first line, and amplifies the reproduced chroma signal during playback;
A chroma signal emphasis/de-emphasis circuit comprising a feedback path that provides negative feedback to the input side of a third transmission path via a transmission path.