JPH01319833A - Run-away detector for computer system - Google Patents

Abstract

PURPOSE:To detect the run-away when a CPU, etc., run away and to immediately introduce a system to a fail safe by directly monitoring an input signal of the CPU, etc., with a run-away detecting circuit provided at the external part of a run-away detecting object such as the CPU. CONSTITUTION:A microcomputer system has a CPU 1 of a microprocessor mode, a memory part 2 having a ROM to store fixed data, a RAM for storing data and the like, a peripheral control part 3, an address bus 4, a data bus 5 and a control bus 6 to communicate a reading signal and a writing signal and further, provides a CPU run-away detecting circuit 7 and links this to buses 4-6. This CPU run-away detecting circuit 7 monitors the set-up time and the holding time of respective input signals necessary to the normal action of the CPU 1, etc., and when the time cannot be maintained for a prescribed time, an abnormal signal is generated. Thus, the malfunction can be detected and the system can be immediately introduced to the fail safe.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a runaway detection device for a computer system.

(Prior Art) As a means of detecting runaway in a computer system, for example, a microcomputer system, a watchdog timer (hereinafter abbreviated as WDT) is conventionally provided to monitor runaway in a central processing unit (CPU) in the form of a microprocessor.
There is a known program that controls the WDT by resetting and starting the WDT at regular intervals to ensure that the WDT does not run out of control.

[Problem to be solved by the invention]

However, with this method, if the CPU goes out of control due to external noise etc. and the reset start of WDT is not performed, the runaway will not be recognized by the system until the WDT setting time has elapsed and timed out. During this time, data on the memory may be destroyed over a wide area, or illegal data may be written to the output port, which may cause great harm to the entire system.

In view of such problems, an object of the present invention is to provide a runaway detection method for a computer system that can immediately detect and stop a computer system using a CPU or the like when it runs out of control. do.

[Means to solve the problem]

To this end, the present invention provides a monitoring means for monitoring the set-up and hold times of signals transmitted on a bus line of a computer system, and when the monitoring time does not satisfy a predetermined time condition for a component of the computer system. The present invention is characterized by comprising a determining means for determining that there is an abnormality.

(Function) The present invention focuses on the fact that most of the runaway of components of computer systems such as CPUs is caused by erroneous reading and writing due to noise, and provides output signals for each individual that are necessary for normal operation of the CPU, etc. The set-up time and hold time of the system are monitored, and if this time cannot be maintained for a predetermined period of time, an abnormal signal is generated as a result of a runaway.This abnormal signal is used to detect a malfunction and immediately lead the system to fail-safe. becomes possible.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

First, an overview will be explained using FIG. 1.

(a) in the figure shows a read signal (RD signal) or a write signal (WT signal). Based on this, during normal operation, a bus signal as shown in (b) in the figure appears, and between the two signals. A predetermined set-up time t and hold time jh are guaranteed. On the other hand, (C) in the figure shows a case where the predetermined set-up time t and hold time 1h are not guaranteed due to noise N, etc., and in this case, the CP
U malfunctions and goes out of control.

Since the set-up time t and the hold time t5 are defined between each change point of the rising edge and falling edge between the two signals of interest, the time relationship of the rising edge and the falling edge of the two signals of interest is measured, By determining whether or not predetermined set-up and hold times have been met, it is possible to determine whether normal operation is being performed or whether malfunction has occurred.

In the embodiment, this time relationship is measured and determined as follows. A group of signals of interest is input to a state change detection circuit and converted into a pulse train corresponding to the rise and fall of each signal. Two noteworthy pulse trains are extracted from these pulse trains, and one of the pulse trains is used manually as a starting signal for starting measurement of a time measuring circuit whose set up time and hold time are set to ensure normal operation. In addition, the remaining pulse train is manually input as a stop signal for stopping or terminating the measurement. In response to these human input signals, the time measurement circuit outputs a measurement stop signal for the stop signal and a timeout output to notify that the measurement time has exceeded the set time and the measurement has ended. The two output signals from this time measurement circuit determine whether the CPU is operating normally or malfunctioning.

That is, since the timeout output indicates the result of measurement beyond the predetermined set-up time and hold time, it is a signal that guarantees the read and write operations of the CPU. On the other hand, the measurement stop signal output is a signal indicating that the set-up time and hold time set in advance in the measurement circuit are not satisfied, and when this signal is output, the operation during reading and writing of CPLI is guaranteed. This indicates that the Therefore, if there is a timeout output signal, it is considered to be normal, and if a measurement stop signal is output, it is considered to be abnormal.If you generate an abnormal signal based on this signal and notify the system by reset or interrupt, the system will immediately fail. Can lead to safety.

Next, this example will be explained in more detail.

FIG. 2 shows a microcomputer system according to an embodiment of the present invention, where 1 is a CPU in the form of a microprocessor, and 2 is an RO that stores fixed data such as programs.
3 is a peripheral control unit.

4 is an address bus, 5 is a data bus, and 6 is a read signal (
This is a control bus for transmitting RD double signals, write signals (WT double signals, etc.).In addition to this configuration, in this embodiment, a CPU runaway detection circuit 7 is provided and this is coupled to buses 4 to 6. be.

FIG. 3 shows a detailed configuration example of the CPU runaway detection circuit 7.

Here, 84 to 86 are state change detection circuits connected to the buses 4 to 6, respectively, and can be composed of a differentiating circuit, a filter circuit, and the like. 94 and 95 are OR gates that calculate the logical sum of the outputs of the state change detection circuits 84 and 85, respectively.
It is a circuit. 105 is a monitoring timer control circuit, and RD
RD signal pulse 14R and WT signal pulse 14W generated by state change detection circuit 86 with double signal and WT double signal
, and the data pulse train 15 which is converted into pulses by the state change detection circuit 85 and logically summed by the OR circuit 95 for the data signal group. Reference numeral 104 denotes a supervisory timer control circuit that receives the pulses 14R, 14K and a pulse train related to the signal group of the address bus and controls the set-up timer 114 and the hold timer 124.

The set-up timers 114 and 115 output a time-up output signal 18 or a measurement stop output signal 19,
The hold timers 124 and 125 output a time-up output signal 21 or a measurement stop output signal 22, and these timers can be configured using an OR time constant circuit or a timer circuit. These outputs are then supplied to a determination signal output circuit 13, and if there is an abnormality, an abnormality signal 20 is output.

In the above configuration, when the CPIII performs a read operation of data on the memory 2, the fourth
This will be explained using the diagram and FIG.

At this time, the signals of the RD signal address bus 4 and data bus 5 are manually input to the CPIJ runaway monitoring circuit 7 (the fourth
See figure (A). However, although the figure shows an example of a data bus, the same applies to an address bus). The input signals are manually input to state change detection circuits 84 to 86,
Each signal is converted into a pulse train as shown in FIGS. 4(A) to 4(B). Of this pulse train, the RD signal pulse is manually input to the monitoring timer control units 104 and 105 as a set-up timer measurement stop signal and a hold-up timer activation signal. Further, the determination signal output circuit 13 is also manually inputted as a status. On the other hand, a pulse train 15 related to an address bus and a data bus, and monitoring timer control units 104 and 105
is input as a set-up timer start signal and a hold-up timer measurement stop signal.

When a set-up timer activation signal is input to the supervisory timer control units 104 and 105, the set-up timers 114 and 115, which have set up a set-up time to ensure normal operation, are activated via the signal line 16 and start measurement. Start.

When the timers 114 and 115 exceed the set time, a set-up timer output or time-up output 18 is generated and input to the judgment signal output circuit 13. Under normal conditions, the measurement time satisfies the set time, so abnormal signal 2
0 is not output (FIG. 4(C)). When the RD signal pulse 14 is continuously applied manually, the set-up timer 114,
The hold-up timer 115 is reset because the time has expired, and the hold-up timers 124 and 125, which are set with a hold-up time that guarantees normal operation, start measuring.

When the timers 124 and 125 exceed the set time, a hold-up timer output or time-up output 21 is generated and input to the judgment signal output circuit 13. Under normal conditions, the measurement time satisfies the set time, so abnormal signal 2
0 is not output (FIG. 4(C)).

On the other hand, in the event of an abnormality, after the set-up timer is activated, but before the timers 114 and 115 measure beyond the set time, the RD signal pulse 14 is sent to the monitoring timer control unit 104.10.
5 and the judgment signal output circuit 13, the measurement is stopped and the timers 114 and 115 output the measurement stop output 19.
is notified to the judgment signal output circuit 13. The camera settings are the same as the setup time that guaranteed operation.
If the measurement ends before the time-up output, the setup time will be insufficient, and the address bus 4 for the RD signal will be
．． The setup time of data bus 5 is defective and the CP
U misreads. Therefore, by inputting the measurement stop signal by the RD signal pulse 14, the judgment signal output circuit 13
An abnormality signal 20 is generated (FIG. 5) and can be notified to the system by reset, interrupt, etc. The same applies to the case of poor hold time.

As described above, since an abnormality can be detected immediately after a malfunction, there is an advantage that the system can be easily made fail-safe.

In the above embodiments, the present invention was applied to detecting a runaway CPU, but the present invention can also be applied to detecting a runaway in other devices and apparatuses constituting a computer system by changing the set time of the timer. Of course, it can be applied effectively.

〔Effect of the invention〕

As explained above, according to the present invention, the runaway detection circuit provided outside the CPU or other object to be detected for runaway is configured to directly monitor the input/output signals of the CPU or the like. It is possible to stop the operation of the CPU, etc. in the minimum amount of time, and to minimize the negative impact on the surroundings.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram for explaining the outline of the runaway detection device of the present invention, FIG. 2 is a block diagram showing an embodiment of the computer system according to the present invention, and FIG. 3 is a runaway detection circuit according to the present embodiment. 4(A) to (C) are timing charts for explaining the normal operation according to this embodiment, and FIG. 5 is a timing chart for explaining the operation during abnormality. This is a timing chart. 1...cpu. 2... Memory, 3... Peripheral control unit, 4... Address bus, 5... Data bus, 6... Control bus, 7... CPU runaway monitoring circuit, 13... Judgment signal Output circuit, 84-86... State change detection circuit, 94.95... OR circuit, 104.105... Monitoring timer control circuit, 114.1
15...Set-up timer, 124.125...
Hold timer. Figure 1 Figure 2 Figure 4 RDMJWTI official name Figure 4

Claims (1)

[Claims] 1) A monitoring means for monitoring the setup time and hold time of a signal transmitted through a bus line of a computer system, and determining that an abnormality occurs when the monitoring time does not satisfy a preset time condition for a component of the computer system. 1. A runaway detection device for a computer system, comprising: determination means.