JPH01319948A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01319948A JPH01319948A JP63152708A JP15270888A JPH01319948A JP H01319948 A JPH01319948 A JP H01319948A JP 63152708 A JP63152708 A JP 63152708A JP 15270888 A JP15270888 A JP 15270888A JP H01319948 A JPH01319948 A JP H01319948A
- Authority
- JP
- Japan
- Prior art keywords
- silicon wafer
- thermosetting resin
- semiconductor device
- lead frame
- bond
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/013—Manufacture or treatment of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
Landscapes
- Die Bonding (AREA)
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は半導体装置の製造方法および半導体装置製造用
シリコンウェハに関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing a semiconductor device and a silicon wafer for manufacturing a semiconductor device.
〈従来の技術〉
ICやLSI等の半導体装置の製造において、リードフ
レームに半導体チップ(回路をパターニングしたシリコ
ンウェハを所定の大きさに切断したもの)からなる素子
を固定する工程がある。従来、この工程ではチップを固
定するに際してペースト状接合剤が用いられており、通
常はペースト状接合剤をリードフレームのタブ上にディ
スペンス法またはスクリーン印刷法にて形成し、次に形
成された接合剤上にチップを載置し、加熱硬化させる方
法が採用されている。このようにして接合されたものに
ワイヤボンディングを行なったのち、樹脂モールド法等
にて封止を行なうのが一般的である。<Prior Art> In the manufacture of semiconductor devices such as ICs and LSIs, there is a step of fixing an element made of a semiconductor chip (a silicon wafer patterned with a circuit cut into a predetermined size) to a lead frame. Traditionally, this process uses a paste bonding agent to secure the chip, and the paste bonding agent is usually formed on the tab of the lead frame by a dispensing method or screen printing method, and then the formed bond is The method used is to place the chip on top of the agent and heat it to harden it. After wire bonding is performed on the parts joined in this way, it is common to perform sealing using a resin molding method or the like.
〈発明が解決しようとする課題〉
しかし、上記従来からの方法ではペースト状接合剤に粘
度のバラツキや劣化等がある場合、形成される接合剤の
量や厚みなどにバラツキを生じ、その結果、得られる接
合物の強度にもバラツキが生じて信軌性に劣るようにな
る。また、ときには強度不足によって後の工程(例えば
ワイヤボンディング工程など)で接合されたチップが剥
離、脱落を起こしたり、ペースト量が多い場合にはペー
ストの食みだしによって半導体素子としての特性不良に
陥ることもあり、信頼性を低下させる恐れがある。<Problems to be Solved by the Invention> However, in the above-mentioned conventional methods, if the paste-like bonding agent has variations in viscosity or deterioration, the amount and thickness of the bonding agent formed will vary, and as a result, The strength of the resulting joined product also varies, resulting in poor reliability. In addition, sometimes due to insufficient strength, chips bonded in later processes (such as wire bonding process) may peel or fall off, or if the amount of paste is large, the paste may ooze out, resulting in poor characteristics as a semiconductor element. This may reduce reliability.
従って、本発明は接合剤の形成量や厚みをバラツキなく
均一にでき、チップの接合強度を一定に維持できる半導
体装置の製造方法を提供することを目的とする。Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device in which the amount and thickness of the bonding agent can be made uniform without variation, and the bonding strength of the chips can be maintained constant.
〈課題を解決するための手段〉
本発明者らは上記目的を達成すべく検討を重ねた結果、
切断前のシリコンウェハに接合剤として半硬化状態の熱
硬化性樹脂層を形成し、そののち切断、固定を行なうこ
とによって接合剤形成量にバラツキのない信頼性の向上
した半導体装置が製造できることを見い出し、本発明を
完成させるに至った。<Means for Solving the Problems> As a result of repeated studies by the present inventors to achieve the above object,
By forming a semi-hardened thermosetting resin layer as a bonding agent on a silicon wafer before cutting, and then cutting and fixing it, it is possible to manufacture semiconductor devices with improved reliability and no variation in the amount of bonding agent formed. This discovery led to the completion of the present invention.
即ち、本発明は回路をパターニングしたシリコンウェハ
の裏面全面に、半硬化状態の熱硬化性樹脂層を形成し、
所定の大きさに切断を行なったのち、切断片をリードフ
レームのタブ上に7a置、熱゛圧着することを特徴とす
る半導体装置の製造方法、および該半導体装置製造用シ
リコンウェハに関するものである。That is, the present invention forms a semi-cured thermosetting resin layer on the entire back surface of a silicon wafer patterned with a circuit,
The present invention relates to a method for manufacturing a semiconductor device, characterized in that after cutting to a predetermined size, the cut piece is placed on a tab of a lead frame and thermally compressed, and a silicon wafer for manufacturing the semiconductor device. .
第1図(a)のように、本発明において回路を印刷等に
よってパターニングしたシリコンウェハ1の裏面全面に
は半硬化状態(Bステージ)の熱硬化性樹脂層2が形成
される。As shown in FIG. 1(a), in the present invention, a thermosetting resin layer 2 in a semi-cured state (B stage) is formed on the entire back surface of a silicon wafer 1 on which a circuit has been patterned by printing or the like.
形成方法としては任意の方法が採用できるが、代表的に
は下記方法が用いられる。Although any method can be adopted as the forming method, the following method is typically used.
■Bステージの熱硬化性樹脂を融点以上、硬化温度以下
の温度にて溶融させ、ホットメルトコータにて塗工する
方法。■A method in which B-stage thermosetting resin is melted at a temperature above the melting point and below the curing temperature and coated with a hot melt coater.
■Bステージの熱硬化性樹脂をN−メチル−2−ピロリ
ドン、ジメチルホルムアミド、ジメチルアセトアミド、
ケトン類などの有機溶剤にて溶解し、デイスペンサーの
ノズル等によってシリコンウェハの裏面にキャスティン
グ後、硬化温度以下の温度で乾燥させる方法。■ B-stage thermosetting resin is N-methyl-2-pyrrolidone, dimethylformamide, dimethylacetamide,
A method of dissolving it in an organic solvent such as ketones, casting it onto the back side of a silicon wafer using a dispenser nozzle, and then drying it at a temperature below the curing temperature.
上記熱硬化性樹脂はBステージのものを用いるもことに
よって、粘度や厚みの調整が容易となり、後の熱圧着工
程での硬化、固着が良好となる。このような熱硬化性樹
脂としては従来から接合剤として用いられているものが
使用できるが、好ましくはビスマレイミドとトリアジン
樹脂モノマーを主成分とする樹脂が挙げられる。このよ
うな樹脂は一般式、
(但し、Ar、は2価の芳香族基を示す)テ表すれるビ
スマレイミドと、一般式、N=c OArt Oc
=N
(但し、Ar2は2価の芳香族基を示し、前記Ar。By using a B-stage thermosetting resin, the viscosity and thickness can be easily adjusted, and curing and fixing in the subsequent thermocompression bonding process are improved. As such a thermosetting resin, those conventionally used as a bonding agent can be used, but preferably resins containing bismaleimide and triazine resin monomers as main components are used. Such a resin has a bismaleimide represented by the general formula (where Ar represents a divalent aromatic group) and a bismaleimide represented by the general formula, N=c OArt Oc
=N (However, Ar2 represents a divalent aromatic group, and the above-mentioned Ar.
と同一でも異なっていてもよい)
で表されるジーシアネート、および該ジーシアネートが
3分子以上環化重合したトリアジン環を有し、分子末端
にシアネート基を有するトリアジン樹脂とからなるもの
であり、代表的にはBTレジン(三菱瓦斯化学社製)が
挙げられる。(which may be the same as or different from) and a triazine resin having a triazine ring obtained by cyclopolymerizing three or more molecules of the dicyanate and having a cyanate group at the end of the molecule, A typical example is BT resin (manufactured by Mitsubishi Gas Chemical Co., Ltd.).
上記熱硬化性樹脂を形成する厚さは5〜100μm、好
ましくは10〜50μmの範囲とする。The thickness of the thermosetting resin is in the range of 5 to 100 μm, preferably 10 to 50 μm.
、5μmに満たない場合は接合強度が不充分となり、1
00μmを超える厚みでは熱伝導性が劣るようになり好
ましくない。, if it is less than 5 μm, the bonding strength will be insufficient, and 1
If the thickness exceeds 0.00 μm, the thermal conductivity will be poor, which is not preferable.
本発明においては以上のようにしてシリコンウェハの裏
面全面にBステージの熱硬化性樹脂層を形成したのち、
第1図(b)に示すように所定の大きさに切断し、第1
図(C)のように切断片(半導体チップ3)をグイボン
ダー等を用いてリードフレーム4のタブ上に載置、熱圧
着して半導体装置(第1図(d)参照)とする。熱圧着
時の加熱条件は熱硬化性樹脂の硬化温度(BTレジンの
場合は170’C)以上とし、好ましくは200〜35
0°C程度とする。In the present invention, after forming a B-stage thermosetting resin layer on the entire back surface of the silicon wafer as described above,
Cut it into a predetermined size as shown in Figure 1(b), and
As shown in FIG. 1C, the cut piece (semiconductor chip 3) is placed on the tab of the lead frame 4 using a glue bonder or the like and bonded by thermocompression to form a semiconductor device (see FIG. 1D). The heating conditions during thermocompression bonding should be at least the curing temperature of the thermosetting resin (170'C in the case of BT resin), preferably 200-35°C.
The temperature should be around 0°C.
本発明では接合剤にBステージの、熱硬化性樹脂を用い
て、予めシリコンウェハの裏面に形成しているので、上
記切断片をリードフレームに接着(仮着)する際のボイ
ド発生を防止することができる。また、接合剤としての
熱硬化性樹脂は切断前のシリコンウェハの裏面に予め設
けられているので、従来法と比べて均一な量および厚み
に接合剤層が形成され、接合強度不足や特性不良等の信
頼性の低下が防止できるものである。In the present invention, a B-stage thermosetting resin is used as the bonding agent and is formed on the back side of the silicon wafer in advance, thereby preventing the generation of voids when the cut pieces are bonded (temporarily bonded) to the lead frame. be able to. In addition, since the thermosetting resin as a bonding agent is previously provided on the back side of the silicon wafer before cutting, the bonding agent layer is formed in a uniform amount and thickness compared to conventional methods, resulting in insufficient bonding strength and poor characteristics. It is possible to prevent a decrease in reliability such as the following.
また、本発明においては前記熱硬化性樹脂に、金、銀、
銅、ニンケル、アルミニウム等の金属粉末を導電性充填
剤として配合し、導電性が必要な場合に用いることがで
きる。配合方法としては、例えば熱硬化性樹脂100重
量部に対して導電性充填剤を100〜900重量部混合
し、樹脂の融点以上、硬化温度以下の溶融状態にてミキ
シングロールやニーダ−等を用いて均一に混合したり、
適当な溶剤に樹脂を溶解したのち導電性充填剤と前記比
率で均一に混合する方法などが挙げられる。Further, in the present invention, the thermosetting resin may include gold, silver,
Metal powder such as copper, nickel, aluminum, etc. can be blended as a conductive filler and used when conductivity is required. As a compounding method, for example, 100 to 900 parts by weight of a conductive filler is mixed with 100 parts by weight of a thermosetting resin, and a mixing roll, a kneader, etc. are used in a molten state above the melting point of the resin and below the curing temperature. to mix it evenly,
Examples include a method in which the resin is dissolved in a suitable solvent and then uniformly mixed with the conductive filler at the above ratio.
〈実施例〉 以下に実施例を示し、本発明を具体的に説明する。<Example> EXAMPLES The present invention will be specifically explained below with reference to Examples.
実施例1
シリコンウェハ(直径12.5cm、 JIEcC35
0μm)の裏面全面に、100°Cに加熱して溶融させ
たBTレジン(三菱瓦斯化学社製、BT2070)を厚
さ25μmとなるようにホットメルトコータにて均一に
塗工、冷却してBステージの熱硬化性樹脂層が形成され
たシリコンウェハを作製した。Example 1 Silicon wafer (diameter 12.5 cm, JIEcC35
BT resin (manufactured by Mitsubishi Gas Chemical Co., Ltd., BT2070) heated to 100°C and melted is uniformly coated on the entire back surface of the 0 μm) using a hot melt coater to a thickness of 25 μm, and cooled. A silicon wafer on which a thermosetting resin layer for a stage was formed was fabricated.
次に、得られたシリコンウェハを3x3.3mm角の大
きさにグイシングし、得られた切断片(チップ)を4,
2−アロイからなるリードフレーム6タブ上にグイボン
ダーにてi!置、300°Cで10秒間熱圧着して半導
体装置を得た。Next, the obtained silicon wafer was diced into a size of 3 x 3.3 mm square, and the obtained cut pieces (chips) were cut into 4 pieces.
i! with Gui bonder on 6 tabs of lead frame made of 2-alloy! Then, thermocompression bonding was performed at 300° C. for 10 seconds to obtain a semiconductor device.
得られた半導体装置におけるチップとリードフレーム間
の接合強度をプッシュプルゲージによって測定したとこ
ろ、剪断応力は室温下で5 kg / cfflの値を
示し、実用的に充分な強度であることが判った。また、
接合剤とリードフレームとの接着界面にはボイドの発生
は見られず、均一な厚みにて接着していた。When the bonding strength between the chip and the lead frame in the obtained semiconductor device was measured using a push-pull gauge, the shear stress showed a value of 5 kg/cffl at room temperature, which was found to be sufficient strength for practical use. . Also,
No voids were observed at the adhesive interface between the adhesive and the lead frame, and the adhesive was bonded with a uniform thickness.
実施例2
BTレジン(三菱瓦斯化学社製、BT−2470)10
0gを、50gのメチルエチルケトンと50gのN−メ
チル−2−ピロリドンの混合溶剤にて均一に溶解させる
。次いで、3本ロールを用いて銀粉(描出金属社製、A
gc−L ) 400 gと充分に混練して導電性ペー
ストを作製した。Example 2 BT resin (manufactured by Mitsubishi Gas Chemical Co., Ltd., BT-2470) 10
0 g is uniformly dissolved in a mixed solvent of 50 g of methyl ethyl ketone and 50 g of N-methyl-2-pyrrolidone. Next, silver powder (manufactured by Kashitsu Kinzoku Co., Ltd., A
gc-L) 400 g to prepare a conductive paste.
得られたペーストをデイスペンサーのノズルを通してシ
リコンウェハ(直径12.5cm、厚さ350μm)の
裏面全面に乾燥後の厚みが10μmとなるように均一に
塗工し、150°Cにて30分間乾燥させてBステージ
の熱硬化性樹脂層が形成されたシリコンウェハを作製し
た。The obtained paste was applied uniformly to the entire back surface of a silicon wafer (diameter 12.5 cm, thickness 350 μm) through the nozzle of a dispenser so that the thickness after drying was 10 μm, and dried at 150°C for 30 minutes. A silicon wafer on which a B-stage thermosetting resin layer was formed was fabricated.
次に、得られたシリコンウェハを実施例1と同様にして
リードフレームのタブ上に載置し、250°Cで10秒
間熱圧着して半導体装置を得た。Next, the obtained silicon wafer was placed on the tab of a lead frame in the same manner as in Example 1, and thermocompression bonded at 250° C. for 10 seconds to obtain a semiconductor device.
得られた半導体装置におけるチップとリードフレーム間
の接合強度を実施例1と同様にして測定したところ、室
温下で13 kg/aft、 250°Cの温度下では
2 kg / c+flの剪断応力を示し、実用的に充
分な強度を示すものであった。When the bonding strength between the chip and the lead frame in the obtained semiconductor device was measured in the same manner as in Example 1, it showed a shear stress of 13 kg/aft at room temperature and 2 kg/c+fl at a temperature of 250°C. , which showed sufficient strength for practical use.
また、ボイドの発生も見られず、接合層の体積抵抗率を
四探針法にて求めたところ、1.0X10−′3Ω・c
mの値を示し、実用的iこ充分な導電性を示した。In addition, no voids were observed, and the volume resistivity of the bonding layer was determined by the four-probe method to be 1.0X10-'3Ω・c.
m value, and showed sufficient conductivity for practical use.
〈発明の効果〉
以上のように本発明の製造方法によれば、回路をパター
ニングしたシリコンウェハの裏面全面に、予めBステー
ジの熱硬化性樹脂層を形成しているので、所定の大きさ
のチップに切断した際に該樹脂層の厚みが各チップ間で
バラツキが少なく、リードフレームとの接合強度のバラ
ツキも防止でき信頼性が向上するものである。<Effects of the Invention> As described above, according to the manufacturing method of the present invention, a B-stage thermosetting resin layer is formed in advance on the entire back surface of a silicon wafer on which a circuit has been patterned. When the resin layer is cut into chips, there is little variation in the thickness of the resin layer among the chips, and variations in bonding strength with the lead frame can also be prevented, thereby improving reliability.
さらに、グイボンディング工程における従来の硬化時間
が削減できるので、作業効率が向上し自動化も容易とな
るものである。Furthermore, since the conventional curing time in the bonding process can be reduced, work efficiency is improved and automation is facilitated.
第1図(a)〜(d)は本発明の半導体装置の製造方法
を示す工程図である。FIGS. 1(a) to 1(d) are process diagrams showing the method for manufacturing a semiconductor device of the present invention.
Claims (4)
面に、半硬化状態の熱硬化性樹脂層を形成し、所定の大
きさに切断を行なったのち、切断片をリードフレームの
タブ上に載置、熱圧着することを特徴とする半導体装置
の製造方法。(1) Form a semi-cured thermosetting resin layer on the entire back surface of a silicon wafer patterned with a circuit, cut it to a predetermined size, and place the cut piece on the tab of a lead frame. A method for manufacturing a semiconductor device characterized by thermocompression bonding.
1)記載の半導体装置の製造方法。(2) Claim in which the thermosetting resin contains a conductive filler (
1) The method for manufacturing the semiconductor device described above.
面に、半硬化状態の熱硬化性樹脂層を形成してなる半導
体装置製造用シリコンウェハ。(3) A silicon wafer for manufacturing semiconductor devices, in which a semi-hardened thermosetting resin layer is formed on the entire back surface of a silicon wafer patterned with circuits.
3)記載の半導体装置製造用シリコンウェハ。(4) Claim in which the thermosetting resin contains a conductive filler (
3) The silicon wafer for manufacturing a semiconductor device as described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63152708A JPH01319948A (en) | 1988-06-21 | 1988-06-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63152708A JPH01319948A (en) | 1988-06-21 | 1988-06-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01319948A true JPH01319948A (en) | 1989-12-26 |
Family
ID=15546417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63152708A Pending JPH01319948A (en) | 1988-06-21 | 1988-06-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01319948A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002357900A (en) * | 2001-05-31 | 2002-12-13 | Mitsubishi Gas Chem Co Inc | Photosensitive resin composition |
| JP2002357899A (en) * | 2001-05-31 | 2002-12-13 | Mitsubishi Gas Chem Co Inc | Photosensitive resin composition |
| JP2007311728A (en) * | 2006-05-22 | 2007-11-29 | Sumitomo Bakelite Co Ltd | Semiconductor wafer having adhesive layer, semiconductor element, and semiconductor package |
| JP2008288571A (en) * | 2007-04-18 | 2008-11-27 | Hitachi Chem Co Ltd | Wafer with adhesive, method for producing the same, and adhesive composition |
| JP2010116531A (en) * | 2008-10-15 | 2010-05-27 | Hitachi Chem Co Ltd | Adhesive composition, adhesive layer, and multilayer package |
-
1988
- 1988-06-21 JP JP63152708A patent/JPH01319948A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002357900A (en) * | 2001-05-31 | 2002-12-13 | Mitsubishi Gas Chem Co Inc | Photosensitive resin composition |
| JP2002357899A (en) * | 2001-05-31 | 2002-12-13 | Mitsubishi Gas Chem Co Inc | Photosensitive resin composition |
| JP2007311728A (en) * | 2006-05-22 | 2007-11-29 | Sumitomo Bakelite Co Ltd | Semiconductor wafer having adhesive layer, semiconductor element, and semiconductor package |
| JP2008288571A (en) * | 2007-04-18 | 2008-11-27 | Hitachi Chem Co Ltd | Wafer with adhesive, method for producing the same, and adhesive composition |
| JP2010116531A (en) * | 2008-10-15 | 2010-05-27 | Hitachi Chem Co Ltd | Adhesive composition, adhesive layer, and multilayer package |
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