JPH0132717B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In television technology, the usual horizontal sync pulse Z, equalization pulse A and vertical sync pulse V
It becomes necessary to delay the complete composite synchronization pulse S by several scan lines in time.

In the device known from German Patent No. 1261876, three color signals R, G, B are recorded line-sequentially in the case of recording television signals by means of a narrow-band recording device, for example a video disk device, and the reproduction is performed using In this case, the scanning line delay lines are connected in series so that they can be used simultaneously again.
In this case, in addition to the continuous color signal,
The luminance signal Y present in each scan line is recorded.

In this case, the luminance signal is synthesized from a plurality of consecutive horizontal scanning lines during recording in order to improve the screen sharpness during playback (German Published Patent Application No. 2612619). In the case of the circuit shown in FIG. 4 of this publication, the recorded luminance signal is delayed by four scanning lines. Therefore, the complete composite synchronization signal S must also be delayed by four scanning lines. This is because if this is not done, the correspondence between the scanning line having the image signal and the vertical synchronizing pulse will no longer match, resulting in a vertical screen shift.

In this type of circuit, the composite synchronization signal S is routed via a separate path. This is based on two reasons. The first reason is that the composite synchronization signal S cannot be led through a circuit that averages the luminance signal over a plurality of scanning lines. Therefore, the composite synchronization signal S will be corrupted during the vertical blanking period. This is because in this case the signal S
This is because they are not necessarily equal in all scanning lines. The second reason is that it is preferable to remove the composite synchronization signal S from the luminance signal guided through the delay line. Next, the reason will be explained.

First, the amplitude region occupied by the original image signal is called the amplitude region BA amplitude between the black value and the white value.
The television signal occupies an amplitude range larger than this BA amplitude, since in the television signal the synchronization pulse exceeds the black value and reaches the so-called out-of-black value. Therefore, if the synchronizing pulse S is removed from the television signal, the remaining image signal will occupy only the original BA area. Therefore, the delay line only needs to process image signals between black and white.
It is not necessary to use it for large amplitude synchronization pulses. Therefore, the control area of the delay line can be used sufficiently well for image signals between black and white. A circuit of this kind is known from DE 2558168 A1.

Other signal processing circuits using comb filters also require this kind of delay of the composite synchronization signal S.

It is possible to delay the composite synchronization signal S with the same circuit elements as for the luminance signal, for example in an ultrasonic delay line or a bucket chain. However, this type of component is expensive and therefore increases the cost.

It is also known to delay this type of pulse signal using a shift register. However, in this case a large number of circuit stages with expensive components is required in order to accurately transmit pulses with different pulse widths of the television signal S over relatively long delay times. The main problem is that even when the shift clock is related to the H frequency (horizontal frequency), the following dangers arise. That is, the beginning of the pulse or the end of the pulse is placed between two clock periods;
There is then a risk that the reading into the shift register will deviate from its time alignment by the duration of one clock period. Therefore, the condition of the screen may be significantly impaired.

The object of the invention is to operate satisfactorily even for relatively long delay times, without being dependent on the respective television standard, and to be able to eliminate already existing pulse disturbances by regenerating the entire pulse. The purpose of the present invention is to propose a simple delay circuit for the synthesized synchronization signal S _p .

This problem is solved according to the invention by making it possible to obtain from the original synthetic synchronization signal a pulse with a frequency twice the horizontal frequency, a pulse with the same frequency as the horizontal frequency, and a pulse with the same frequency as the vertical frequency. This problem is solved by a configuration in which a new composite synchronization signal is generated that is shifted by a desired time from the pulses of .

Next, embodiments of the present invention will be described with reference to the drawings.

In the overall circuit of the invention shown in FIG.
S _p is played back and further shifted in time. A PLL circuit comprising a phase comparison stage 1, an oscillator 2, a frequency divider 3 and a filter element 4 first obtains control pulses 1/2H and H from the signal S _p . The oscillator 2 oscillates at a frequency 2·f _H which is twice the horizontal frequency. This corresponds to the duration of half a horizontal scan line period and is conventionally expressed as 1/2H. A frequency divider 3 for generating control pulses H is provided in the control loop. As a result, the phase of the control pulse H with respect to S _p is determined by phase comparison. The pulse signal used in the following explanation is shown in FIG.

The composite sync pulse signal of FIG. 2 has a variety of sync pulses, each having a different duration. That is, horizontal synchronization pulse Z with duration d, duration d/2
equalization pulse A, and a vertical synchronization pulse V of duration q.

In FIG. 1, pulse V _p is first separated from signal S _p . Pulse V is then derived from pulse V _p by means of counting stages 5 and 6 . The configuration of the counting stage depends on the respective requirements, ie, for example, how many horizontal scanning lines the -S signal is time-shifted with respect to S _p , or whether it is necessary to generate an additional V-blanking signal. It depends on whether it is there or not.

-S with respect to S _p by two horizontal scan lines, the control pulse 1/2H must be counted over approximately one sub-screen. The pulse V _p is derived from the wide V-pulse of the signal S _p . Thereby, pulses with half a period of n ₂ horizontal scan lines are counted until the beginning of the equalization pulse before the next screen change. Pulse V' therefore marks the position of the first equalization pulse of an undelayed screen change. Pulses having a period of half a period of n ₃ horizontal lines are then counted up to the first equalization pulse of the delayed screen change. A pulse V is therefore generated at the position of the equalization pulse before the delayed -S signal. A delayed composite synchronizing pulse signal -S is generated in a monostable circuit 7. This circuit is further controlled by a shift register 8 via the pulses shown in FIG.

Two counters are provided in FIG. Counter 5 supplies pulses V'. Counter 6 supplies the necessary pulses V to shift register 8 in order to generate a new signal -S at terminal 9.
This new pulse -S is delayed with respect to the signal S _p by, for example, two horizontal scan lines.

A composite synchronizing signal -S is generated in the circuit 7 in the lower part of the circuit of FIG. An embodiment of this circuit 7 is shown in FIG. The composite synchronization signal -S is divided into a control pulse H having a horizontal frequency from the output side of the frequency divider 3, a control pulse 1/2H having a frequency twice the horizontal frequency, that is, having half the horizontal scanning period of the oscillator. A pulse V having a vertical frequency from the frequency generator 6. Shift register 8 generates the necessary control pulses for circuit 7. This will be explained next using FIGS. 2 and 3. Furthermore, a frequency divider 10 and an OR gate 11 are provided.

The monostable multivibrator 28 shown in FIG. 3 generates the composite synchronization pulse -S shown in FIG. This composite synchronization pulse consists of a horizontal synchronization pulse Z with duration d, forward and backward equalization pulses A _V and A _H with duration p,
and a vertical synchronization pulse V _S having a duration q. The leading edge of all pulses is generated by the monostable multivibrator 28 from the trigger edge of the control pulse 1/2H. As a result, the leading edges of all pulses of pulse train -S are forced to have the same delay time relative to pulse 1/2H. Circuit elements R _d , R _q ,
C ₁ , C ₂ define the duration of the pulses generated by monostable multivibrator 28 . The switching of the pulse duration for generating the pulse train -S is effected by two switches 12, 13. Both switches are activated via gates 14,15. The resistor R _d sets the duration of the horizontal synchronization pulse Z, and the resistor R _q sets the duration q of the vertical synchronization pulse V _S .

FIG. 2 shows the control pulses applied to a total of six inputs of the circuit of FIG. While the control pulse D at the input of the gate 16 is equal to "1",
Both switches 12 and 13 become conductive. As a result, the time constant R _d ·(C ₁ +C ₂ ) determines the pulse width. During this time a horizontal synchronization pulse Z with duration d is
It is generated at terminal 2 in monostable multivibrator 12. Furthermore, the control pulse H is pulse 1/2
Only each second pulse of H is activated so that the monostable multivibrator 28 can be triggered.
Therefore, the pulse width d of the pulse Z is set by the resistor R _d . Control pulse P ₁ = “1” and P ₂ =
The switch 13 is shut off during the time when the signal is "1". As a result, the time constant becomes R _d ·C ₁ . C ₁
In the case of C ₂ , half the pulse width P=1/2·d is obtained for the generated front equalization pulse A _V .
During the time when the control pulse Q="1", the switch 12 is cut off and the switch 13 is turned on. Therefore, a time constant (C ₁ +C ₂ ) and (R _d +R _q ) necessary for generating a wide vertical synchronization pulse V _S occurs. Accurate setting of the pulse width is done by resistor _Rq . In this case, the pulse widths of the other pulses are not changed. While D=0, the control pulse H has no acting force because of the gate 16. As a result, an output pulse is generated every 1/2H of each pulse. In this way, the composite pulse -S shown in FIG. 2 is generated.

The control pulses P ₁ , Q, P ₂ , shown in FIG.
D is generated by shift register 8 shown in FIG. The voltages applied to the inputs A, B, C, D are delivered by the pulse V to the outputs P ₁ , Q, P ₂ , D of the shift register 8. Based on this, the forward equalization pulse A _V shown in FIG. 2 is generated. This equalized pulse is divided by frequency divider 1
It is input to 0 and counted here. The frequency divider 10 is
Send one pulse every time n ₁ pulse is counted. This pulse advances the shift register 8 by one step, whose serial input S _I is placed at zero potential. 625 - n ₁ =5 for the horizontal scanline standard. In this way, control pulses P ₁ , Q, P ₂ and D sequentially shift to "1". Finally, control pulse D="1" prevents frequency divider 10 from being supplied with further pulses -S via gate 11. The register 8 therefore remains in the above position and the counter remains in its zero position until a new pulse V is applied which starts a new course of the operating cycle as shown in FIG.

By means of counters 5 and 6 or only by counter 5, an arbitrary time shift is generated as a stepwise shift of 1/2H. - The stepless setting of the deviation between S and S _p can be carried out using the delay element 1 shown in FIG.
7, 18. For example, by the delay element 18 in front of the H input side of the phase comparison stage 1,
−S can be advanced more than S _p . This delay element is also important when generating an additional H blanking pulse starting before S _p . -S can be delayed with respect to S _p by means of a forward delay element 17 on the S _p input side of the phase comparator stage 1. When the signal -S is delayed by a bucket chain or a shift register, the number of pulses of various types of pulses included in the composite synchronization signal is automatically maintained. In the circuit described above, this number of pulses is previously given by counter 10 and optionally by counter 5. These counters will need to be adjusted when switching from the 625 to 525 horizontal scan line standard. This adjustment change can be made automatically.

FIG. 4 shows a circuit of this type. A pulse duration discrimination circuit 23 separates the equalization pulse or the wide vertical synchronization pulse V from the signal S _p . These pulses are counted and the counting results are input to the memory 24 after the counting is completed. This input is effected by an input acceptance pulse applied to another input of the memory 24. The memory 24 includes the frequency divider 10
and, if necessary, the frequency divider 5.

The television standard identification circuit shown in FIG. 5 is specially protected against disturbances. In this case, the number of horizontal pulses between two vertical pulses is
A number between the number of horizontal scanning lines of both standards for one field, for example between 263 and 312, is counted as more or less. In this case 263 and 312
The approximate arithmetic mean value of 288 is selected.

The output side of the counter 25 shifts to "1" every time 288 -H pulses following the trailing edge of the V pulse are counted.
This causes the counter 25 to pass through the NOR gate 26.
The input side of is cut off from subsequent -H pulses.
The counting state "1" at the output of the counter 25 is therefore retained until it is read into the D flip-flop 27 by the leading edge of the next V pulse. The trailing edge of the V pulse resets the counter 25 to "0" via the R input. As a result, counting is started anew. The embodiments described above are directed to the 625 horizontal scan line standard. D flipflop 2
The output state "1" of 7 causes n ₁ to be set to 5 and possibly n ₂ to be set to 625-5=620, for example. In the case of 525 horizontal scanning line standard, the counter output side, that is, D flip-flop 2
7 remains "0". In this case, n ₁ becomes 6,
and optionally n ₂ must be set to 525-6=519. Therefore, n ₃ , which defines the shift position of the start of the pulse V _S , is set to the same value for both television standards. comprising an automatic device for setting the counter 10 and optionally the counter 5;
The circuit for shifting the time of the -S signal supplies an output signal corresponding to the input signal in each case without changing the circuit. The circuit therefore operates like a conventional delay device in this respect. However, this circuit offers the advantage over conventional delay circuits of regenerating each pulse in its entirety and not transmitting pulse disturbances to the output.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a pulse signal waveform diagram explaining the operation of the circuit in FIG. 1, and FIG. 3 is an embodiment of the -S generating circuit in FIG. 4 and 5 illustrate an identification circuit for detecting the television standard of an input signal and automatically adapting the circuit to this standard. 1... Phase comparison stage, 2... Oscillator, 3... Frequency divider, 4... Filtering element, 5, 6... Counting stage, 7...
Synthetic synchronization signal generator, 8...Shift register, 1
0... Frequency divider, 23... Pulse duration identification circuit, 24... Memory, 25... Counter, 27...
D-Flip-flop, 28...monostable multivibrator.

Claims (1)

[Claims] 1. In a circuit for temporally shifting a composite synchronization signal S of a television signal, from the original composite synchronization signal S _p , a pulse 1/2H having a frequency twice the horizontal frequency, a horizontal frequency so that a pulse H having the same frequency and a pulse V having the same frequency as the vertical frequency are obtained;
A delay circuit for a television signal composite synchronization signal S, characterized in that a composite synchronization signal -S shifted by a desired time from these pulses is newly generated. 2. Pulse counting is used to identify what type of television standard the original composite synchronizing signal S _p belongs to, and the counter required for reproducing the composite synchronizing signal -S is Programming is performed based on the counting results, and in this case, the time-shifted composite synchronization signal -S and the original composite synchronization signal S _p
2. The delay circuit according to claim 1, wherein the delay circuit is programmed to match the number of synchronizing pulses of various types having different durations. 3. The delay circuit according to claim 2, further comprising a counter, the counter counting vertical synchronization pulses or forward or backward equalization pulses in the original composite synchronization signal S _p . . 4 Pulse for counting is pulse duration identification circuit 2
4. A circuit as claimed in claim 3, in which the synchronizing signal S _p is separated from the synthesized synchronization signal S p via a signal S p . 5. The delay circuit according to claim 2, wherein pulses H existing between two vertical synchronization pulses and having the same frequency as the horizontal frequency are counted. 6 Pulse H with the same frequency as the horizontal frequency
6. The delay circuit according to claim 5, wherein the delay circuit is extracted from an oscillator 2 whose phase is synchronized with the original synthetic synchronization signal S _p . 7 A time shift of an integer multiple of the period 1/2H, which is half of the horizontal scanning line period, is performed by counting by the counter 6, and the intermediate value of the time shift is continuously set by the delay elements 17 and 18. A delay circuit according to claim 1, wherein the delay circuit is adapted to be implemented.