JPH0136133B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Description of the technical field to which the invention pertains] The present invention relates to a data processing device having two cache memories.

[Description of prior art]

In a data processing device with a built-in program, instruction words and operands are stored in the main memory, so the access time to the main memory has a large effect on performance. Therefore, a method of providing a high-speed, large-capacity cache memory to equivalently reduce the main memory access time is also widely used. In recent years, a method has been proposed in which a cache memory for operands and a cache memory for instructions are provided separately to avoid conflicts in access to the cache memory.

Although this method is extremely effective, it requires the provision of two cache memories and involves an increase in the amount of metal. In addition, in a data processing device that uses a virtual address method, an address translation buffer TLB that converts a virtual address to a real address is used.
(TLANSLATION LOOKASIDE BUFFER)
A common method is to index the cache memory using the real address obtained by . If a virtual address system is applied to the two separate cache memories described above, it is necessary to provide a TLB for each cache memory, which also increases the amount of hardware.

Although such an increase in the amount of metal is essential from the viewpoint of improving performance, it has the disadvantage of increasing failure rate and decreasing operating rate.

On the other hand, in the data processing device market, a high-speed model alone lacks versatility, and a machine family including medium/low-speed models of the same architecture is required. Previously, medium-speed models were newly designed completely separately from high-speed models, which had the disadvantage of requiring a large amount of development cost and development time.

[Description of the purpose of the invention]

A first object of the present invention is to switch between addresses to be transferred to two cache memories and between output data according to the connection instruction information of the two cache memories, thereby enabling operation from using two cache memories. The purpose is to enable degeneration to operation with only one cache and improve operability against cache memory failures.

A second object of the present invention is to provide a high-speed data processing device that employs two cache memories, so that even when one cache memory is deleted, the remaining one remains
It is an object of the present invention to provide a data processing device having as a submodel a low-cost medium-speed data processing device that operates only with a cache memory.

[Structure of the invention]

(Means for Achieving the First Object) According to the present invention, in a data processing device having a cache memory, a data array for storing data retrieved from a main storage means, and a data array in the data array related to the data are provided. first and second cache memories each including a pair of address arrays storing a correspondence between a storage address and a storage address in the main storage means, and capable of responding to mutually different addresses; a data switching means for switching the output data of the first and second cache memories; and a data switching means for switching between the output data of the first and second cache memories; a configuration display means for displaying; and a request control for outputting an address for the unconnected cache memory to the other connected cache memory in response to the unconnected state of one of the cache memories displayed by the configuration display means. and, in response to the unconnected state of one of the cache memories displayed by the configuration display means, prohibits the data switching means from selecting the output data of the unconnected cache memory, and selects the output data of the other unconnected cache memory. A data processing device having a switching control means for permitting selection of output data of a certain cache memory is obtained.

(Means for Achieving the Second Object) Furthermore, according to the present invention, in a data processing device having a cache memory, a data array for storing data retrieved from the main storage means, and the data array regarding the data are provided. an address array that stores a correspondence between a storage address in the main storage means and a storage address in the main storage means;
a first cache memory and a second cache memory that is separable from the data processing device and that are capable of responding to mutually different addresses; and output data of the first and second cache memories. data switching means for switching the second cache memory; configuration display means for displaying whether the second cache memory is connected or disconnected to the data processing device; and the configuration display means displays the second cache memory. request control means for outputting an address for the unconnected cache memory to the cache memory in the first connected state in response to the unconnected state of the second cache memory; In response to the unconnected state of the second cache memory, the data switching means prohibits selecting the output data of the unconnected cache memory, and selects the output data of the cache memory in the first connected state. a switching control means for permitting the selection, and when the configuration display means displays a disconnected state of the second cache memory, the second cache memory is not installed in the data processing device. Accordingly, a data processing device can be obtained which can operate only with the first cache memory.

[Description of embodiments of this invention]

Next, the present invention will be explained in detail using the drawings. FIG. 1 is a block diagram showing an embodiment to which the present invention is applied. In FIG. 1, instruction register 1
holds an instruction word consisting of an instruction code part OPC, an address deviation D, and an index designation part X. The index designation section X of the instruction register 1 designates one entry of the index register 2, which consists of a plurality of entries. The address deviation D and the output of index register 2 are output to operand address adder 5.
, it is added to the base register 3 that holds the base address of the virtual space to generate a virtual operand address. The instruction pre-fetch counter 4 holds the relative address in the virtual space of the instruction word to be pre-fetched, and is incremented by 1 each time a fetch request is sent. The output of the instruction prefetch counter 4 is added to the base address held by the base register 3 in an instruction address adder 6 to generate a virtual address. The address switching circuit 7 outputs the output of the operand address adder 5 and the output of the instruction address adder 6 to the switching virtual address register 8. The output of the virtual address register 8 is connected to an address translation buffer (TLB) 9, which converts it into a real address, outputs it to the real address register 10, and stores it in the cache memory 11.
used for indexing. Address switching means 1
2 switches between the output of the operand address adder 5 and the output of the instruction address adder 6, and outputs it to the virtual address register 13. The output of the virtual address register 13 is the address translation buffer (TLB) 1
4 and is converted into a real address by the address conversion buffer 14, and the real address register 1
5. The output of real address register 15 is used to index cache memory 16. Here, address translation buffer (TLB) 9
and 14 each have the general configuration described in NEC Technical Report Vol. 35, No. 5, but since they have no direct relation to the present invention, detailed explanations will be omitted.

A detailed block diagram including the peripheral parts of the cache memory 11 and the cache memory 16 is shown in FIG. The real address register 10 and the real address register 15 each have a real page address 10a.
and 15a, column addresses 10b and 15b,
Holds intra-block addresses 10c and 15c. Column address 1 of real address register 10
0b is address array 1 of cache memory 11
The real page addresses stored in 01 are read for the number of levels. These read real page addresses are compared in parallel with the real page address 10a of the real address register 10 in the comparator group 103 to search for a match. The data in the data array 102 is read out using part of the column address 10b and block address 10c in the real address register 10, and the data for the obtained number of levels is read out by a selector controlled by the output of the comparator group 103. 1
05, and data is selected and output from the level corresponding to the comparator that has detected a match. If no match is detected, the real address held in the real address register 10 is sent to the storage control unit 18, and the operation continues while replenishing the data read from the main memory MM. Cache memory 16 is indexed by real address register 15. The cache memory 16 includes an address array 111, a data array 112, and a comparator group 11.
3 and a selector 115, whose connections and operations are similar to those of the cache memory 11. By having two cache memories in this manner, it is possible to obtain two different data, such as an operand and an instruction word, in one machine cycle.

Referring again to FIG. 1, the data output from the cache memory 11 is directly transferred to the arithmetic execution section 19. The switching circuit 20 switches the data outputs of the cache memory 11 and the cache memory 16,
It is supplied to the command buffer 21. Command Batsuhua 21
is a buffer memory that stores the instruction word transferred from the cache memory before the processing of the instruction existing in the instruction register 1 is completed. Similar to the switching circuit 20, the switching circuit 17 switches the data outputs of the cache memory 11 and the cache memory 16, and provides a path for transferring data to the instruction register 1 via the switching circuit 22, bypassing the instruction buffer 21. form.

FIG. 3 is a diagram showing a control circuit 100 relating to sending out a cache memory request in the embodiment shown in FIG. The operand fetch control unit 50 decodes the instruction word held in the instruction register 1 and outputs the control signal 7.
Outputs 0,71. In this figure, a memory request signal 70 and a branch target fetching display signal 71 indicating whether the memory request is a branch instruction or not are shown. The instruction fetch control unit 51 uses the instruction prefetch counter 4 to output an instruction fetch request 72 while managing the empty state of the instruction buffer 21. The diagnostic control unit 52 is in charge of collecting failure information of the data processing device, retrying commands, and controlling the configuration of the cache memory. This cache memory configuration control function uses signal lines 76 and 7 from cache memories 11 and 16.
7 and the system configuration information from an external device via the signal line 78, the function determines whether the cache memory is connected or disconnected, and outputs the determination result to the cache configuration display 53. be. The cache configuration display 53 receives the determination result from the diagnostic control section 52 and displays whether each of the cache memories 11 and 16 is connected or disconnected from the data processing apparatus. Output 7 of this cache configuration display 53
3 is sent to the request control section 54 and the switching control section 55. The request control unit 54 is a core part of the present invention. The request control unit 54 responds to various requests, a cache configuration display output 73, and signals 74 and 75 indicating that each of the two cache memories is in a request-acceptable state, and sends a request to both cache memories. A possible request is determined and notified to cache memory 11 via signal line 80 and to cache memory 16 via signal line 81. At the same time, in order to send the corresponding addresses to both cache memories, the request control unit 54 sends the switching circuit 7 via the control line 82 and the switching circuit 1 via the control line 83.
Control 2. In addition, when the cache memory request cannot be accepted or a request conflict occurs, the request control unit 54 sends a signal to the request source, that is, the operand retrieval control unit 50, via a signal line 8 to inform that the request cannot be sent.
4. Notify the instruction fetch control unit 51 via the signal line 85, and the notified control unit 50 or 51 maintains the state until it becomes possible to send the request. Switching control section 5
5 is a control signal 90 of the operand extraction control unit 50
and the output signal 73 of the cache configuration indicator 53.
in response to the signal of the switching circuit 1 via the signal line 92.
7 controls the switching circuit 20 via the signal line 93 to select appropriate data from the two cache memories.

A control flowchart of the request control section 54 is shown in FIG. The operation of the request control section 54 shown in FIG. 3 will be described below with reference to FIG. 4 as well. When the signal line 73 instructs the connection of the cache memory 16, the request sent from the operand retrieval control unit 50 via the signal line 70 is transferred to the cache memory according to the branch destination prefetch instruction sent via the signal line 71. 11 or cache memory 16. If the cache memory to be sent is in a state where requests cannot be accepted, the operand retrieval control unit 50 is notified via the signal line 84. Also, the operand address adder 5
The output address is sent to cache memory 11 or 16 via signal lines 82 and 83 by controlling switchers 7 and 12.
When the signal line 73 instructs disconnection of the cache memory 16, the request sent from the operand retrieval control section 50 is issued regardless of whether or not it is an instruction to preempt the branch destination.
Output to the cache memory 11. An instruction fetch request sent from the instruction fetch control section 51 is processed when the cache memory 16 is connected, and when a branch target prefetch instruction arrives from the operand fetch control section 50.
Sending is inhibited due to request sending conflict, and the instruction fetching control unit 51 is notified that the sending is not possible.
If a branch destination preemption instruction does not arrive, an instruction preemption request can be sent to the cache memory 16,
Sending of requests is controlled in accordance with a signal line 85 indicating the request sending enabled state of the cache memory 16. When the cache memory 16 is disconnected, the sending of the command retrieval request is suppressed by a request from the operand retrieval control unit 50, and when there is no such request, a signal line indicating the request-acceptable state of the cache memory 11 is used. The request is sent to the cache memory 11 in response to 76. In addition, in a state where sending is inhibited or reception is not possible, the signal line 85 is connected to the instruction fetch control unit 51.
Notify via.

A control flowchart of the switching control section 55 is shown in FIG. The operation of the switching control section 55 in FIG. 3 will be described with reference to FIG. 5 as well. Cash memory 16
When the cache memory 16 is disconnected, the switching circuit 17 and the switching circuit 20 are fixed to select the cache memory 11, and when the cache memory 16 is connected, the switching circuit 20 is fixed to select the cache memory 16. At the same time, the switching circuit 17 is enabled to select either the cache memory 11 or the cache memory 16 according to an instruction from the control line 90. Here, the control line 90 is used when fetching an operand by referring to data other than an instruction word, such as in an indirect address modification operation.

To be more specific, when only one cache memory is connected, this cache memory stores both operands and instruction words, whereas when cache memories 11 and 16 are connected together, this cache memory stores both operands and instruction words. If so, these cache memories 11
and 16 will share roles. That is, the cache memory 11 exclusively stores operands (including indirect words), and the cache memory 16 exclusively stores instruction words. Furthermore, during indirect word processing, the indirect word is read out along the path of cache memory 11→switching circuit 17→switching circuit 22→instruction register 1. When the number is less than this, the switching circuit 17 selects a path for fetching the instruction word from the cache memory 16. On the other hand, since the instruction buffer 21 does not store indirect words but only instruction words, the selection circuit 20 permanently selects the cache memory 16.

In the above explanation, the cache memory 16
However, by providing a switch similar to the switch 20 before the arithmetic execution unit 19, the cache memory 11 can be disconnected and the cache memory 16 can function as an alternative cache memory. be able to.

In addition, when the cache configuration display 53 permanently indicates that one of the cache memories is disconnected by the signal 78 (FIG. 3) from an external device, the cache configuration display 53 indicates that the disconnected cache memory Since all input and output signals are disconnected, the disconnected cache memory can be removed from the device. Similarly, address translation buffers, real address registers, and virtual address registers can also be deleted. This function allows a slower data processing device to be easily realized at a lower cost than a high speed data processing device having two cache memories.

Also, in response to address translation buffer failures,
By disconnecting the address translation buffer that has caused the failure, operability can be improved.

[Explanation of the effects of the invention]

As described above, the present invention has the effect of improving the operability of a data processing apparatus having two cache memories by providing the request control means and the switching control means.

Furthermore, by providing a request control means and a switching control means, the present invention can be used as a sub-model of a high-speed data processing device employing two cache memories.
This has the effect of easily realizing a low-cost, medium-speed data processing device that operates on a cache memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data processing device to which the present invention is applied, FIG. 2 is a detailed block diagram of the cache memories 11 and 16 shown in FIG. 1, and FIG. 3 is a control diagram of the data processing device of FIG. circuit 100
4 is a diagram showing a control flowchart of the request control section 54 of FIG. 3, and FIG. 5 is a diagram showing a control flowchart of the switching control section 55 of FIG. 3. 1...Instruction register, 2...Index register, 3...Base register, 4...Instruction counter, 5
...operand address adder, 6...instruction address adder, 7 and 12...address switching circuit, 8 and 13...virtual address register, 9 and 14...address conversion buffer, 10 and 15...real address register, 11 and 16...carrier Tsushiyu Memory, 17
and 20... switching circuit, 21... instruction buffer, 22
. . . switching circuit, MM . . . main memory, 50 . . . operand retrieval control unit, 51 . . . instruction retrieval control unit, 52 .

Claims (1)

[Scope of Claims] 1. In a data processing device having a cache memory, a data array for storing data retrieved from main memory means MM, a storage address in the data array regarding the data, and a storage address in the main memory means. First and second cache memories 11 each include a pair of address arrays that store correspondence with addresses, and are capable of responding to mutually different addresses.
and 16, data switching means 17 and 20 for switching output data of the first and second cache memories, and the first and second cache memories are respectively connected to the data processing device. configuration display means 53 for displaying whether the
and a request control means 5 for outputting an address for the unconnected cache memory to the other connected cache memory in response to the unconnected state of one of the cache memories displayed by the configuration display means.
4, in response to the unconnected state of one of the cache memories displayed by the configuration display means, prohibits the data switching means from selecting the output data of the unconnected cache memory and selects the output data of the other cache memory that is in the connected state; a data processing device having a switching control means 55 for permitting selection of output data of a cache memory; 2. In a data processing device having a cache memory, a data array for storing data retrieved from the main memory means MM, and a correspondence between a storage address in the data array and a storage address of the main memory means regarding the data are stored. a first cache memory 11 and a second cache memory 16 that can be separated from the data processing device, each including a pair with an address array and capable of responding to mutually different addresses; and data switching means 17 and 20 for switching the output data of the second cache memory and the second cache memory, and a configuration that displays whether the second cache memory is connected or disconnected to the data processing device. displaying means 53; and in response to the non-connected state of the second cache memory displayed by the configuration display means, outputting an address for the non-connected cache memory to the first cache memory in the connected state; a request control means 54 for controlling the second cache memory; and a request control means 54 for inhibiting the data switching means from selecting the output data of the unconnected cache memory in response to the unconnected state of the second cache memory displayed by the configuration display means. , a switching control means 55 for permitting selection of output data of the first cache memory in a connected state, and the configuration display means displays a non-connected state of the second cache memory. In this case, the data processing device is capable of operating only with the first cache memory without the second cache memory being installed in the data processing device.