JPH0140590B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a wire breakage detection device for a three-phase circuit. When detecting a single wire break in a three-phase circuit, for example, in a three-phase distribution line, distinguishing it from load switching or two-wire or three-wire break, the single-wire break can be reliably detected even when the load is a large proportion of the motor load. We are currently looking at a separate proposal for the configuration to make it possible.
No. 39218 (Japanese Unexamined Patent Publication No. 157326, 1982), Patent Application No. 157326
See No. 39219 (Japanese Unexamined Patent Publication No. 58-157327). ]． Figure 1 shows the configuration of this existing proposal, where 1 is a three-phase distribution line, 2 is a detection circuit that detects the positive sequence current I1 from the phase currents Ia, Ib, and Ic of distribution line 1, and 3 is a detection circuit that detects the negative sequence current I2. 4 is a detection circuit that detects the change ΔI1 in the positive sequence current, 5 is a detection circuit that detects the change ΔI2 in the negative sequence current, 6 is a first arithmetic comparison circuit, and 7 is a second arithmetic comparison circuit. It is a circuit. The first arithmetic comparison circuit 6 inputs the above-mentioned ΔI1 and ΔI2, calculates ΔI2/ΔI1, compares the calculated value with a reference value, and outputs when it is within the range of this reference value. In other words, as explained in the previous proposal, when either A, B or C phase is disconnected, ΔI2/ΔI1 is 1, a, a ² (however, a is a vector operator)

[Formula]) Therefore, as can be understood from the pie chart shown in Figure 2, the phase is at a maximum of ±30 degrees (in the figure) with 1, a, and a ² as the centers. ±25 degrees in example)
If the operating range is set to a range where the absolute value is greater than 0.5 (0.7 in the example in the figure),
If this operating range is set to the reference value,
When the value of ΔI2/ΔI1 is within the above operating range,
It becomes possible to detect a wire breakage in any one of the A, B, and C phases while distinguishing it from other faults. In this specification, ΔI represents a vector change including the phase and absolute value, |ΔI| represents the absolute value of this vector change, and Δ|I| represents a change in the absolute value. The latter two are therefore two color quantities. The first arithmetic comparison circuit 6 can reliably detect a line break when most of the load is a resistive load, but when the proportion of the motor load increases, the phase of ΔI2/ΔI1 at the time of a line break is no longer specified and deviates from the preset operating range. Therefore, under such load conditions, only the first arithmetic and comparison circuit 6 can distinguish a single wire break from other faults. Unable to detect. Therefore, a second arithmetic comparison circuit 7 is separately prepared. Here, when a wire is disconnected, both the positive-sequence and phase currents change, but in the case of a motor load, we focus on the fact that there is a difference in the amount of change between the positive-sequence current and the negative-sequence current.
When ΔI2/ΔI1| exceeds a certain value (for example, 2), it is assumed that a line break has occurred, and the ratio is calculated by the second calculation and comparison circuit 7, and the calculation result is compared with a certain value, It outputs an output when it exceeds a certain value. The ratio is greater than or equal to 1 when there is a disconnection that includes a motor load, but it differs depending on the ratio of the motor load. Generally, the larger the ratio of motor load is, the larger it becomes. Therefore, the ratio may be appropriately set depending on the motor load ratio. FIG. 3 is a pie chart showing the operating characteristics of the arithmetic comparison circuit 7 shown in FIG. As described above, when an output is output from either the first or second arithmetic/comparison circuits 6, 7, it can be considered that a line break has occurred. On the other hand, as mentioned above, ΔI1, ΔI2 and |ΔI1|, |
When detecting a line break using the ratio of ΔI2|, even when each of these values is extremely small, for example, even within the error range of the detection accuracy of each of these values, if the above ratio is satisfied, a line break is detected. It is possible that it may be detected as Therefore, it is necessary to eliminate misjudgments caused by such errors. To this end, it is possible to focus on the fact that the current in the disconnection layer decreases when a line is broken, and to use this as one of the elements for detecting that a line break has occurred when the amount of change in the phase current exceeds a certain value. Therefore, the changes in the phase currents Ia, Ib, and Ic of the A, B, and C phases Δ|Ia|, Δ|Ib
A calculation circuit 8 for calculating |, Δ|Ic| is prepared, and a level determination circuit 9 determines the level of its output. The level determination circuit 9 is configured to output an output when the level changes beyond a certain level.
This output becomes the input to the OR gate 10. Reference numerals 11 and 12 designate AND gates which take each output from the arithmetic and comparison circuits 6 and 7 as one input, respectively, and each of which receives the output from the OR gate 10 as another input. Each and gate 1
The outputs from 1 and 12 pass through delay timers 13 and 14 and become inputs to OR gate 15. delay timer 1
3 and 14 are provided so that it is assumed that a line break has occurred when the input to each AND gate 11 and 12 continues for a certain period of time or more. By using the output of the OR gate 15, it is possible to distinguish a wire breakage in any phase from other faults, and to detect it reliably even when the proportion of motor load is large. In the previously proposed configuration described above, the current detection condition at the time of a wire breakage is based on the decreasing change in the phase current by the arithmetic circuit 8, but the decrease in the phase current is not only caused by a wire breakage but also due to normal load fluctuations. Therefore, there is a possibility of erroneous detection simply based on the amount of change in phase current. This invention sets detection conditions for phase current reduction changes that are similar to the state of change in each phase current at the time of a wire break, rather than simply determining the level of the change in phase current. The purpose is to distinguish this from changes in phase current due to load fluctuations, thereby preventing false detection. The first condition for detecting changes in phase current in this invention focuses on the fact that in the case of a resistive load, when one wire is broken, the current decrease change in the disconnection layer is generally larger than the current decrease change in the other two phases. . That is, a
When the phase is disconnected, Δ｜Ia｜≧ΔIs Δ｜Ia｜≧Δ｜Ib｜, Δ
｜Ia｜≧Δ｜Ic｜(1) Also, when the b phase is disconnected, Δ｜Ib｜≧ΔIs Δ｜Ib｜≧Δ｜Ic｜, Δ
｜Ib｜≧Δ｜Ic｜(2) Furthermore, when c phase is disconnected, Δ｜Ic｜≧ΔIs Δ｜Ic｜≧Δ｜Ia｜, Δ
The condition can be |Ic|≧|Ib|(3). Here, Δ|Ia| is Δ|Ia|=|mIa|−|Ia|, and |Ia| is the absolute value of the phase current at the moment,
Also, |mIa| is the absolute value of the phase current a certain time before the current time. Therefore, when Δ|Ia|>0, it means a decrease in current, and when Δ|Ia|<0, it means an increase in current. The same applies to changes in other phase currents.
Furthermore, ΔIs is a set value greater than zero. The second detection condition is that it has been confirmed that as the motor load ratio increases, the phase current at the time of one line breakage tends to decrease for the breakage phase and increase for the other two phases. In other words, the change in phase current when one wire is broken is a positive value in the broken phase,
The other two phases have negative values. Therefore, when the a phase is disconnected, Δ|Ia|≧ΔIs, Δ|Ib|<0, Δ|Ic|<0
(4) Also, when the b phase is disconnected, Δ|Ib|≧ΔIs, Δ|Ic|<0, Δ|Ia|<0
(5) Furthermore, when c phase is disconnected, Δ|Ic|≧ΔIs, Δ|Ia|<0, Δ|Ib|<0
(6) should be the condition. The third detection condition is that in the case of a motor load, the phase currents of two phases other than the disconnection phase tend to increase with time immediately after the disconnection. That is, for example, when the a-phase is disconnected, the phase current of the b-phase gradually increases from time t ₀ immediately after the disconnection in FIG. 4. At times t ₀ , t ₁ , t ₂ , t ₃ ..., the increase value Δ|Ib
If | ₀ , Δ|Ib| ₁ , Δ|Ib| ₂ , Δ|Ib| ₃ ..., this value will gradually increase as time passes. A similar trend is followed in the case of an increase in the c-phase phase current. The same applies when other phases are disconnected. Therefore, when phase a is disconnected, Δ|Ib| ₀ +Δ|Ic| ₀ /Δ|Ib|i+Δ|Ic|i≦1(7
) When phase b is disconnected, Δ|Ic| ₀ +Δ|Ia| ₀ /Δ|Ic|i+Δ|Ia|i≦1(8
) Furthermore, when c phase is disconnected, Δ|Ia| ₀ +Δ|Ib| ₀ /Δ|Ia|i+Δ|Ib|i≦1(9
) can be used as the condition. However, i=1, 2, 3
etc. As a result of the above, when the conditions shown in equations (1) to (9) are satisfied, compared to the detection conditions for the phase current change in the previously proposed configuration, that is, the configuration shown in Fig. Detection becomes possible under sufficiently close conditions. In other words, malfunctions due to load fluctuations and the like can be sufficiently avoided. FIG. 5 shows an embodiment of the invention. Note that parts given the same reference numerals as in FIG. 1 indicate the same or corresponding parts. In the figure, Δ| from the arithmetic circuit 8
Outputs corresponding to Ia|, Δ|Ib|, and Δ|Ic| are given to determination circuits 21-23, determination circuits 24-26, and determination circuits 27-29. Judgment circuits 21 to 23
evaluates each of the conditions shown in equations (1) to (3), and outputs an output when the conditions are met. Judgment circuit 24-2
6 determines the conditions shown in equations (4) to (6), and outputs an output when the conditions are satisfied. Judgment circuit 27~
29 executes the calculations of equations (7) to (9), judges the conditions shown in these equations, and outputs an output when the conditions are satisfied. The first arithmetic comparison circuit 6 outputs the arithmetic comparison results for each of the A-phase to C-phase disconnections for each phase. The output for each phase is sent to the determination circuit 21 corresponding to that phase.
With each output from ~23, the AND gate 31
~33 inputs. The output from the second arithmetic comparison circuit 7 is connected to AND gates 34 to 36 whose inputs are the respective outputs from the determination circuits 24 to 26.
This is one other input. Thus, when one line is broken from the AND gates 31 to 33 in the resistance load, and from the AND gates 34 to 36 in the motor load, an output is output corresponding to the break phase. Note that instead of outputting an output for each phase from the first arithmetic comparison circuit 6, it may be configured to output an output even when any phase is disconnected as shown in FIG. It may also be given as one input. The determination circuits 27 to 29 include AND gates 34 to 3
After receiving the output from 6, execution of the calculation begins as described above. Since the output from the AND gates 34 to 36 can be regarded as a line break occurring in the motor load, the determination circuits 27 to 29 may perform calculations based on this. Each output from each judgment circuit 27 to 29 when the conditions shown in equations (7) to (9) are satisfied is the output from the AND gate 4 along with the output from the AND gates 34 to 36.
One input each from 1 to 43 is required. The output from each AND gate 41 to 43 is output from the delay timer 4.
The signal is input to the OR gate 47 through steps 4 to 46. On the other hand, each output of AND gates 31-33 is inputted to OR gate 51 via delay timers 48-50.
The output of both OR gates 47 and 51 is the OR gate 52.
is input. Therefore, by using the output of the OR gate 52, it is possible to detect the occurrence of a wire breakage regardless of whether the load is a resistive load or a motor load. Note that delay timers 44 to 4
6, 48 to 50 are for determining whether the above-mentioned conditions have continued for a certain period of time or more, and are for ensuring detection of a line break. In the above embodiment, the calculation of the changes in both the positive and negative phase currents is performed using ΔI2/ΔI1.
Alternatively, it may be performed using ΔI1/ΔI2,
[Patent Application No. 57-39219 (Japanese Unexamined Patent Publication No. 58-157327)
reference. ], in short, the ratio between the change in the positive-sequence current and the change in the negative-sequence current can be calculated and compared by the first and second arithmetic comparison circuits 6 and 7. However, in this case, the second
Naturally, the operating ranges shown in FIGS. 3 and 3 are different. Specifically, instead of the operating range shown in Fig. 2, the operating range is a range of a circle with radius r (for example, 0.5) centered on points 1, a ² , and a, and instead of Fig. 3, for example, radius (for example, 1/
2) may be set within the range of the circle as the operating range. As detailed above, according to the present invention, regardless of whether the load is a resistive load or a motor load, a single wire breakage is detected under conditions that are closer to the state of a single wire breakage than in the previously proposed configuration. Therefore, it is possible to reliably prevent erroneous detection due to load fluctuations, etc., as in the previously proposed configurations.

[Brief explanation of drawings]

Figure 1 is a block diagram of the previously proposed system, Figures 2 and 3
FIG. 4 is a pie chart showing the operating range, FIG. 4 is a characteristic chart showing changes in phase current, and FIG. 5 is a block diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Three-phase circuit, 8... Arithmetic circuit, 21-29... Judgment circuit, 31-26, 41-43... AND gate, 47, 51, 52... OR gate.

Claims (1)

[Claims] 1. An arithmetic circuit that detects a change in the absolute value of each phase current of a three-phase circuit by subtracting the absolute value of the phase current at a certain time from the absolute value of the phase current at a certain time before an arbitrary time; The change in the absolute value of the phase current is input, and for each phase, the change in the absolute value of the phase current is greater than or equal to the set value, and
A determination circuit that determines that the change in the absolute value of the phase current of the other two phases is greater than or equal to the change in the absolute value of the phase current, and a determination circuit that determines that the change in the absolute value of the phase current of the other two phases is greater than or equal to the set value A determination circuit that determines that the change in absolute value is negative, and a determination circuit that determines that the sum of the increases in the absolute values of the phase currents of the other two phases at a given time is the phase current of the other two phases before the time. a determination circuit for determining whether the absolute value is larger than the sum of increments, and the determination output of each of the determination circuits is used as one of the outputs for detecting occurrence of single wire disconnection.