JPH0141042B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplifier bias control device, and more particularly to a bias control device that automatically adjusts the idle current of an amplifier having an SEPP (single-ended push-pull) configuration.

The adjustment of the idle current, which is the DC bias of the output amplification element in a class B SEPP amplifier, is mainly done by manual adjustment using a temperature compensation element such as a varistor or thermistor and a variable resistor. Therefore,
It takes several minutes to several tens of minutes to reach a constant idle current value from the time the power is turned on, and it is also difficult to accurately match the idle current value to a desired setting value. Furthermore, there is also the drawback that so-called thermal distortion (thermal cross-modulation distortion) occurs due to fluctuations in the operating point due to signals.

An object of the present invention is to provide a bias control device that can stabilize a circuit by keeping the DC bias current of an amplifying element substantially constant.

The amplifier bias control device according to the present invention includes a resistive bridge circuit provided between the output electrode of the amplifying element and the circuit output, and the bridge circuit detects a voltage corresponding to the DC bias current flowing through the amplifying element, and outputs the detected voltage. and a reference voltage, and the DC bias of the amplifying element is controlled by the difference output.

The present invention will be explained below with reference to the drawings.

FIG. 1 shows a circuit diagram of an embodiment of the present invention, in which the signal input v _i passes through a variable bias circuit 1 that controls the DC bias of the amplification elements Q ₁ and Q ₂ , and then passes through the output amplification elements Q _{1 and} Q 2 . This is the base input for Q ₂ . Both amplifying elements Q ₁ and Q ₂ are emitter follower type and B
It has a class SEPP configuration, and both emitter output terminals are commonly connected via emitter resistors R _E and R _E1 , respectively, and the signal v ₀ ' at this common connection point d becomes the circuit output v ₀ via the resistor R ₃ . , a load such as a speaker (not shown) is push-pull driven through the circuit output terminal.
Resistors R _E and R ₃ and resistors R _E1 and R ₃ are amplification elements Q ₁ ,
It is connected in series between each emitter output terminal of Q ₂ and the circuit output terminal. Resistors R ₁ , R ₂ and R ₁₁ , R ₁₂ are provided in parallel with each of these series-connected circuits, and the resistors R ₁ and R ₂ are also connected to the resistor R ₁₁ .
R ₁₂ are connected in series between the emitter output terminals of the amplifier elements Q ₁ and Q ₂ and the circuit output terminal, respectively. Therefore, the resistances R _E , R ₃ , R ₁ and R ₂ also reduce the resistance
R _E1 , R ₃ , R ₁₁ and R ₁₂ constitute a bridge circuit, respectively. Here, the resistance R _E ,
R _E1 is the first resistor of the bridge circuit, and resistor R ₃ is the second resistor.
The resistors R ₁ and R ₁₁ are the third resistors, and the resistors R ₂ and R 11 are the third resistors.
_R12 corresponds to the fourth resistor.

One input of the level comparator 2 is derived from the common connection point C between the resistors R ₁ and R ₂ , and is also connected to the resistor R ₁₁ .
One input of the level comparator 3 is derived from the common connection point with _R12 . The reference voltage for both level comparators 2 and 3 is the common connection point between resistors R _E and R ₃ .
Voltages obtained by level-shifting the voltage v ₀ ′ up and down by ±V _b are used.

In such a configuration, the voltage V _ab between a and b (b is the circuit output point) during the half cycle when the transistor Q ₁ is on is V _ab = R _E (I _d + I ₀ ) + R ₃ · I ₀ ...(1). Here, I _d represents the idle current, and I ₀ represents the output current. Moreover, the voltage between c and _d is V _cd = R ₂ /R ₁ +R ₂・V _ab −R ₃・I ₀ =R ₂・R _E /R ₁ +R ₂ I _d +R ₂・R _E −R ₁・R ₃ /R ₁ +R ₂ I ₀ …
…(2) becomes. Therefore, assuming that the condition R ₂ · R _E = R ₁ · R ₃ , that is, the bridge equilibrium condition, is satisfied, then
Equation (2) is V _cd = R ₂・R _E /R ₁ +R ₂・I _d =R ₁・R ₃ /R ₁ +R ₂・I _d ……(
3) Therefore, by detecting the voltage between c and d, it is possible to detect the idle current I _d flowing through the amplifying element Q ₁ .

Since the two inputs to the level comparator 2 are vo'+V _cd and vo'+V _b , the comparison output from the comparator 2 becomes an error signal proportional to |V _b -V _cd |. Similarly, during the half cycle when transistor Q ₂ is on, the output of level comparator 3 is different from the error signal proportional to |V _b - V _cd | (e is the difference between resistors R ₁₁ and R ₁₂
). Therefore, if the variable bias circuit 1 is controlled in accordance with these error signals to adjust the bias between the bases of the output transistors Q ₁ and Q ₂ , negative feedback is generated so that the error signals become zero, and the idling is stopped. The current I _d is instantaneously set to a value determined by the reference voltage V _b .

FIG. 2 is a circuit diagram of another embodiment of the present invention,
Parts equivalent to those in FIG. 1 are designated by the same reference numerals. If we only mention the parts that differ from Figure 1,
The reference voltages of level comparators 2 and 3 are v _i ±V _b , and similarly in this example, the comparison output is |
It is proportional to V _b −V _cd | and |V _b −V _ed |, and automatic idle current adjustment is possible.

3 and 4 are circuit diagrams showing specific examples of the circuit shown in FIG. 1, and in each of these figures, equivalent parts are designated by the same reference numerals. In FIG. 3, level comparators 2 and 3 include differential transistors Q ₃ ,
It has a differential amplifier configuration with Q ₄ , Q ₅ , and Q ₆ ,
The differential outputs of these amplifiers 2 and 3 serve as control inputs of the variable bias circuit 1.

This circuit 1 has transistors Q ₇ and Q ₈ whose collectors are connected to the circuit input and whose bases are connected to _the circuit input via resistors _{R 4} and R ₅ , respectively. Level comparison outputs between the base and each collector are applied, respectively. By doing this, the voltage between the bases of the output transistors (Darlington connection configuration) Q ₁ and Q ₂ is controlled by the impedance of the transistors Q ₇ and Q ₈ , so that the error output from comparators 2 and 3 becomes zero. can be operated to set the idle current to a desired value.

In FIG. 4, level comparators 2 and 3 are differential amplifiers composed of differential transistors Q ₃ , Q ₄ and Q ₅ , Q ₆ , and the collector outputs of transistors Q ₃ and Q ₆ are common, and the transistors The collector outputs of Q ₄ and Q ₅ are common, and the variable bias circuit 1 is controlled by this pair of common outputs. This circuit 1 has transistors Q ₉ and Q ₁₀ connected between the bases of output transistors Q ₁ and Q ₂ and a connection point d, respectively.
The impedance of Q ₉ and Q ₁₀ is the same as that of transistor Q ₁₁
The idle current is adjusted under the control of a circuit consisting of ~ _Q14 . Therefore, a pair of error outputs are input to each base of transistors Q ₁₁ and Q ₁₃ .

FIG. 5 is a diagram showing a specific example of the circuit shown in FIG. 2, and equivalent parts are indicated by the same reference numerals in both figures. Similarly, the level comparators 2 and 3 are differential amplifiers made up of differential transistors Q ₃ , Q ₄ and Q ₅ , Q ₆ , and the variable bias circuit 1 is made up of differential transistors Q 3 , Q 4 and Q 5 , Q 6 .
It is a differential amplifier type consisting of Q ₁₅ , Q ₁₆ and Q ₁₇ , Q ₁₈ , and the circuit input is commonly applied to the bases of transistors Q ₁₅ and Q ₁₇ , and transistors Q ₁₆ ,
Each collector output of _Q18 is an output transistor _Q1 , _Q2
It is used as each base input. differential transistor
The collector loads of Q ₁₅ , Q ₁₆ and Q ₁₇ , Q ₁₈ are transistor Q ₁₉ , diode D ₁ and transistor
Q ₂₀ is a current mirror circuit consisting of a diode D ₂ , and the error output from the level comparators 2 and 3 controls the mirror current of each current mirror circuit to control the base potential of the transistors Q ₁ and Q ₂ . The desired idle current is set.

As described above, according to the present invention, the DC bias current of the amplification element can be controlled to be constant at all times, so there is no need to add a temperature compensation circuit such as a varistor, and no adjustment is required. Furthermore, a constant DC bias value is obtained immediately upon power-on, eliminating variations, and furthermore, thermal distortion due to temperature changes due to transient heat caused by signals, etc., is prevented.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing each embodiment of the present invention, FIGS. 3 and 4 are diagrams showing a specific example of the circuit in FIG. 1, and FIG. 5 is a specific example of the circuit in FIG. 2. It is a figure which shows an example. Explanation of symbols of main parts, 1...Variable bias circuit, 2, 3...Level comparator, _R1 to _R3 , _R11 ,
R ₁₂ , R _E , R _E1 ...Resistance for bridge circuit.

Claims (1)

[Claims] 1. First and second resistors (R _E and R ₃ ) connected in series between the output terminal of the amplification element and the circuit output terminal.
and third and fourth resistors (R ₁ and R ₂ ) connected in parallel to these resistors and in series with each other; Amplifier bias control including a variable bias circuit that detects the voltage between the connection points of the fourth resistors and controls the DC bias of the amplification element by using an error output corresponding to the difference between the detected voltage and a predetermined reference voltage. Device.