JPH0142014B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a common bus control system, and particularly to a common bus control method in an information processing system having a common bus that is exclusively shared by a plurality of control devices for data transfer and whose usage rights are centrally managed by a management device. Regarding the method.

FIG. 1 is a diagram showing an example of the configuration of an information processing system to which the present invention is applied. In FIG. 1, a central processing unit 1, a main memory 2, and input/output control units 3-1 and 3-2 are interconnected via a common bus 4. Data exchanged between the devices is transferred via the common bus 4. However, if multiple sets of data are transferred simultaneously via the common bus 4, confusion will occur, so the central processing unit 1 centrally manages the right to use the common bus 4. When the central processing unit 1 receives a data transfer request from any of the devices, if the common bus 4 is not in use,
The request source device is given the right to use the common bus 4, and the common bus 4 is blocked from data transfer requests generated from other devices until the data transfer is completed.

FIG. 2 is a diagram showing an example of a conventional common bus control method in the information processing system shown in FIG. In FIG. 2, for example, an input/output control device 3-1 as a control device, an input/output device (not shown) under management, and a main storage device 2 as a connected device.
A condition (transfer request condition) 31 that requires data transfer via the common bus 4 occurs between the two, and the flip-flop 32 is set. The flip-flop 32 sends a transfer request signal 41 to the common bus 4. Having received the transfer request signal 41 via the common bus 4, the central processing unit 1 as a management device sets the flip-flop 11 to display that the common bus 4 is in use, and uses known means to transfer the transfer request signal 41 to the input/output control unit 3--.
1 is given the right to use the common bus 4, and thereafter the common bus 4 is blocked in response to data transfer requests generated from other devices. The input/output control device 3-1 executes data transfer between the input/output device (not shown) under management and the main storage device 2, and when the data transfer is completed, the main storage device 2 sends a response signal 42 to the common bus 4. Send out. The central processing unit 1 receives a response signal 4 from the common bus 4.
2, it resets the previously set flip-flop 11, regains the right to use the common bus 4 given to the input/output control device 3-1, and disables the use of the common bus 4 from now on for new data transfer requests. Allow.

As is clear from the above description, in the conventional common bus use display method, the central processing unit 1 that manages the right to use the common bus 4 receives the transfer request signal 41 from the flip-flop 11 that indicates the use of the common bus 4. and reset by receiving the response signal 42. The above signal sequence is shown in FIG. 3a. Therefore, if the main memory device 2 becomes unable to send out the response signal 42 due to a failure or the like, the flip-flop 11 will not be reset and the central processing unit 1 will not be able to send the response signal 42 to the input/output control unit 3-1. The usage right cannot be regained at any time, and other data transfer requests cannot be satisfied. As a countermeasure against this, a time limit circuit 33 is provided in the input/output control device 3-1. The time limit circuit 33
When the transfer request condition 31 occurs, the flip-flop 32 is set and the transfer request signal 41 is sent out.
starts time measurement, and a response signal 4 is sent from the common bus 4.
2 is received, time measurement is stopped. If the response signal 42 is not received within a predetermined time limit T after the start of time measurement, the time limit circuit 33 outputs a time limit signal 43.
The time signal 43 sets the flip-flop 35 via the gate 34, which is rendered conductive by the transfer request signal 41, and causes the pseudo response signal 42' to be sent to the common bus 4. Upon receiving the pseudo response signal 42', the central processing unit 1 resets the flip-flop 11 as if it had received the response signal 42 sent from the main memory 2, and regains the right to use the common bus 4. On the other hand, in the input/output control device 3-1, the pseudo response signal 42' is sent to the flip-flop 32.
The transfer request signal 41 being sent is reset.
also stops, and the timer circuit 33 is also restored. Furthermore, a reset signal 44 is applied to the flip-flop 35 via an inverter 36 to reset it. The above signal sequence is shown in FIG. 3b. In this way, the pseudo response signal 42' is sent to the input/output control device 3-1.
It is necessary to prepare a means to send out the data, which may impair economic efficiency.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional common bus use display method as described above, and to cancel the common bus use display without providing means for sending a response signal.

This purpose consists of a plurality of control devices, connected devices, management devices, and a common bus that connects each of the devices, and when a transfer request signal is generated in one control device, a timer circuit operates within the device and This signal is detected by the management device, the common bus is blocked from transfer request signals from other control devices, and when the data transfer between the control device and the connected device is completed, control is performed by the response signal from the connected device. The transfer request signal is cut off within the device, the operation of the timer circuit is stopped,
When the management device detects disconnection of the transfer request signal, the blockage of the common bus is released, and if a response signal does not arrive within a certain period of time, the transfer request signal is disconnected by the time signal of the time limit circuit, and the control device detects the disconnection of the transfer request signal. This is achieved by a common bus control method characterized in that the blockage of the common bus is released by detecting a signal disconnection.

An embodiment of the present invention will be shown below with reference to FIGS. 4 and 5. FIG. 4 is a diagram showing a common bus control method according to an embodiment of the present invention in the information processing system shown in FIG. 1, and FIG. 5 is a diagram showing an example of the signal sequence in FIG. 4. In FIG. 4, a data transfer request condition 31 is established between an input/output device (not shown) managed by, for example, an input/output control device 3-1' as a control device and a main storage device 2 as a connected device. occurs and sets flip-flop 32. The flip-flop 3
2 sends a transfer request signal 41 to the common bus 4.
Upon receiving the transfer request signal 41 from the common bus 4, the central processing unit 1 as a management device sets the flip-flop 11 to indicate the use of the common bus 4.
The right to use the common bus 4 is given to the input/output control device 3-1' by known means, and the common bus 4 is subsequently blocked from data transfer requests generated from other devices. The input/output control device 3-1' executes data transfer between the input/output device (not shown) under management and the main storage device 2, and when the transfer is completed, the main storage device 2 responds to the common bus 4. A signal 42 is sent out.
When the input/output control device 3-1' receives the response signal 42 from the common bus 4, it applies a reset signal 45 to the flip-flop 32 through the gate 37 to reset it. When the flip-flop 32 is reset, the transfer request signal 41 being sent is stopped. In the central processing unit 1', the inverter 12 detects the stoppage of the transfer request signal 41 being received from the common bus 4, and applies a reset signal 46 to the flip-flop 11 to reset it. As a result of the above, the central processing unit 1' is connected to the input/output control unit 3-
The right to use the common bus 4 granted to the common bus 1' is regained, and the common bus 4 is
is allowed to be used. The above signal sequence is the fifth
Shown in Figure a. On the other hand, the transfer request signal 41 sent from the flip-flop 32 is also applied to the timer circuit 33 to start counting time. If the response signal 42 is not sent from the main storage device 2 due to a failure or other reason, the time limit circuit 33 outputs the time limit signal 43 after a predetermined time period T has elapsed. The time signal 43 causes a reset signal 45 to be applied to flip-flop 32 via gate 37, causing it to be reset. Thereafter, as described above, the transfer request signal 41 being sent to the common bus 4 is stopped, the flip-flop 11 of the central processing unit 1' is reset, and the central processing unit 1' regains the right to use the common bus 4. Note that the time limit circuit 33 is restored when the response signal 42 is received or when the transfer request signal 41 is stopped. The above signal sequence is shown in FIG. 5b.

As is clear from the above explanation, according to this embodiment, the central processing unit 1' resets the flip-flop 11 that indicates the use of the common bus 4 by stopping the transfer request signal 41 received from the common bus 4, and grants the right to use the common bus 4. Take it back. Therefore, if the input/output control device 3-1' that sent the transfer request signal 41 does not receive the response signal 42 within the predetermined time limit T, it only stops sending the transfer request signal 41 and sends a pseudo response signal etc. There is no need to install a means for sending out.

Note that FIGS. 4 and 5 are only one embodiment of the present invention, and for example, the management device that centrally manages the right to use the common bus 4 is not limited to the central processing unit 1'; The control device that is exclusively shared is the input/output control device 3-1' or the main storage device 2.
Although many modifications may be considered without being limited to the above, the effects of the present invention remain the same in any case. Further, FIG. 4 merely shows the principle of the present invention, and it goes without saying that many modifications may be considered in practical use.

As described above, according to the present invention, a management device that centrally manages the right to use a common bus operates an indication of the use of the common bus depending on the presence or absence of a transfer request signal sent from a control device that exclusively shares the common bus. Therefore, the configuration of the control device is simplified, and the economical efficiency of the information processing system can be promoted.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of an information processing system to which the present invention is applied, FIG. 2 is a diagram showing an example of a conventional common bus control method, and FIG. 3 is a diagram showing an example of the signal sequence in FIG. FIG. 4 is a diagram showing a common bus control method according to an embodiment of the present invention, and FIG. 5 is a diagram showing an example of the signal sequence in FIG. 4. In the figure, 1 and 1' are the central processing unit, 2
is the main memory, 3-1, 3-2 and 3-1' are input/output control devices, 4 is a common bus, 11, 32 and 35 are flip-flops, 12 and 36 are inverters, 31 is a transfer requirement, and 33 is a A time circuit, 34 and 37 are gates, 41 is a transfer request signal, 42 is a response signal, 42' is a pseudo response signal, 4
3 is a time signal, and 44, 45 and 46 are reset signals.

Claims (1)

[Claims] 1 Consists of a plurality of control devices, connected devices, management devices, and a common bus that connects each of the devices, and when a transfer request signal is generated in one control device,
A time circuit operates within the device, the signal is detected by the management device, the common bus is blocked from transfer request signals from other control devices, and when the data transfer between the control device and the connected device is completed, the signal is detected by the management device. , the transfer request signal is disconnected within the control device in response to a response signal from the connected device, the operation of the time limit circuit is stopped, and the blockage of the common bus is released by the management device detecting the disconnection of the transfer request signal, If a response signal does not arrive within a certain period of time, the transfer request signal is cut off by a time limit signal of a time limit circuit, and the blockage of the common bus is released when the control device detects the cutoff of the signal. Bus control method.