JPH0142019B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a vector processing processor that includes a plurality of parallel operation units and processes vector instructions.
When executing a conditional instruction, based on the number of ons in the vector length unit of the mask information given as information indicating whether to execute the instruction for each element, whether to execute it with a masked instruction or This invention relates to a method for selecting an instruction at the time of execution of a conditional instruction in which it is possible to select whether to perform vector length shortening processing or skip the instruction.

[Conventional background and problems]

FIG. 1 is a diagram showing an example of a processing system having a vector processing processor, FIG. 2 is a diagram conceptually explaining processing corresponding to vector instructions, and FIG. A diagram showing an example of the configuration of a compiler that generates and supplies a target program from a source program, Figure 4 is a diagram explaining how a source program is transferred to intermediate text, and Figure 5 is a diagram showing how a source program is vectorized. Figures 6 to 8 are diagrams explaining how to prepare a statement mask and path mask for a source program containing an IF statement so that it can be executed in parallel. be.

For example, as shown in FIG. 1A, elements a ₁ , a ₂ , . . . belonging to vector A and elements b ₁ , b ₂ , . . . belonging to vector B are added together to form element c _{1 .} , c ₂ , . . . , c 2 , . . . 1st
In the case shown in Figure A, mask element m ₁ ,
m ₂ , ..., and the first
Processing as generalized in FIG. B is performed.

A data processing system having a vector processing processor that performs the above processing has a system configuration as shown in FIG. 2 as an embodiment.
In the figure, reference numeral 1 is a main storage device, 2 is a memory control device, 3 is a vector processing processor, 4 is a channel processor, 5 is a large storage device, 6 is a scalar processing circuit section, 7 is a vector processing circuit section, 8- 0,8
-1, ... are floating point data registers, 9
-0, 9-1, ... are vector registers that can each store a plurality of data (element data), and 10-0, 10-1, ... are vector registers that can each store a plurality of mask data (mask element data). ); 11 is a vector length register in which information on the number of elements to be stored in each vector register is set; 1;
Reference numerals 2-0 and 12-1 represent memory access pipelines, 13 an addition/subtraction pipeline, 14 a multiplication processing pipeline, 15 a division processing pipeline, and 16 a mask processing pipeline.

When a vector processing processor as described above executes a process, a given source program is compiled into a form suitable for execution by the processor to generate a target processor. FIG. 3 shows the configuration of a compiler that performs the compilation.

In FIG. 3, 17 is a source program stored in a large storage device, 18 is a compiler,
19 is an object program compiled and stored on a large storage device; 20 is a source interpretation section; 21 is a storage allocation section; 22 is a vectorization section; 23 is an intermediate text optimization section; 24 is a register usage determination section; 25 represents a target program output section.

A compiler 18 takes in a source program 17 from a large storage device and generates a desired target program 19. At this time, each of the illustrated units performs the following processing.

That is, the source interpreter 20 takes in the source program 17 from the large storage device, performs sentence interpretation, and develops it into intermediate text. For example, if the source program is as shown on the left side of FIG. 4, it is developed into intermediate text as shown on the right side of the figure. Storage area allocation part 2
1 allocates addresses within the storage area corresponding to various data appearing within the program. Vectorization unit 22
detects loop structures in the program, recognizes parallel executable parts, and changes intermediate text as shown in FIG. The intermediate text optimization unit 23
At the intermediate text level, optimization is performed to effectively utilize a vector processing processor as shown in FIG. The register use determining unit 24 allocates resources (registers) on the vector processing processor to data appearing in the intermediate text. Then, the target program output unit 25 outputs the machine instruction words to the large storage device and performs optimization at the instruction word level.

The compiler for operating the vector processing processor has the configuration shown in Figure 3.
A program that does not have an IF statement in its loop structure can be processed in a parallel executable format as conceptually shown in FIG. However, when a source program as shown in FIG. 6 is given, the loop structure contains "IF(A(I).GT.
B(I)) GO TO 50'', such loop configurations have traditionally been treated as not being able to be executed in parallel. However, in the case of this program, the destination of the IF statement is stopped within the loop, and the method uses statement mask mi to instruct whether or not to execute each statement in the program for each individual process. It was found that parallel execution was possible by adopting . A compiler processing method for providing the sentence mask mi has already been proposed as a prior invention (Japanese Patent Application No. 57-31198) by the same applicant as the present application. The outline thereof will be explained below with reference to FIGS. 6 to 8.

The program shown in FIG. 6 generally instructs the following processing. That is, it instructs to repeatedly execute statements ₁₀ to ₇₀ until the value of I changes from "1" to "N", and during that time, a certain I is executed by statement ₂₀ .
If A(I) is greater than B(I) for the value of , then statement ₅₀
, and according to statement ₄₀ , for a certain value of I, B(I)
If is greater than Y, it instructs to jump to statement ₆₀ . For example, if the above statement mask corresponds to statement ₃₀ and instructs to execute the statement ₃₀ when the condition is other than "A(I).GT.B(I)", the IF statement will be It becomes a form that disappears like this.

Figure 7 shows what kind of statement masks are applied to each of the statements ₁₀ to ₇₀ that make up the program shown in Figure 6.
An explanatory diagram explaining how to give m ₁₀ to m ₇₀ is shown.

In the case of statement ₁₀ , it is necessary to execute for all I, regardless of the value of I. From this, the sentence mask m ₁₀ is φ (empty). Also for sentence ₂₀
As m ₂₀ , it becomes φ. The route from statement ₂₀ to statement ₅₀ is taken when the condition "A(I).GT.B(I)" of statement ₂₀ is met, and the bus mask P ₂₀ , ₅₀ is used for the path.
As P ₂₀ , ₅₀ = A(I). GT.B(I) is given, and similarly, P ₂₀ , ₃₀ = ₂₀ , ₅₀ is given as the path mask P ₂₀ , ₃₀ . From this result, the sentence mask m ₃₀ corresponding to sentence ₃₀ is m ₃₀ = ₂₀ , ₅₀ .

The sentence mask m ₄₀ for sentence ₄₀ is the same as m ₃₀ . In the same way, pass masks P ₄₀ , ₆₀ and
P ₄₀ and ₅₀ are given as shown, and the sentence mask m ₅₀ is
This is the logical sum of the path masks P ₂₀ , ₅₀ and P ₄₀ , ₅₀ . And the sentence masks m ₆₀ and m ₇₀ become φ.

When such a statement mask mi is given, the program shown in FIG. 6 becomes a form that does not include an IF statement and can be executed in parallel, like the program shown in FIG. 8. In FIG. 8, ":M ₂ " and ":M ₅ " shown with ":" may be considered to be sentence masks for the corresponding sentences.

In this way, in general, (i) a statement mask is given to the i-th statement as the statement mask mi corresponding to each statement in the loop including the IF statement, and (ii) the i-th statement is
If the ith statement is not an IF statement, give the path mask Pi,i+1 and the value mi to the path toward the (i+1)th statement; (iii) If the ith statement is an IF statement, then When the condition of the IF statement is Ci, give mi・AND.Ci as the path mask Pik to the path to the kth sentence that is the destination to jump to when the condition is met, and (iv) When the th sentence is an IF statement, mi・AND・ is given as a path mask Rik for the path to the kth sentence that is the jump destination when the condition Ci of the IF sentence is not met. , () In giving the above sentence mask m _i , examine the above path mask and perform a logical OR on the path mask Pli corresponding to the path leading to the i-th sentence, that is, m _i = U l Pli (l≠i), and compile in such a way that the range of parallel execution is increased even when an IF statement is included.

Execution of a conditional instruction based on such mask information takes time equal to the length of the spectrum, regardless of the state of the mask. However, there is a problem that some instructions have a very small number of masks turned on, or instructions with all masks turned off, resulting in wasted execution time.

[Purpose of the invention]

The present invention is based on the above considerations, and includes:
It is an object of the present invention to provide a conditional instruction execution time selection method that can reduce the execution time of instructions with a small number of ons by recognizing the number of ons in a mask.

[Structure of the invention]

The execution-time selection method for conditional instructions is used in a data processing system that has a vector processing processor that is equipped with multiple parallel processing units and processes vector instructions. Once the mask information indicating whether to execute the command or not and the number of mask ons in vector length units are set, the number of mask ons is checked and the condition is set that the number of mask ons is 0. Then, on the condition that the number of on masks is smaller than a predetermined threshold, the execution of the relevant instruction is skipped, and on the condition that the number of mask ons is smaller than a predetermined threshold, a vector length shortening processing instruction is used to extract only the part where the mask is on, create new vector data, and perform vector operations. Then, the result of the vector operation is taken into the part where the mask is on, and the operation on the element where the mask is on is performed using a masked instruction on the condition that the number of mask ons is greater than a predetermined threshold. It is characterized in that it is configured to perform.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 9 is a diagram showing the configuration of one embodiment of the present invention.
0 is a diagram explaining the conditional instruction execution method used in the present invention, FIG. 11 is a diagram showing vector text corresponding to the conditional instruction execution method shown in FIG. 10, and FIG. Masks to which the invention is applied
FIG. 13, which is a diagram showing an example of register settings, is a diagram illustrating the flow of processing when executing an instruction according to the present invention. In the figure, 26 is an instruction buffer register, 27 is a decoder, 28 is a mask register (MR), 29 is a matching circuit, and 30
3 is a comparison circuit, 31 is a threshold setting unit (THRESHOLD), 32 and 33 are inverters, 3
4 is a branch processing section, 35 is a branch processing section for mask processing, and 36 is a branch processing section for compression/diffusion processing.

In FIG. 9, the mask register 28 is written with mask information for each vector length as well as information indicating the number of mask ONs (MSR; Mask Status Register), and the mask register 28 is used to store the instructions stored in the instruction buffer register 26. is set based on the mask definition command decoded by the decoder 27. The matching circuit 29 checks whether the contents of the MSR in the mask register 28 are 0 or not in accordance with the execution command from the decoder 27, and returns 0 (Yes).
In the case of 0, the branch processing section 34 is operated, and when it is not 0, the comparator circuit 3 is operated through the inverter 32.
Operate 0. The branch processing unit 34 performs skip processing without executing instructions.
That is, here, when the conditional instruction is executed, the MSR
If the content of is 0 (an instruction with a mask that is all off), the instruction is not executed. Comparison circuit 30 compares mask register 28 with
This is to check whether the content of the MSR is greater than or equal to the threshold value, and if the content of the MSR is greater than or equal to the threshold value, the branch processing unit 35 to mask processing is operated, and if not, it is branched to compression/diffusion processing. Processing section 36
make it work. Branch processing unit 35 to mask processing
is configured to perform processing that employs a masked calculation method, and branch processing unit 36 to compression/diffusion processing is configured to perform processing that employs a compression/diffusion method. Next, these methods will be explained.

In addition to masked vector operations, vector processing processors have vector length shortening instructions that are suitable for processing conditional statements such as IF statements. The present invention is implemented using this vector length shortening processing instruction, and below, an example using one of them, a compression/spreading instruction, will be explained as a representative example.
In a masked instruction (conditional instruction), for example, in the case of VT1←VT2 OP VT3; mt (mt is mask information indicating a condition), the operation on that element is performed depending on the contents of mt (on or off). Decide whether to proceed or not. However, it takes the same amount of time to execute elements that are not executed. On the other hand, for compression/spreading instructions, for example, VT2'comp ←---- VT2:mt VT3'comp ←---- VT3:mt VT1'←----VT2' OP VT3' VT1exp ←---- VT1 ′:mt comp ←―――― indicates the compression of vector data, and exp ←―――― indicates the spread of vector data.

In some cases, compression extracts only the part where the contents of mt are on and creates new vector data (VT
2', VT3'), and the diffusion involves taking in the contents of VT1' into the part where the contents of mt are on.
The calculation at this time can be performed using the number of turns on mt as the vector length. FIG. 10 shows the conditional operation, for example, Ai+Bi:mi:i=1, 2, . . . 8. In FIG. 10, A shows a masked operation method using masked instructions,
B shows a compression/spreading method using compression/spreading instructions. Comparing these two methods, the compression/diffusion method requires pre- and post-compression and diffusion processing as auxiliary operations, which takes time; however, the execution of the calculation itself is ).
It is effective when the true rate is small. On the other hand, the masked calculation method takes the calculation time equal to the vector length, but
Since there is no auxiliary operation, it is effective when the true rate is high. FIG. 11 shows an example of vector text that employs these methods. In FIG. 11, A shows an example where the masked calculation method is used, and B shows an example where the compression/spreading method is used.

FIG. 12 shows an example of mask register settings to which the present invention is applied. In FIG. 12, mask registers MR0 to MR3 have information MSR0 to MSR3 indicating the number of mask ONs, showing an example of a vector length of 6.
For example, in the case of mask register MR1, it is executed using a masked instruction, and the mask register MR1 is executed using a masked instruction.
In the case of MR2, the content of MSR2 is 0, so it is skipped, and in the case of mask register MR3, the content of MSR3 is very small compared to the vector length of 6, so it is executed using a compression/spreading instruction.

Next, the flow of processing when executing a conditional instruction is shown in Section 13.
This will be explained with reference to the figures.

Set information to mask registers (MR, MSR). Perform the following processing.

Check whether MSR=0.

If Yes, the process is skipped and the process ends; if No, the process is performed.

If the threshold is vector length * γ (γ < 1),
Check whether the content of MSR is greater than the threshold.

If Yes (true rate is high), process is performed, and if No (true rate is low), process is performed.

Execute using masked instructions.

Compress and spread data using compression/spreading instructions.

As mentioned earlier, according to , the execution time is proportional to the vector length, but according to , the execution time is proportional to the true rate plus α (the time required for auxiliary operations of compression and diffusion). It takes time.

Also, mask register MR to MSR
If the hardware does not allow this to be set at the same time as the mask register MR, then the mask register MR is set.
It is also possible to issue an instruction to count the number of ON bits of MR and perform processing on behalf of the software.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the execution time of instructions with a low true rate and instructions with all masks off can be shortened, and the processing efficiency of a data processing system can be improved. can.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of a processing system having a vector processing processor, Fig. 2 is a diagram conceptually explaining processing corresponding to vector instructions, and Fig. 3 is a diagram showing an example of a processing system having a vector processing processor. A diagram showing an example of the configuration of a compiler that generates and supplies a target program from a source program, Figure 4 is a diagram explaining how a source program is transferred to intermediate text, and Figure 5 is a diagram showing how a source program is vectorized. Figures 6 to 8 are diagrams explaining how to prepare a statement mask and path mask for a source program containing an IF statement so that it can be executed in parallel. 9th
The figure shows the configuration of one embodiment of the present invention, Figure 10 is a diagram explaining the conditional instruction execution method used in the present invention, and Figure 11 shows the conditional instruction execution method shown in Figure 10. FIG. 12 is a diagram showing an example of mask register settings to which the present invention is applied, and FIG. 13 is a diagram illustrating the flow of processing when executing an instruction according to the present invention. 1...Main storage device, 2...Memory control device, 3
...Vector processing processor, 4...Channel
Processor, 5...Large storage device, 6...Scalar processing circuit section, 7...Vector processing circuit section, 8-0 to 8-n...Floating point data register, 9
-0 to 9-n...vector register, 10
-0 to 10-n...mask register, 11
...Vector length registers, 12-0 and 12-1...
...Memory access pipeline, 13...Addition/subtraction pipeline, 14...Multiplication processing pipeline, 15...Division processing pipeline, 16...Mask processing pipeline, 17...Source program, 18...Compiler , 19...Objective program, 20...Source interpretation unit, 21...Storage area allocation unit, 22...Vectorization unit, 23...Intermediate text optimization unit, 24...Register usage determination unit,
25...Object program output unit, 26...Instruction buffer register, 27...Decoder, 28...
Mask register (MR: Mask Register), 2
9... Matching circuit, 30... Comparison circuit, 31... Threshold value setting section (THRESHOLD), 32 and 33... Inverter, 34... Branch processing section, 35... Branch processing section to mask processing, 36... Branch processing unit for compression/spreading processing.

Claims (1)

[Claims] 1. In a data processing processor having a vector processing processor that is equipped with a plurality of parallel calculation units and processes vector instructions, the vector processing processor determines whether or not to execute the instruction for each element when executing a conditional instruction. When the mask information indicated and the number of mask ons in vector length units are set, the number of mask ons is checked, and on condition that the number of mask ons is 0, execution of the instruction is skipped; Under the condition that the number of on masks is smaller than a predetermined threshold, a vector length shortening processing instruction is used to extract only the part where the mask is on, create new vector data, and perform vector operations.
After that, the result of the vector operation is imported into the part where the mask is on, and on condition that the number of mask ons is greater than a predetermined threshold, the masked instruction is used to perform the operation on the element where the mask is on. An execution-time instruction selection method for conditional instructions, characterized in that: