JPH0149068B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a biphasic mark modulation circuit that modulates a data signal into a biphasic mark and outputs the modulated signal.

BACKGROUND ART In recent years, with the development of electronic technology, there is a tendency for various types of information to be digitally recorded at high density.
For example, in a video tape recorder, the sound quality of an audio signal is improved by recording the audio signal on a magnetic tape in a pulse code modulated state. In this case, if information is recorded on a recording medium such as a magnetic tape or a magnetic disk while being pulse code modulated, the following problems will occur.

(A) If the same code continues, it becomes extremely difficult to extract the clock component.

(B) Intersymbol interference increases when sign reversals are severe.

(C) The difference between the number of "1s" and the number of "0s" becomes a DC component, and this DC component adversely affects the servo system responsible for the recording medium drive system.

A modulation method called Bi-Phase-Mark has been proposed to solve these problems. The signal modulated by this biphase mark method is composed of a synchronization signal section and a data signal section, and the synchronization signal section is a 3-bit signal whose polarity is inverted every 1.5 bits. Here, the polarity of the synchronizing signal changes depending on the content of the data signal located immediately before it, and if the immediately preceding data signal is "1", it becomes "L" as shown in Figure 1a. The signal starts from , and the previous data signal is “0”.
If it is, the requirement is that the signal starts from "H" as shown in FIG. 1b. Next, the data signal generated following this synchronization signal is a signal with one bit as one unit, and it is always inverted between bits, and a "1" signal is inverted at the center of the bit. , the "0" signal is required not to be inverted at the center of the bit. In other words,
When representing a “0” signal, the previous signal is “0”
When the signal is "1", the state is as shown in FIG. 2a, and when the previous signal is "1", the state is as shown in FIG. 2b. Further, when representing a "1" signal, when the immediately preceding signal is "0", the result is as shown in FIG. 2c, and when the immediately preceding signal is "1", the state is shown in FIG. 2d. The signals modulated into the states shown in FIGS. 2a to 2d are sequentially sent out in predetermined block units following the synchronization signal (FIGS. 1a and 1b).

However, the above-mentioned biphase mark modulation has the problem that the modulation circuit becomes extremely complicated and expensive because it requires high-speed processing while satisfying extremely complicated conditions.

DISCLOSURE OF THE INVENTION Accordingly, it is an object of the present invention to provide a biphase mark modulation circuit that is simple in construction and inexpensive to manufacture.

In order to achieve this object, the biphase mark modulation circuit according to the present invention is constructed by combining a counter and a gate circuit in a special configuration.

A circuit constructed in this manner can be constructed easily and inexpensively without using a special, complicated, and expensive circuit such as a microcomputer. Further, the circuit according to the present invention has various excellent effects such as high-speed processing of data signals due to its fast operation.

BEST MODE FOR CARRYING OUT THE INVENTION FIG. 3 is a circuit diagram showing an embodiment of a biphasic mark modulation circuit according to the present invention. In the figure, 1 is a clock pulse CP which is reset by a block synchronization signal generated for each predetermined block and has a period of 1/2 of the bit period.
The first one generates a 15-bit signal B every time it counts.
This 1.5-bit signal B is a counter, and this 1.5-bit signal B is used as an AND gate 2 for matching with the block synchronization signal A.
By resetting the first counter 1 again via the 3-count operation, the 3-count operation is sequentially repeated. A second counter 3 generates a synchronization end signal C indicating the end of the synchronization signal period by counting the 1.5-bit signal B by two after being cleared by the block synchronization signal A; AND gate 2 and second counter 3 receive 1.5 bit signal B indicating 1.5 bit period.
and a synchronization signal generation control circuit 4 that generates a synchronization end signal C indicating the end of the synchronization signal period.
Reference numeral 5 denotes a mode switching circuit which generates a synchronous generation period signal D and an asynchronous generation period signal E indicating the generation period of the synchronous signal, and is a flip-flop which takes the block synchronous signal A as a set input S and the synchronous end signal C as a reset input. It is constituted by a circuit 6. 7 is a bit clock generation circuit which receives the clock pulse CP as an input;
A divide-by-2 circuit 8 generates a bit clock pulse F by dividing the frequency of the bit clock pulse F by two, and a first one circuit generates a bit start signal G that is triggered by the rising edge of the bit clock pulse F and indicates the start point of each bit period. The bit clock pulse F supplied via the yacht multivibrator circuit 9a and the inverter 10
A second one-shot multivibrator circuit 9b generates a bit center signal H indicating the center portion of each bit cycle when triggered by the second one-shot multivibrator circuit 9b. Reference numeral 11 denotes a NAND gate which receives the bit start signal G and the asynchronous signal generation period signal E, and 12 generates the asynchronous signal generation period bit start signal I by inverting the output signal of the NAND gate 11.
13 is an inverter that generates a bit center signal H.
This is a NAND gate which receives as input the synchronous signal generation period signal E, and generates the asynchronous generation period bit center signal J. And these nand gate 1
1, 13 and the inverter 12 are the first logic circuit 1
4. Reference numeral 15 denotes a second logic circuit, which is composed of a NOR gate 17 which receives as input the asynchronous generation period bit center signal J and the data input signal K supplied via the inverter 16, and receives the input data signal K. Only the bit center signal J during the "1" period is sent out as the input data bit center signal L. Reference numeral 18 denotes coincidence detection means 100, which is composed of an inverter 19 that inverts the 1.5th bit signal B and outputs it to the NAND gate 20, a NAND gate 20 that receives this inverted output and the synchronous generation period signal D as input, and an asynchronous generation period bit. A NOR gate 21 which receives the start signal I and the input data bit center signal L as inputs, and an AND gate which generates the inverted position signal M by receiving the output signal of the NAND gate 20, the output signal of the NOR gate 21, and the block synchronization signal A as inputs. 22. Reference numeral 23 denotes a flip-flop circuit which generates a biphasic mark modulated signal N subjected to biphasic mark modulation by being triggered by the inversion position signal M.

In the biphase mark modulation circuit configured in this way, the fourth
When the negative polarity block synchronization signal A shown in FIG.
Counters 1 and 3 are cleared, and flip-flop circuit 6 of mode switching circuit 5 is set. Here, after the first counter 1 is cleared, it counts the clock pulses CP, and when the counted value reaches "3", it generates a 1.5-bit signal B of negative polarity. Since this 1.5-bit signal B resets the first counter 1 itself via the AND gate 2, it is generated from the first counter 1.
As shown in Figure 4c, the 1.5-bit signal B is 3 times the clock pulse CP from the generation of the reset signal A.
This will continue to occur every pulse. In this case, since the bit period of the data signal is twice the period of the clock pulse CP, the 1.5-bit signal B has a period 1.5 times the bit period of the data signal. The 1.5-bit signal B generated in this way is counted in the second counter 3,
When this count reaches "2", a synchronization end signal C is generated indicating that the 3-bit period, which is the synchronization signal generation period, has ended.

The flip-flop circuit 6 of the mode switching circuit 5 is set by the block synchronization signal A.
It is reset by the synchronization end signal C. As a result, the set output terminal Q of the flip-flop circuit 6 generates a synchronous generation period signal D indicating the generation period of the synchronous signal, as shown in FIG. 4d, and the reset output terminal generates an asynchronous generation period signal B. Figure 4 e
This is generated as shown in .

On the other hand, 2 constituting the bit clock generation circuit 7
The frequency divider circuit 8 sequentially divides the frequency of the clock pulse CP by two to generate a bit clock pulse F having a period twice that of the clock pulse CP, as shown in FIG. 4f. This bit clock pulse F is supplied to the first one-shot multivibrator circuit 9a, and is triggered by its rising edge to generate a narrow bit start signal G shown in FIG. 4G. Further, the second one-shot multivibrator 9b is triggered by the rising edge of the bit clock pulse F supplied via the inverter 10, thereby generating a bit center signal H indicating the center portion of each bit. The bit start signal G is matched with the asynchronous generation period signal E in the NAND gate 11 constituting the first logic circuit 14, and is further inverted in the inverter 12, so that it becomes the asynchronous generation period bit start signal I. It is output as shown in Figure 4 i. Further, the bit center signal H is determined to match the asynchronous generation period signal E in the NAND gate 13, so that it is generated as the asynchronous generation period bit center signal J as shown in FIG. 4J.

On the other hand, when the input data K shown in FIG. Noah Gate 17 after being reversed in
The input data bit center signal L shown in FIG. 4 is generated by determining the coincidence with the asynchronous generation period bit center signal J. The input data bit center signal L and the asynchronous generation period bit start signal I generated in this way are sent to the third logic circuit 18.
is taken out through the Noah Gate 21 that constitutes the
A NAND gate 20 determines whether the output signal of the inverter 19 that inverts the 1.5-bit signal B and the synchronization period signal D match. Then, by determining the coincidence between the coincidence signal which is the output signal of the NOR gate 21 and the NAND gate 20 and the block synchronization signal A in the AND gate 22, the inversion position signal M of the output signal is generated as shown in FIG. generated. By triggering the flip-flop circuit 23, the inversion position signal M generated in this way is converted into an inversion position signal M as shown in FIG. 4n.
A biphase mark modulation signal N is generated which is inverted every time . In this case, the first 3-bit period of the biphase mark modulation signal N is the synchronizing signal part, and as explained in FIGS. It becomes a signal. The part following this synchronization signal part is the data part, and when the input data A is "0", as described in FIG. 2 a and b,
The signal is inverted every bit period, and when the input data A is "1", the signal is inverted at the center of one bit period, as described in FIG. 2c and d.

In a circuit configured in this way, biphase mark modulation can be easily and reliably performed at high speed with a simple circuit configuration without using a complicated and expensive circuit such as a microprocessor. . Further, in the present invention, since the synchronization signal can also be generated by simultaneous processing, the processing is simplified.

[Brief explanation of drawings]

1a, b and 2 a to d are waveform diagrams for explaining biphasic mark modulation, FIG. 3 is a circuit diagram showing an embodiment of a biphasic mark modulation circuit according to the present invention, and FIG. 4 a to d n is a waveform chart showing the operation of each part of the circuit shown in FIG. 3. 4...Synchronizing signal generation drive circuit, 5...Bit switching circuit, 7...Bit clock generation circuit, 14,
15, 18...first to third logic circuits, 23...flip-flop circuit, 100...coincidence detection means (inverter 19 and NAND gate 20).

Claims (1)

[Scope of Claims] 1. A 1.5-bit signal is generated every three clock pulses based on the generation time point of a block synchronization signal generated for each predetermined block unit, and the generation time point of the block synchronization signal is used as a reference point. a synchronization signal generation drive circuit that generates a synchronization end signal at the time when six pulse periods of the clock pulse have elapsed; and a synchronization generation period that indicates a period from the time when the block synchronization signal is generated to the time when the synchronization end signal is generated. a mode switching circuit that generates an asynchronous generation period signal indicating a period other than the signal and the synchronous generation period; and a mode switching circuit that generates a bit start signal and a bit center signal at the rising and falling points of a bit clock signal obtained by dividing the frequency of the clock pulse by two. a bit clock generating circuit; a logic circuit; a logic circuit for generating an input data bit center signal by determining a match between a "1" signal of the input data supplied with one cycle of the bit clock signal as one bit signal period and the asynchronous generation period bit center signal; 2, a coincidence detection means for outputting a coincidence signal by determining coincidence between the 1.5-bit signal and the synchronous generation period signal; A third logic circuit that generates an inverted position signal by calculating an AND with a center signal, and a flip-flop circuit that inverts its output and sends out a biphase mark modulation signal every time the inverted position signal is supplied. A bi-phase mark modulation circuit characterized by: