JPH0150140B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for verifying the level of a phase pulse signal when receiving a phase pulse signal injected into a channel at a predetermined phase angle on an AC voltage wave such as a low voltage distribution line. be.

A phase pulse signal is a signal that causes a steep voltage fluctuation on an AC voltage wave by instantaneously shorting lines between lines via a capacitor and inductance. As shown in FIG. 1, the phase pulse signals 1, 1' are separated from the AC voltage wave 2 at the receiver, and their levels 3, 3' vary greatly depending on the distance from the oscillator. In current receivers, the reception threshold level 4 is constant as shown in FIG. 2, so the subsequent vibrations of the phase pulse signal 1'
may be greater than the reception threshold level 4, so that in addition to the signal pulse 6, a ghost pulse 7 is generated. The phase pulse signals 1, 1' are
One cycle of the AC voltage wave 2 is divided into a predetermined phase width and is injected into one channel assigned to a plurality of channels set, thereby transmitting it to the receiver. The subsequent oscillations 5 of the pulse signal 1' are assigned to the channel next to the channel CH ₁ as shown in FIG.
If the signal enters CH ₂ and ghost pulse 7 is generated on channel CH ₂ , a reception malfunction will occur.

An object of the present invention is to provide a method for verifying the level of a phase pulse signal that can prevent the generation of ghost pulses due to subsequent vibrations.

The present invention will be explained below with reference to FIGS. 4 to 6. According to the method of the present invention, as shown in FIG. 4, reception threshold levels 8, 8' corresponding to the levels of phase pulse signals 1, 1' are maintained until a predetermined time period T has elapsed. As a result, the level of the subsequent vibration 5 becomes lower than the reception threshold level 8', so that the ghost pulse 7 is not generated and only the signal pulse 6 can be detected.

FIG. 5 shows a specific example of a level verification circuit implementing the method of the present invention. This operation will be explained with reference to FIG. Input terminal connected to power distribution line, etc.
An alternating voltage wave 2 carrying a phase pulse signal 1 is input from t ₁ , and the phase pulse signal 1 is separated from the alternating voltage wave 2 by a high-pass filter 9 consisting of a resistor R ₀ and a capacitor C ₀ . A threshold level generation circuit 10 consisting of resistors R ₁ to _{R o+1} divides a threshold level reference voltage V _s by resistors R ₁ to _{R o+1} to generate n threshold level values. _L1 ～
_Lo is set and inputted to the negative input terminals of the comparators IC ₁ to _{IC o} of the comparison circuit 11, respectively. On the other hand, phase pulse signal 1 is input to the plus input terminal of each comparator IC ₁ to _{IC o} . The reception threshold level determination circuit 12 includes (n-1) R-S flip-flops.
The R-S flip-flops FF ₁ to FF _{o-1 are} reset before the phase pulse signal 1 _is input. Therefore, high level signals are applied from the reset output terminal to the AND gates G ₂ -G _o of the signal pulse selection circuit 13, respectively. When the instantaneous level of the phase pulse signal 1 exceeds the lowest threshold level value L _o , the comparator IC _o sends a high level signal to the AND gate G _o , so the AND gate G _o transmits the high level signal. It is output from the output terminal _t2 via the OR gate 14. Next, when the instantaneous value level of phase pulse signal 1 exceeds the threshold level value L _o-1 , the comparator IC _o-1
sends a high level signal to AND gate G _o-1 ,
AND gate G _o-1 outputs a high level signal from output terminal t ₂ via OR gate 14 . At the same time, the high level signal of the comparator IC _o-1 is applied to the set input terminal S of the R-S flip-flop FF _o-1 , and the R-S flip-flop FF _o-1 enters the set state, so its reset output The output from the terminal becomes low level, and the output of AND gate G _o also becomes low level. In this way, the instantaneous value level of phase pulse signal 1 is set to the threshold level value.
Every time L _o to L ₂ is exceeded, the AND gate that outputs a high level signal is sequentially switched from AND gate G _o to AND gate G ₂ , and R -
S flip-flops FF _o-1 to _{FF 2} are sequentially set. This allows the threshold level value
Each time the instantaneous value level of the phase pulse signal 1 exceeds L _o -L ₂ , the threshold level values L _o -L ₂ are switched as reception threshold levels.
When the instantaneous value level of phase pulse signal 1 reaches the maximum when it exceeds the threshold level value _L2 , and then decreases, if the instantaneous value level becomes less than the threshold level value _L2 , the output of comparator _IC2 Since the signal becomes low level, the output signal of AND gate _G2 becomes low level, and the high level signal outputted from output terminal _t2 also falls to low level. The high level signal output from the output terminal _t2 becomes the signal pulse 6. The signal pulse 6 is input to a pulse delay circuit 15, and after a predetermined time period T has elapsed since the rise of the signal pulse 6, the pulse delay circuit 15 sends a reset signal to the R-S flip-flops FF ₁ to FF _o-1 all at once. Reset these.
As a result, the reception threshold level returns to the lowest threshold level value L _o .

Before the predetermined time period T elapses, that is, while the R-S flip-flops FF _o-1 to _{FF 2} are held in the set state, the instantaneous value level of the phase pulse signal 1 rises due to the subsequent vibration 5. Also, since the signals sent from the R-S flip-flops FF _o-1 to F ₂ to the AND gates G ₃ to _{G o} are low level, the AND gate G ₃
~G _o is closed and does not pass the high level signal from comparator IC _o ~ _{IC 3} . Therefore, the ghost pulse 7 does not appear at the output terminal _t2 . In this way, the threshold level value _L2 is held as the reception threshold level during the predetermined time period T.
Before the predetermined time period T elapses, the threshold level value
When phase pulse signal 1 having an instantaneous value level exceeding L ₂ is input, AND gate G ₂ outputs a high level signal, which is output as signal pulse 6 from output terminal t ₂ .

If each channel formed in one cycle of the AC voltage wave 2 is assigned to a transmitter with a different distance, the predetermined time period T shown in FIG. Set to a time limit. In addition, in the case of a terminal encoder system in which several channels are assigned to the same transmitter for transmitting coded addresses or information, the predetermined time limit T is set to the time limit for these channels, for example, 10 channels. be done.

In the present invention, multi-stage threshold level values are set, and each time the instantaneous value level of the phase pulse signal exceeds each threshold level value sequentially from the lowest threshold level value, the threshold level Switch the value as the reception threshold level,
Since the reception threshold level is held and returned to the lowest threshold level value after a predetermined time period, generation of ghost pulses due to subsequent vibrations can be prevented when receiving the phase pulse signal. Furthermore, by maintaining the same reception threshold level for a predetermined time period, the S/N ratio can be kept constant within the predetermined time period. Further, by returning the reception threshold level to the lowest threshold level value after a predetermined time period, even an attenuated phase pulse signal from a distant transmitter can be received after a predetermined time period.

[Brief explanation of drawings]

Figures 1A and B are waveform diagrams showing the level of the phase pulse signal, Figures 2A and B are waveform diagrams showing the generation of ghost pulses due to subsequent vibrations, and Figures 3A and B.
4A and 4B are waveform diagrams illustrating the level verification method of the present invention, and FIG. 5 is a circuit diagram of a specific example of a level verification circuit that implements the method of the present invention. , FIG. 6 is a waveform diagram of each part. 1, 1'... Phase pulse signal, 2... AC voltage wave, 3, 3'... Level, 5... Subsequent vibration, 6...
...Signal pulse, 8,8'...Reception threshold level, _L1 to _Lo ...Threshold level value.

Claims (1)

[Claims] 1 In a level verification method in which a phase pulse signal separated from an AC voltage wave is compared with a reception threshold level and a waveform with a level higher than the reception threshold level is detected as a signal pulse, a multi-stage threshold level value is used. is set, and each time the instantaneous value level of the phase pulse signal exceeds each threshold level value sequentially from the lowest threshold level value,
A method for level testing a phase pulse signal, characterized in that the threshold level value is switched and held as a reception threshold level, and after a predetermined time period, the reception threshold level is returned to the lowest threshold level value. .