JPH0151218B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to clock signal phase synchronization in digital signal transmission.

In high-efficiency digital signal transmission, code transmission is performed using pulses shaped into a small roll-off waveform, so a sample timing shift on the receiving side will rapidly deteriorate the characteristics. Traditionally, sample timing, or clock signal extraction, involves rectifying an input signal to generate a clock component, and passing it through a narrowband bandpass waver to extract the clock.

In recent years, receivers have become increasingly digital, and the need for digital processing for clock signal extraction has increased. For digitizing receivers, direct control of sample timing is preferred rather than extraction of the clock signal. An object of the present invention is to provide a simple sample timing control circuit suitable for digital processing. The present invention comprises: a first sampler that samples a complex input signal at zero phase of a clock signal; a second sampler that samples the complex input signal at a π phase of the clock signal; and a complex code of the output of the first sampler. a differentiator that detects a difference between a value of the output of the discriminator one cycle before and a current value; a real part of each of the output of the differentiator and the output of the second sampler;
and a product-sum circuit that obtains the sum of products of imaginary parts, and changes the phase of the clock signal according to the output of the product-sum circuit, so that the complex input signal is sampled by a first sampler at an optimal sampling phase. This is a clock phase control circuit characterized in that it controls the clock so that Next, the present invention will be explained in detail with reference to the drawings.

Figure 1 a is a binary digital signal of +1 and -1,
Alternatively, it shows the eye pattern of the real part or imaginary part of the demodulated signal of the quadrature phase modulated wave. Figure b shows the sample timing, which every T seconds indicated by the arrow corresponds to the widest eye opening time of the eye pattern. Figure c shows a timing signal that is shifted by a π phase (180°) from the previous one. At this timing, the previous a
When a waveform is sampled, it takes approximately three values: a value of ±1 when the transmission code does not change before and after that, and a value near zero when it changes conversely. Although the waveform in Figure 1a depends on the roll-off rate and bit pattern of the transmitted pulse, it is roughly similar to that in Figure 2a.
Even if it is simplified like this, there is no problem on average. Therefore, consider the case where the sample timing is delayed by Te seconds as shown in Figure 2b.
Then, the eye opening becomes narrower from W ₀ to W ₁ , while
The value obtained by sampling the input signal at the timing shown in FIG. 2c also changes from a value near zero to a larger value. This time, except when the transmission code does not change before and after the arrow c, if it changes from -1 to +1, the sample value at c will take a positive value e _(-+) , and conversely from +1 to - When it changes to 1, it takes a negative value e _(-+) . As a result, by knowing the transmission codes before and after the timing c, it is possible to detect a shift in sample timing. Therefore, the timing of Figures 1 and 2 b is now based on the data sample.
Timing c is also called zero cross detection timing.

The above explanation can be summarized as follows. First, if the data before and after the zero-cross detection timing remains unchanged, timing shift information cannot be obtained from the input waveform sample value at the zero-cross detection timing. Second, when the data changes from -1 to +1, the timing shift information is proportional to the input waveform sample value at the zero cross detection timing. Thirdly, when the data changes from +1 to -1, the timing shift information is proportional to the value of the opposite polarity of the input waveform sample value at the zero cross detection timing.

FIG. 3 shows a concrete example of the principle of timing deviation information detection described above. In the figure, 1 is the first sampler that samples the input signal at the data sample timing, 2 is the second sampler that samples the input signal at the zero cross timing, and 3 is the sign identification of the output of the first sampler and ±1. A discriminator to output,
4 is a differentiator for detecting changes in data as explained above, and is composed of a -beat delay circuit 40 and a subtracter 41. 5 is a multiplier that takes the product of the differentiator output and the second sampler output. 6 is a clock signal generator that includes a high-speed pulse oscillator 61, a counter 60 that counts down the same pulses, and an adder 62 that supplies the initial value of the counter as the sum (N+α) of a predetermined constant N and a control signal α. It is completed. When the counter counts down to zero, it outputs a sample pulse to the outside, sets the output value of the adder 62 as the next initial value, and starts counting down again. This shows that the control signal applied to input terminal 104 can control the output phase of the sample pulse from the clock signal generator. 7 is a T/2 delay circuit for generating zero cross detection timing from data sample timing.

Now, considering the output of the multiplier 5, if the data does not change, the output of the differentiator 4 is zero, so
Zero is output to the output terminal 101. -1 to +
When the data changes to 1, the output of the differentiator 4 becomes 2, and 2× (zero cross sample value) appears at the output terminal 101. Conversely, when the data changes from +1 to -1, The output of the differentiator 4 is −2, and −2×(zero cross sample value) is represented at the output terminal 101. This shows that timing shift information in the correct direction appears at the output terminal 101 for any data change.

FIG. 4 shows the relationship between the average output e of the output terminal 101 and the timing Te. The reason why the characteristics are disconnected at Te = ±T/2 in the same figure is because the data sample timing is close to the zero cross timing of the waveform, which causes a sudden polarity reversal. do. In the above explanation, the input signal has been treated as a real number, but there may be a case where two series of independent data exist in the real part and the imaginary part, such as a demodulated signal of quadrature phase modulation. In this case, one of the real part and the imaginary part can be treated as a real number waveform and handled in the same way as before, but there is a problem in picking up the other part that has valid information and leaving it behind. Therefore, in such a case, another timing deviation detection method that effectively utilizes both the real part and the imaginary part is required.

The first sampler 1, second sampler 2, discriminator 3, and differentiator 4 in FIG. 3 are assumed to be 1', 2', 3', and 4' as the same components that input and output complex numbers, respectively.
The input terminal 100 and the output terminals 102 and 103 are also two sets of terminals 1000 and 100 corresponding to complex numbers, respectively.
FIG. 5 shows a reconfiguration of 100', 102', and 103' having numbers 1, 1020, 2021, 1030, and 1031 to accommodate complex number input. Components not particularly described here are the same as those in FIG. 3. However, the multiplier of 5 is not shown here. 200 is a reference number throughout FIG.

FIG. 6 shows a block diagram of one embodiment of the present invention. Block 200 is the same as in FIG. Block 5' is a product-sum circuit, with multipliers 50, 5
1 and an adder 51, input terminals 102',
103', complex numbers (a+jb) from (c+jb) and (ac+db) are output. As a result, the output terminal 101' obtains information that is the sum of timing deviation information obtained from the real part and timing deviation information obtained from the imaginary part of the input signal.

Note that when the input signal is a real number, the fifth and sixth
All the elements for the imaginary part in the figure are no longer needed, and the product-sum circuit 5' only needs the multiplier 50.
It will be the same as the block diagram shown in the figure. Therefore, it can be seen that FIG. 3 is also another embodiment of the present invention in which the input signal is a real number.

Although the above explanation has been based on the assumption that carrier phase synchronization of demodulated signals of four-phase phase modulation has been established, the clock phase control circuit of the present invention can also be used in situations where carrier synchronization has not been established at all. I would like to add that it operates without any deterioration.
As described above, according to the present invention, a clock phase control circuit suitable for digital processing can be provided.

[Brief explanation of drawings]

FIGS. 1 and 2 are diagrams for explaining the relationship between digital transmission waveforms and sample timing. Third
The figure shows a block diagram of an embodiment of the present invention. In the figure, 1 is a first sampler, 2 is a second sampler, 3 is a discriminator, 4 is a differentiator, and 5 is a multiplier. FIG. 4 is a diagram showing the relationship between the timing deviation Te and the timing deviation detection output. Fifth
FIG. 6 is a partial block diagram and an overall diagram of another embodiment of the present invention. In the figure, 1' is a first sampler, 2' is a second sampler, 3' is a discriminator, 4' is a differentiator, and 5' is a product-sum circuit.

Claims (1)

[Claims] 1 a first sampler that samples a complex input signal at zero phase of the clock signal; a second sampler that samples the complex input signal at the π phase of the clock signal; identifying the complex sign of the output of the first sampler; a discriminator; a differentiator that detects a difference between a value of the discriminator output one cycle before and a current value; a real part of each of the differentiator output and the second sampler output;
and a product-sum circuit that obtains the sum of products of imaginary parts, and changes the phase of the clock signal according to the output of the product-sum circuit, so that the complex input is sampled by a first sampler at an optimal sampling phase. 1. A clock phase control circuit characterized by a clock phase control circuit.