JPH0152924B2 - - Google Patents

Info

Publication number
JPH0152924B2
JPH0152924B2 JP59051446A JP5144684A JPH0152924B2 JP H0152924 B2 JPH0152924 B2 JP H0152924B2 JP 59051446 A JP59051446 A JP 59051446A JP 5144684 A JP5144684 A JP 5144684A JP H0152924 B2 JPH0152924 B2 JP H0152924B2
Authority
JP
Japan
Prior art keywords
transistors
common
resistor
base
emitters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP59051446A
Other languages
Japanese (ja)
Other versions
JPS60194810A (en
Inventor
Akira Usui
Kazuhiko Kubo
Hiroyuki Nagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59051446A priority Critical patent/JPS60194810A/en
Publication of JPS60194810A publication Critical patent/JPS60194810A/en
Publication of JPH0152924B2 publication Critical patent/JPH0152924B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/1433Balanced arrangements with transistors using bipolar transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/1458Double balanced arrangements, i.e. where both input signals are differential
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041Functional aspects of demodulators
    • H03D2200/0084Lowering the supply voltage and saving power
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041Functional aspects of demodulators
    • H03D2200/0088Reduction of intermodulation, nonlinearities, adjacent channel interference; intercept points of harmonics or intermodulation products

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Superheterodyne Receivers (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、テレビジヨンチユーナー回路や
CATVコンバーター、衛星放送受信機等に用い
ることのできる、高周波領域における集積回路を
用いた周波数混合回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to television tuner circuits and
This invention relates to a frequency mixing circuit using an integrated circuit in the high frequency range, which can be used in CATV converters, satellite broadcast receivers, etc.

従来例の構成とその問題点 従来の周波数混合回路の一例を第1図に示す。Conventional configuration and its problems An example of a conventional frequency mixing circuit is shown in FIG.

図の端子Aは局部発振器信号、端子Bは高周波
信号のおのおの入力端子、端子Cは中間周波数信
号の出力端子である。端子Bより与えられた高周
波信号には基準電位V1を与えておき、これをト
ランジスタ1のベースに供給し、さらに抵抗2を
通してトランジスタ3のベースにも加える。トラ
ンジスタ3のベースは、4によつて高周波成分が
軽減され直流電位が加えられることになる。トラ
ンジスタ1,3のエミツタは抵抗5,6を介し
て、互いに結合し、その結合点から定電流源7が
接続されている。高周波信号はそれぞれトランジ
スタ1,3にて増幅される。トランジスタ1,3
のコレクタは、それぞれトランジスタ8,9の共
通エミツタとトランジスタ10,11の共通エミ
ツタに接続される。トランジスタ8,9,10,
11は、トランジスタ8,11のベース間、トラ
ンジスタ9,10のベース間がそれぞれ接続され
ている。
Terminal A in the figure is a local oscillator signal, terminal B is an input terminal for high frequency signals, and terminal C is an output terminal for intermediate frequency signals. A reference potential V 1 is applied to the high-frequency signal applied from terminal B, and this is supplied to the base of transistor 1 and further applied to the base of transistor 3 through resistor 2 . The base of the transistor 3 has its high frequency component reduced by the transistor 4 and is applied with a DC potential. The emitters of transistors 1 and 3 are coupled to each other via resistors 5 and 6, and a constant current source 7 is connected to the coupling point. The high frequency signals are amplified by transistors 1 and 3, respectively. Transistor 1, 3
The collectors of are connected to the common emitters of transistors 8 and 9 and to the common emitters of transistors 10 and 11, respectively. Transistors 8, 9, 10,
Reference numeral 11 is connected between the bases of transistors 8 and 11 and between the bases of transistors 9 and 10, respectively.

トランジスタ8,11の共通ベースには、容量
12を介して端子Aより局部発振信号が加えられ
るとともに、抵抗13を通して基準電位源14の
基準電位V2が与えれる。またトランジスタ9,
10の共通ベースは抵抗15を介して基準電位源
14に接続されるとともに、容量16を介して接
地されている。トランジスタ8,10の共通コレ
クタは電源端子に接続される。またトランジスタ
9,11の共通コレクタは抵抗17を介して電源
端子に接続されている。
A local oscillation signal is applied from a terminal A via a capacitor 12 to the common base of the transistors 8 and 11, and a reference potential V 2 from a reference potential source 14 is applied via a resistor 13. Also, the transistor 9,
The common base of 10 is connected to a reference potential source 14 via a resistor 15 and grounded via a capacitor 16. The common collectors of transistors 8 and 10 are connected to a power supply terminal. Further, common collectors of the transistors 9 and 11 are connected to a power supply terminal via a resistor 17.

このようにしてダブルバランス型の周波数混合
回路を構成し、トランジスタ11と9の共通コレ
クタより周波数混合信号を出力端子Cに供給して
いるものである。
In this way, a double-balanced frequency mixing circuit is constructed, and a frequency mixing signal is supplied to the output terminal C from the common collector of the transistors 11 and 9.

ところで第1図の構成でトランジスタ8,11
の共通ベースの電位をVD,VE、トランジスタ9,
10の共通ベースの電位をVF、トランジスタ1
のベース電位VG、トランジスタ3のベース電位
をVHとして各点の直流電位を考えてみると抵抗
2による電位降下でVG>VHであり、局部発振器
信号が加わるためVD,VE>VFとなる。これは、
容量16が集積回路内の容量として、せいぜい数
pFしか構成できないために高周波成分の減衰が
十分確保できないために生ずる現象である。VG
>VH、VD,VE>VFのような電位差を生じた場合
には、トランジスタ8,10の共通コレクタに流
れ込む電流は、トランジスタ9,11の共通コレ
クタに流れる電流より大きくなり、いまたとえ
ば、抵抗13,15として3.3KΩ、抵抗5,6と
して100Ω、抵抗2に6.6KΩのものを用い、電源
電圧Vcc=12Vのときに定電流源7にI=3mA流
したときには、トランジスタ8,10の共通コレ
クタには1.7mA、トランジスタ9,11の共通コ
レクタには1.3mAという値がおのおの得られた。
By the way, in the configuration shown in Fig. 1, transistors 8 and 11
The potential of the common base of V D , V E , transistors 9,
10 common base potential V F , transistor 1
Considering the DC potential at each point, assuming that the base potential of V G is V G and the base potential of transistor 3 is V H, V G > V H due to the potential drop due to resistor 2, and since the local oscillator signal is added, V D , V E >V F. this is,
If the capacitance 16 is the capacitance in the integrated circuit, at most
This phenomenon occurs because sufficient attenuation of high frequency components cannot be ensured because only pF can be configured. V G
> V H , V D , V E > V F , the current flowing into the common collectors of transistors 8 and 10 becomes larger than the current flowing into the common collectors of transistors 9 and 11, and now For example, if resistors 13 and 15 are 3.3KΩ, resistors 5 and 6 are 100Ω, and resistor 2 is 6.6KΩ, and when power supply voltage Vcc = 12V and constant current source 7 is supplied with I = 3mA, transistor 8, A value of 1.7 mA was obtained for the common collector of transistors 9 and 11, and a value of 1.3 mA was obtained for the common collector of transistors 9 and 11, respectively.

このため、出力端子Cには負荷抵抗17と
1.3mAで得られる変換利得、3次歪しか確保でき
ず、回路が完全にバランスして1.5mA流したとき
に比べて、変換利得で3dB、3次歪(インターセ
プトポイント)でも3dB劣化するという欠点があ
つた。
Therefore, the load resistor 17 is connected to the output terminal C.
The disadvantage is that the conversion gain obtained at 1.3 mA and only third-order distortion can be secured, and compared to when the circuit is perfectly balanced and flows 1.5 mA, the conversion gain is 3 dB and the third-order distortion (intercept point) is degraded by 3 dB. It was hot.

発明の目的 本発明は定電源源の値を同一にした場合に、変
換利得、3次歪を改善する手段を提供することを
目的とする。
OBJECTS OF THE INVENTION It is an object of the present invention to provide means for improving conversion gain and third-order distortion when constant power sources have the same value.

発明の構成 本発明による周波数混合回路は、高周波入力信
号を2つに分け、そのうちの一方をダブルバラン
ス型回路を構成する2つの高周波増幅トランジス
タの一方のベースに供給し、他方を第1の抵抗を
介して他方の高周波増幅トランジスタのベースに
供給し、この他方高周波増幅トランジスタのベー
スを第1の容量を介して接地するとともに、上記
ダブルバランス型回路を構成する第1〜第4のト
ランジスタのうち第1、第2のトランジスタのエ
ミツタを共通に接続し、第3、第4のトランジス
タのエミツタも共通に接続し、第1、第2のトラ
ンジスタの共通エミツタを上記一方の高周波増幅
トランジスタのコレクタに、第3、第4のトラン
ジスタの共通エミツタを上記他方の高周波増幅ト
ランジスタのコレクタにおのおの接続し、局部発
振器信号を第1、第4のトランジスタの共通ベー
スに供給し、この共通ベースを第2の抵抗を介し
て基準電位源に接続し、第2、第3のトランジス
タの共通ベースを第2の容量を介して接地すると
ともに第3の抵抗を介して上記基準電位源に接続
し、かつ第2、第4のトランジスタのコレクタを
共通に接続して電源端子に接続し、第1、第3の
トランジスタのコレクタを共通に接続して負荷抵
抗を介して上記電源端子に接続し、この負荷抵抗
と共通コレクタの接続点より中間周波出力信号を
得るようにしたものであり、より大きいパワーの
中間周波出力信号を得ることができ、変換利当、
3次歪ともに大幅な改善がはかれるものである。
Structure of the Invention The frequency mixing circuit according to the present invention divides a high frequency input signal into two, supplies one of them to one base of two high frequency amplification transistors forming a double-balanced circuit, and supplies the other to a first resistor. of the first to fourth transistors constituting the double-balanced circuit. The emitters of the first and second transistors are connected in common, the emitters of the third and fourth transistors are also connected in common, and the common emitter of the first and second transistors is connected to the collector of one of the high frequency amplification transistors. , the common emitters of the third and fourth transistors are respectively connected to the collectors of the other high frequency amplification transistor, a local oscillator signal is supplied to the common base of the first and fourth transistors, and this common base is connected to the common base of the second transistor. connected to a reference potential source via a resistor, a common base of the second and third transistors being grounded via a second capacitor, and connected to the reference potential source via a third resistor; , the collectors of the fourth transistor are commonly connected and connected to the power supply terminal, the collectors of the first and third transistors are commonly connected and connected to the power supply terminal via a load resistor, and this load resistor and The intermediate frequency output signal is obtained from the connection point of the common collector, and it is possible to obtain an intermediate frequency output signal with higher power, and the conversion gain,
Both third-order distortion can be significantly improved.

実施例の説明 本発明の一実施例の構成を第2図に示す。Description of examples FIG. 2 shows the configuration of an embodiment of the present invention.

図において17の抵抗を挿入した位置以外は第
1図と同等構成になつているので、重複する説明
の部分は省略する。上記抵抗17はトランジスタ
8,10の共通コレクタと電源端子の間に接続さ
れており、中間周波数出力はトランジスタ8,1
0の共通コレクタより出力端子Cに供給されるも
のである。トランジスタ8,10の共通コレクタ
には第1図にて説明したように、定電流源7の電
流値Iとして3mAのとき、1.7mAが得られ、第
1図の例に比て変換利得で6dB、3次歪(インタ
ーセプトポイント)でも6dBの改善が得られた。
これは、回路を完全にバランスさせたとき
(1.5mA流したとき)に比べても3dBの改善が得
られるもので、集積回路等で、電流をできるだけ
制限する必要のあるときには特に有効な手段であ
るといえる。
In the figure, the structure is the same as that in FIG. 1 except for the position where the resistor 17 is inserted, so redundant explanations will be omitted. The resistor 17 is connected between the common collector of the transistors 8 and 10 and the power supply terminal, and the intermediate frequency output is connected between the common collector of the transistors 8 and 10 and the power supply terminal.
0 is supplied to the output terminal C from the common collector. As explained in Fig. 1, when the current value I of the constant current source 7 is 3 mA, 1.7 mA is obtained at the common collector of the transistors 8 and 10, and the conversion gain is 6 dB compared to the example shown in Fig. 1. , a 6dB improvement was also obtained in third-order distortion (intercept point).
This provides an improvement of 3 dB compared to when the circuit is perfectly balanced (when 1.5 mA flows), and is an especially effective method when it is necessary to limit the current as much as possible, such as in integrated circuits. It can be said that there is.

発明の効果 このように、本発明によれば、ダブルバランス
型の電流バランスをアンバランスにして出力端子
に多くのパワーを供給できる構成にすることによ
り、定電流値において変換利得、3次歪に対して
有利な条件を確保できるものである。
Effects of the Invention As described above, according to the present invention, by making the current balance of the double-balanced type unbalanced and configuring it to be able to supply more power to the output terminal, the conversion gain and third-order distortion can be reduced at a constant current value. This means that favorable conditions can be secured.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例における周波数混合回路の回路
図、第2図は本発明の一実施例における周波数混
合回路の回路図である。 A……局部発振信号入力端子、B……高周波信
号入力端子、C……周波数混合出力端子、1,
3,8,9,10,11……ダブルバランス型混
合回路を構成するトランジスタ、2,5,6,1
3,15,17……ダブルバランス型混合回路を
構成する抵抗、4,16………接地容量、7……
定電流源、14……基準電位源。
FIG. 1 is a circuit diagram of a frequency mixing circuit in a conventional example, and FIG. 2 is a circuit diagram of a frequency mixing circuit in an embodiment of the present invention. A...Local oscillation signal input terminal, B...High frequency signal input terminal, C...Frequency mixing output terminal, 1,
3, 8, 9, 10, 11...Transistors forming a double-balanced mixed circuit, 2, 5, 6, 1
3, 15, 17...Resistance constituting the double-balanced mixed circuit, 4, 16...Grounding capacitance, 7...
Constant current source, 14...Reference potential source.

Claims (1)

【特許請求の範囲】[Claims] 1 高周波入力信号を2つに分け、そのうちの一
方をダブルバランス型回路を構成する2つの高周
波増幅トランジスタの一方のベースに供給し、他
方を第1の抵抗を介して他方の高周波増幅トラン
ジスタのベースに供給し、この他方の高周波増幅
トランジスタのベースを第1の容量を介して接地
し、上記ダブルバランス型回路を構成する第1〜
第4のトランジスタのうち第1、第2のトランジ
スタのエミツタ、第3、第4のトランジスタのエ
ミツタをそれぞれ共通に接続し、第1、第2のト
ランジスタの共通エミツタを上記一方の高周波増
幅トランジスタのコレクタに、第3、第4のトラ
ンジスタの共通エミツタを上記他方の高周波増幅
トランジスタのコレクタにおのおの接続し、局部
発振信号を上記第1、第4のトランジスタの共通
ベースに供給し、この共通ベースを第2の抵抗を
介して基準電位源に接続し、第2、第3のトラン
ジスタの共通ベースを第2の容量を介して接地す
るとともに第3の抵抗を介して上記基準電位源に
接続し、上記第2、第4のトランジスタのコレク
タを共通に接続して電源端子に、第1、第3のト
ランジスタのコレクタを共通に接続して負荷抵抗
を介して上記電源端子におのおの接続し、この負
荷抵抗と共通コレクタの接続点より中間周波出力
信号を得るようにしたことを特徴とする周波数混
合回路。
1. Divide the high-frequency input signal into two, supply one of them to the base of two high-frequency amplification transistors forming a double-balanced circuit, and supply the other to the base of the other high-frequency amplification transistor through the first resistor. and the base of the other high frequency amplification transistor is grounded via the first capacitor, and the first to
Among the fourth transistors, the emitters of the first and second transistors and the emitters of the third and fourth transistors are connected in common, respectively, and the common emitter of the first and second transistors is connected to the emitters of the first and second transistors. The common emitters of the third and fourth transistors are connected to the collectors of the other high-frequency amplification transistor, and a local oscillation signal is supplied to the common base of the first and fourth transistors, and the common base is connected to the collector of the third and fourth transistors. connected to a reference potential source via a second resistor, grounding the common base of the second and third transistors via a second capacitor, and connecting to the reference potential source via a third resistor; The collectors of the second and fourth transistors are commonly connected to the power supply terminal, the collectors of the first and third transistors are commonly connected and each connected to the power supply terminal via a load resistor, and the load A frequency mixing circuit characterized in that an intermediate frequency output signal is obtained from a connection point between a resistor and a common collector.
JP59051446A 1984-03-16 1984-03-16 frequency mixing circuit Granted JPS60194810A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59051446A JPS60194810A (en) 1984-03-16 1984-03-16 frequency mixing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59051446A JPS60194810A (en) 1984-03-16 1984-03-16 frequency mixing circuit

Publications (2)

Publication Number Publication Date
JPS60194810A JPS60194810A (en) 1985-10-03
JPH0152924B2 true JPH0152924B2 (en) 1989-11-10

Family

ID=12887155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59051446A Granted JPS60194810A (en) 1984-03-16 1984-03-16 frequency mixing circuit

Country Status (1)

Country Link
JP (1) JPS60194810A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0391305A (en) * 1989-09-04 1991-04-16 Hitachi Ltd Frequency converter and tuner circuit using the same
FR2695272B1 (en) * 1992-08-26 1994-12-09 Philips Composants Mixer circuit for radio or television signals.

Also Published As

Publication number Publication date
JPS60194810A (en) 1985-10-03

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