JPH0152934B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to scanning pulse generation circuits, for example, optical character reading devices, photodetector arrays such as facsimiles, solid-state imaging devices, etc. A generation circuit that generates pulses for selective scanning selectively and digitally, and is particularly related to circuits constructed from integrated circuits (ICs, LSIs) using MOS transistors, etc.

[Prior art]

Conventionally, in the above-mentioned scanning pulse generation circuit, in order to sequentially select a large number of photoelectric conversion elements arranged one-dimensionally or two-dimensionally, input pulses are generated using clock pulses of two or more phases as shown in FIG. Shift register type scanning circuits that sequentially output signals after delaying them by a certain period of time are widely used. This scanning circuit is a circuit diagram showing the first three stages of a shift register type scanning circuit using MOS field effect transistors (hereinafter abbreviated as MOST).

Blocks G ₁ and G ₂ have clock pulses φ 1 and φ ₁ , respectively.
φ ₂ generator, G ₃ is the input pulse V _1N generator, and
V _D is a power supply voltage for driving, and V _S is a reference voltage application terminal that generally provides a ground voltage. transistor
G ₁ and G ₂ are saturation type load MOS formed by shorting the gate and drain, and the transistors G ₃ and
G ₄ is the driving MOST. A circuit in which the source of G ₁ and the drain of Q ₃ or the source of G ₂ and the drain of Q ₄ are combined in series operates as a polarity inversion circuit. Moreover, Q ₅ and Q ₆ are transmission MOST.

The following explanation will take the N channel MOST as an example and use positive logic (expressing a positive high voltage as "1" and the ground voltage as "0"), but for the P channel as well, if the sign of the voltage is reversed, It can be explained in exactly the same way. The input pulse generator G ₃ allows the first
Input pulse V _1N applied to the polarity inversion circuit of the first stage
is delayed by a fixed time determined by the clock pulse each time it passes through each stage due to the transmission MOST which is alternately opened and closed by the clock pulses φ ₁ and φ ₂ . appears at the output terminals V ₀₁ , V ₀₂ , and V ₀₃ .

The above-mentioned shift register type scanning circuit using MOST is suitable for semiconductor integrated circuits because all circuit elements can be manufactured from MOST and the manufacturing process is relatively simple. It's easy. Further, since the operating margin is high and the variation in characteristics of each stage is small, it is extremely excellent as a scanning circuit that requires multi-stage output.

[Problem that the invention seeks to solve]

However, the above scanning circuit has the following drawbacks.

Since current always flows through one of the two-stage inverters, power consumption is large.

Although the load driving ability is determined by MOST Q ₂ (or Q ₁ ), the driver transistor
The channel width (ie, transistor size) of MOST Q ₄ (or Q ₃ ) must be increased, which increases the integration area. _{In other words , the} output _offset voltage is _{V = V 4} ) : Conductance of MOST Q ₄ L ₂ : Channel width of MOST Q ₂ L ₄ : Channel width of MOST Q ₄ In order to reduce the offset,
L ₄ of MOST Q ₄ must be increased,
The area of MOST Q ₄ increases.

The output amplitude is small compared to the power supply voltage. That is, the "0" level of the output does not become the ground potential (approximately V _D ·gm (Q ₂ )/gm (Q ₄ )), and the "1" level of the output does not become the power supply potential.

The influence of variations in the threshold voltage of MOST Q ₄ is large.

In addition to the scanning circuit shown in FIG.
Shift registers based on MOST (CMOS) are also being considered. CMOS circuits offer high speed, low power consumption, and fewer components per stage, but N-channel MOST and P-channel MOST
It is desirable to configure the scanning circuit with the MOST of one of the channels, since it requires an integrated circuit and the manufacturing process becomes complicated.

An object of the present invention is to improve the drawbacks of the semiconductor device constituting the conventional scanning pulse generation circuit described above.

[Means for solving problems]

The present invention is a semiconductor device in which a dynamic scanning circuit (shift register) is constructed by a MOST bootstrap circuit and a reset circuit using feedback.

[Effect]

Below, N channel with electrons as signal charge
This will be explained using a MOS transistor (hereinafter referred to as MOST).
In Fig. 2A and Fig. 3A, 1 is a P-type Si substrate;
2 and 3 are N-type diffusion layers that become drain and source, 4 is a gate electrode, 5 is a gate insulating film (SiO ₂ ), 6 is a field insulating film (SiO ₂ etc.), 7 and 8 are drains,
The source electrode, 9, is an N-type inversion layer. When the gate electrode 4 is OV in FIG. 2A, no inversion layer is formed on the surface of the P-type Si substrate 1 under the gate oxide film 5. When a positive voltage (more than the MOST threshold voltage V _Th ) is applied to the gate electrode 4, an N-type inversion layer 9 is formed as shown in FIG. 3A, and the N-type diffusion layers 2 and 3 are are electrically connected. For example, N type diffusion layer 2
Figure 2B shows the capacitive coupling relationship between
and shown in FIG. 3B.

When the gate electrode 4 is OV, a terminal 12 corresponding to the N-type diffusion layer 2 and a terminal 14 corresponding to the gate electrode 4
The only coupling capacitance between them is the capacitance 22 due to their structural overlap, and the gate electrode 4 (terminal 14) has a parasitic capacitance that suppresses the effect of this capacitive coupling and is substantially connected to the ground 20. Overlap capacitance 2 between gate electrode 4 and P-type Si substrate 1
1. There is an overlap capacitance 23 with the N-type diffusion layer 3 indicated by the terminal 13, and a parasitic capacitance 24 in other parts connected to the gate electrode (FIG. 2B).

On the other hand, a positive voltage (>V _th ) is applied to the gate electrode (terminal 14).
is applied, the gate electrode 4 (terminal 1
4) and the N-type diffusion layer 2 (terminal 12), in addition to the capacitance 22, the capacitance 25 between the inversion layer 9 instead of the capacitance 21 and the N-type diffusion layer 3 (terminal 1
3), and only the parasitic capacitance 24 is connected to the ground 20. Capacities 22 and 23 are normally equivalent, capacitances 21 and 25 are also substantially equal, and normal capacity 2
This value is nearly an order of magnitude larger than that of 2.

Therefore, the coupling capacitance between the N-type diffusion layer 2 and the gate electrode 4 has the property of a varactor capacitance that changes greatly depending on the voltage applied to the gate electrode 4, and a positive voltage is applied to the gate electrode 4 in advance. Sometimes, when a positive pulse is applied to the N-type diffusion layer 2, the voltage of the gate electrode 4 is further increased, producing a bootstrap-like effect.

The present invention is a scanning circuit that utilizes the properties of this varactor capacitance, the principle of which is shown in FIG. Figure 4A
indicates 2 bits corresponding to the basic circuit,
The timing chart for each main point A to E is shown in Figure 4B.
Shown below. The loads 45 and 46 may be resistors, capacitors, or a combination thereof.
When the voltage at point C is already positive, φ ₂
When becomes positive, the voltage at point C is greatly increased,
The MOST 43 applies φ ₂ to the load 46 under non-saturated conditions.

The design requirement is, for example, when point B becomes positive, C
The voltage drop at the point is ΔV (=V _th + K√V _D −V _th ; V _D :
V _D : amplitude of φ ₁ , φ ₂ , K: substrate effect constant), (C ₁ + C ₂ ) V _D /C ₁ + C ₂ + C ₃ + C ₄ ΔV ... (1) C ₂ V _D /C ₁ +C ₂ +C ₃ +C ₄ V _th ... (2) It is sufficient.

When the loads 45 and 46 are small, a capacitance, high resistance (approximately 10 ⁵ to 10 ⁷ Ω for normal integrated circuit device dimensions and applications), or DC voltage is applied to the gate electrode in parallel, and the load is constantly maintained. Just set up a MOST that can flow a small amount of current and treat it as a load.

The scanning pulse generation circuit of the present invention has a significantly simple configuration, does not require a driver MOST that is disproportionately large compared to the load like a normal polarity inversion circuit, is suitable for integration, and has low power consumption. Since the applied pulses φ ₁ and φ ₂ are applied to the load as they are, there is no fluctuation in the pulses applied to the load due to variations in the characteristics of each MOST that makes up the MOST, such as variations in V _th , and there is no vibration. There is no decrease in width. Particularly when applied to an analog device, for example, an image device such as a solid-state image sensor or a frame memory, it is possible to significantly reduce noise.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

The circuit shown in FIG. 1 is one embodiment of the present invention. In Figure 1, H ₁ and H ₂ are synchronization (clock) pulses, Hin is an input pulse, V _S is ground, and O ₁ , O ₂ ,
_O3 is an output pulse, which is used to open and close, for example, a horizontal switch MOS transistor of a solid-state imaging device.

It is now assumed that point A is at a high level (hereinafter abbreviated as "H"). Next, when the synchronizing pulse _H2 is input (becomes "H"), the potential at point B increases through the transistor _T1 . Bootstrap capacitance of points A and B 51
(The parasitic capacitance of MOST mentioned earlier is fine, but
A capacitor may be added externally, and various embodiments of the present invention will be described below, but the same applies to other examples. ), the potential at point A becomes equal to the pulse amplitude
V _D and the transistor T ₁ begins to operate in the non-saturation region. Therefore, at point B, a pulse _O1 having exactly the same waveform as the synchronizing pulse _H2 is output.
Also, at this time, since the transistor _T2 is on at the same time, "H" is written to point C. This potential is approximately V _D minus the threshold voltage of T ₂ .

Next, when _H1 becomes “H”, transistor _T3 and
_T4 turns on, and "H" is written to point E for the same reason as described above.

Furthermore, when H ₂ becomes "H" next time, pulse O ₂ is output to point F in the same way. Now, at this time, transistor _T2 is also turned on. Since "H" is written in point C, the charge accumulated there flows back to point B, and points B and C tend to have the same potential, and the potential of point B changes from 0 to positive. Lift up to.

For example, in a solid-state image pickup device, as shown in FIG. 1B, a horizontal output pulse is generated only once, and if the potential is not zero thereafter, noise will increase. Transistor _T7 is a transistor for clearing the potentials at points B and C to zero. Since point F, which is at a high level, is connected to the gate, _T7 is turned on and points B and C remain fixed at zero potential.

In the circuit shown in FIG. 1, since no direct current flows, the power consumption is as low as that of CMOS, and all elements can be constructed using only N-channel MOSTs.

The circuit shown in Figure 6 has reset transistors 61 and 62 inserted in the output line, and the operating principle is exactly the same as the circuit shown in Figure 5, but the reset transistor makes the operation more reliable. Become. Inserting a reset transistor has no adverse effect on the pitch of the shift register.

FIG. 7 is a modification of the embodiment shown in FIG. 1, with only a slight difference in feedback. In other words, in FIG. 1, the potential at point F is fed back to point C, but in FIG. 7, it is fed back to point B in FIG.
MOST: _T8 , _T9 ).

Conversely, although point B is fed back from point F in FIG. 7, receiving feedback from point E as in another embodiment of the present invention shown in FIG. 8 does not interfere with the principle of the present invention. There isn't.

9 to 12 show other embodiments of the present invention. The embodiment of FIG. 9 differs from FIG. 1 in that the drain of the gate transistor T ₂ is connected to the power supply V _D line,
The output _O1 is applied to the gate of the transistor _T2 . In the embodiments shown in FIGS. 1, 6, 7, and 8, the synchronization pulses H ₁ and H ₂ are
Each time it turns on, transistors T ₂ and T ₄ turn on, and the charges at points B and C move below the gate each time. pulse
When H ₁ and H ₂ are turned off, part of the charge flows to the substrate, and the potential at point C may move slightly toward the positive side. The embodiments shown in FIGS. 9 to 12 avoid this problem. The operating principle is almost the same as in FIG.

Figure 10 shows the bootstrap capacity 51 in Figure 9.
In this case, the gate capacitance of the MOST transistor 101 is used.

FIG. 11 shows an example in which a capacitor 111 is provided externally as a bootstrap capacitor, although the transistors T ₁ and T ₂ already have varactor capacitors.

While the gate of the feedback transistor _T0 in FIG. 9 is connected to point E, FIG. 12 shows an example in which feedback is provided from point D.

FIG. 13 shows another embodiment of the invention. 13th
The figure shows the same as in FIG. 6, but the feedback transistor _T7 is fed back to point B instead of point C.

FIG. 14 shows another embodiment. In this embodiment, reset transistors 141 _and 142 are provided on the output lines O ₁ , _{O 2} , O ₃ .

Furthermore, in the above embodiment, the outputs O ₁ , O ₂ , O ₃ are as follows:
Although the pulse was synchronized with only one of the synchronization pulses _H1 or _H2 , the use as a normal scanning circuit is not limited to this.
For example, in FIG. 1, if H ₁ and H ₂ are similar pulses, output pulses can be obtained from points B, D, and F. It goes without saying that this method of use is applicable to all embodiments of the present invention.

Other types of embodiments of the invention are described below.

FIG. 15 shows an embodiment of the scanning circuit of the present invention. A unit circuit (bit) is composed of four MOSTs, for example, T ₁₁ , T ₁₂ , and T ₁₄ . FIG. 15B shows input pulse φ _io , drive pulses φ ₁ , φ ₂ , and FIG. 15A
Points 15A and 15B are representative of the main points in
and points 15C, 15F, 15 where scanning pulses are obtained.
A time chart of the potential of I is shown in FIG. 15B.
The potentials at points 15D and 15E, 15G and 15H are similar to those at points 15A and 15B, respectively.
It appears as a phase delay of 360° and 720°. Although the terminal V _S is grounded, the same effect can be obtained even if it is coupled to φ ₁ (although the potential waveform at point 15A changes slightly).

The highest potential obtained at point 15A is reduced by ΔV ₁ due to the threshold voltage V _th of T ₁₁ and the substrate effect, and further reduced by ΔV ₂ due to charging of the gate capacitance of T ₁₃ , which is transmitted to point 15B, making T ₁₃ conductive. . Due to φ ₁ , the potential at point 15B is due to the varactor capacitance effect (represented by capacitance 151).
It is pushed up by ΔV and increases by ₃ . ΔV ₃ V _th +
If ΔV ₁ + ΔV ₂ , φ ₁ passes through T ₁₃ (under the condition that T ₁₃ is not saturated) and reaches the output end, for example, point 1.
This will be communicated to 5C.

Also, due to the gate electrode capacitance effect of T ₁₂ , the 15th
As shown in FIG. B, each time the pulse of φ ₂ becomes positive, a potential ΔV ₄ appears at points 15A and 15B, making T ₁₅ periodically conductive. At this time, _φ1 is at ground level, and a reset operation is performed to always stabilize the output terminal at ground potential. T ₁₄ threshold voltage only other
This effect is best exhibited if the value is set higher than MOST.

The scanning circuit of the present invention can obtain output pulses only from φ ₁ , is not affected by variations in characteristics of each MOST, especially T ₁₃ threshold voltage, has no attenuation, and has significantly improved uniformity. Ru. In addition, the power required is extremely low, and there is no need for a driver MOST that is disproportionately large to the load, which is required for inverter circuits, making it particularly suitable for high integration.

In FIG. 16, in order to increase the reset operation in the previous example, a MOST, _T15, is provided, which connects _φ1 and the output terminal through _φ2 . The same effect can be obtained by connecting the drain of _T15 to the grounding terminal V _S instead of _φ1 .

Figure 17 shows the example in Figure 15 with the addition of a MOST, T ₁₆ , _whose source and drain are connected to _φ2 .
exhibits a varactor capacitance effect similar to T ₁₃ , and the
Eliminates the ΔV ₂ drop caused by T ₁₃ gate capacitance charging and simplifies design requirements.

Needless to say, FIG. 16 is combined with the embodiment of FIG. 17, that is, by providing T ₁₅ and T ₁₆ , both effects can be obtained at the same time. Further, by providing a capacitor in parallel in addition to the varactor-like capacitance 151 of T ₁₃ shown in FIG. 15, ΔV ₃ can be made larger. This is equivalent to increasing the capacitance 23 in FIGS. 2B and 3B.

Needless to say, similar effects can be obtained in either example.

FIG. 18 shows an embodiment of an exemplary type of scanning circuit of the present invention. 4 MOSTs, e.g. T ₂₁ , T ₂₂ ,
T ₂₃ and T ₂₄ constitute a unit circuit (bit). In FIG. 18B, input pulse φ _io , drive pulse φ ₁ , φ ₂ ,
And as a representative of the main points in FIG. 18A, the time chart of the potential at points 18A to 18H is
Shown in Figure B.

For example, the highest potential obtained at point 18C is reduced by ΔV ₁ due to the threshold voltage V _th of T ₂₁ and the substrate effect, and further
Due to the charging of the gate capacitance of T ₂₃ , ΔV ₂ drops and is transmitted to point 18D, causing T ₂₃ to conduct. Due to φ ₁ , the potential at point 18D is raised by the varactor capacitance effect, and increases by ΔV ₃ . ΔV ₃ V _th + ΔV ₁ +
If ΔV ₂ , φ ₁ passes through T ₂₃ (under the condition that T ₂₃ is not saturated) and is transmitted to the output terminal, point 18E.

In addition, due to the gate electrode capacitance effect of T ₂ , the 18th
As shown in FIG. B, each time the pulse of φ ₂ becomes positive, a potential ΔV ₄ appears at points 18C and 18D, making T ₂₃ periodically conductive. At this time, _φ1 is at ground level, and a reset operation is performed to always stabilize the output terminal at ground potential. T ₂₄ threshold voltage only other
This effect will be even better if it is set higher than MOST.

In FIG. 19, in order to increase the reset operation in the previous example, a MOST, _T25 , is provided to connect _φ1 and the output terminal through _φ2 . The same effect can be obtained by connecting the drain of _T25 to ground instead of _φ1 .

Figure 20 shows the example in Figure 18 with the addition of a MOST, T ₂₀ , with the source and drain connected to φ _{2 .}
exhibits a varactor capacitance effect similar to T ₂₃ , and the
Eliminates the ΔV ₂ drop caused by T ₂₃ gate capacitance charging and simplifies design requirements.

Needless to say, by combining the examples shown in FIGS. 19 and 20, that is, by providing T ₂₅ and T ₂₆ , both effects can be obtained at the same time. Also, as shown in Figure 18
By providing a parallel capacitance in addition to the varactor-like capacitance of T ₂₃ , ΔV ₃ can be made larger. This is equivalent to increasing the capacitance 23 in FIGS. 2B and 3B. Needless to say, similar effects can be obtained in any of the embodiments.

FIG. 21 is yet another type of embodiment of a scanning circuit according to the present invention. Moreover, FIG. 21B shows the voltage waveform of each node in FIG. 21A. The operation of this scanning circuit will be briefly explained. 21st
In the figure, when input pulse φ _IN is applied, MOS transistor (hereinafter abbreviated as MOST) T ₃₁ is turned on by clock pulse φ ₂ and node 21Z
Charge accumulates at (MOST, gate of T ₃₂ ). next,
When clock pulse _φ1 becomes high level (“H”),
Node 21A becomes “H” and MOST and T ₃₃ also become
ON, the node 21B also becomes "H". When φ ₁ is at a low level (“H”), the potential of the node 21A becomes “L”, but the node 21B remains at “H” thanks to the diode characteristics of MOST and T ₃₃ . The potential of the node 21B is the same as that of the gate of the MOST and _T35 , and when φ ₂ becomes "H", the nodes 21C and 21D also become "H".
When φ ₂ becomes "L" again, the potential of the node 21C becomes "L", but the potential of the node 21D remains "H". Similarly, node 21E,2
The voltage is transmitted to 1F, 21G, and 21H, and when the potential of node 21F becomes “H”, MOST, T ₃₄
The gate of node 21B becomes "H" and turned on, and the potential of node 21B is reset to V _SS , that is, "L".

As can be seen from FIG. 21B, the outputs of the scanning circuit are 21A, 21C, 21E, 21
It is possible to obtain narrow panel rows (blank pulse trains) such as G, . . . and wide panel rows such as B, D, F, H, . Also 21A, 21C, 21E,
The pulse amplitude of 21G,... is MOST, T ₃₂ , T ₃₅ ,
Due to the boot strap effect due to the capacitance between the gate and channel of T _{38 .} . . , a pulse amplitude exactly the same as that of φ ₁ (or φ ₂ ) can be obtained.

The power consumption is only in the stage where the input pulse is being transmitted, and it is extremely small as it only requires charging the load.

Another example of the present invention is shown in FIG. This is MOST, T ₃₂ , T ₃₅ , T ₃₈ , T ₄₁ . . . in Fig. 21.
An external capacitor 221 is added between the gate and source to enhance the boot strap effect.

FIG. 23 shows another example, where nodes 21B, 21
This is the feedback from nodes 21E, 21G, . . . for resetting the potentials of D, .

FIG. 24 is another example, in which an external capacitor 241 is added to the example of FIG. 23 to enhance the boot strap effect.
is added.

FIG. 25 is another example. The sos of the reset transistor is connected to _φ1 and _φ2 .

Figure 26 is another example, in which the circuit configuration of Figure 25 has a capacitance of 2 to strengthen the boot strap effect.
61.

FIG. 27 shows another example. 271 in Figure 21
This includes a MOS varactor, and these have a property that their capacitance is large only when the gate is "H". For example, if the potential of node 21B is "H", the capacitance of 271 sufficiently brings the gate of MOST, _T35 to "H", and if it is "L", the capacitance of 271 is small and does not have any adverse effect. Furthermore, this MOS
Varactors can also be added to the examples of FIGS. 22-26.

FIG. 28 shows another example. In order to make the “H” potential of the nodes 21A, 21C, 21E, 21G, etc. of the circuit in FIG. 23 more complete, MOST, T ₅₁
~ _T54 plus. The MOST to complete this reset can also be added to FIGS. 21, 22, and 24-27.

Note that the timing chart for the circuits of FIGS. 22 to 27 is the same as that of FIG. 21B.

The features of this embodiment can be summarized as follows.

(i) 3MOST/stage is sufficient, improving the degree of integration.
(However, in the example shown in Figure 28, 4MOST/
(ii) When used as 6MOST/stage, output pulses synchronized only with φ ₁ (or φ ₂ ) can be obtained,
The non-uniformity of the output pulses is significantly reduced.

(iii) As output pulses, nodes 21A, 21C,
When using 21E, 21G, . . . , the output pulse amplification is exactly the same as φ ₁ (or φ ₂ ), and there is no V _TH drop due to MOST.

(iv) The output pulse width can be the same as the clock pulse width (narrow pulse width) and the clock pulse period (wide pulse width).

(v) Bad parasitic effects when integrated into ICs (chatge
pumping).

(vi) Extremely low power consumption.

(vii) In order to operate this scanning circuit, φ ₁ , φ ₂ ,
Only φ _IN and V _SS (GND) are required; V _DD is not necessary.

FIG. 29 shows the termination circuit of the above scanning circuit.

This figure shows T ₆₁ , T ₆₂ , T ₆₃ ,
This is the MOST of T ₆₄ and T ₆₅ connected.

The potential of the node 21F is reset by the pulse 21I synchronized with _φ1 by MOST, _T61 , as long as the potential of the node 21H is "H". Further, the potential of the pulse H is "L" when the potential of the node 21G is "L".
It is shown that it is reset by the pulse 21J synchronized with _φ2 by MOST and _T63 only when . In addition, the gm ratio of MOST, T ₆₃ and T ₆₄ is gm,
It should be 64/gm, about 638. Also,
MOST, T ₆₂ is included to ensure operation that is not required.

FIG. 30 illustrates another termination circuit. Assume that "H" is currently stored at point 30A of the shift register. Next, when φ ₁ becomes “H”, T ₇₁ is in the ON state, so the 30B point and 30C
The potential at the point becomes "H". When _φ1 becomes “L”,
The potential 30B becomes "L", but the potential 30C remains "H". Next, when φ ₂ becomes “H”, T ₇₃ becomes ON state, and the 30C potential is at the 30C point.
The capacity is divided into 30D points. (30C point capacity C _C ,
The capacitance C _D potential at the 30D point is C _C /C _C +C _D דH”. ) At this time, if the potential of 30D is made higher than the threshold voltage of _T75 , _T75 will be in the ON state, and the potential of 30A will be discharged and become "L". Next, when _φ1 becomes “H”, _T74 becomes ON state and the 30D potential becomes “L”
(The C potential remains C _C /C _C +C _D דH”). Next, when φ ₂ becomes “H”, the 30C potential changes again.
Divided into C _C C _D. After repeating the above steps to discharge the potential of 30A, the potential of 30C drops to "L".

The characteristics of this circuit are as follows: {C _C /C _C +C _D × “H” > (Threshold voltage of T ₇₄ )
(Threshold voltage of T ₇₄ )} C _C and C _D should be selected so that the relationship between C _C and C _D is not strict, and a rough ratio is sufficient.

Even if the potential of 30B and 30C tries to rise to "H" due to charge pumping, etc., by repeating the timing of dividing by φ ₂ and discharging at φ ₁ ,
It can be returned to “L”.

It can be terminated by simply adding two MOSTs.

〔Effect of the invention〕

According to the present invention, there is no period during which DC current flows as in a polarity inversion circuit, so it is suitable for low power consumption, high-speed scanning, and high integration, and has a uniform output waveform due to the efficient coupling capacitance of the bootstrap. This has the effect of providing good performance, less malfunction, and a large operating margin.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the scanning pulse generation circuit of the present invention, FIGS. 2 and 3 are diagrams explaining the parasitic capacitance of a MOST type transistor, and FIG. 4 is a diagram showing an embodiment of the scanning pulse generation circuit of the present invention. A diagram explaining the principle,
FIG. 5 is a diagram showing a conventional scanning pulse generation circuit, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG.
Figure 1, Figure 12, Figure 13, Figure 14, Figure 15
Figure 16, Figure 17, Figure 18, Figure 19,
Figure 20, Figure 21, Figure 22, Figure 23, Figure 2
Figure 4, Figure 25, Figure 26, Figure 27, Figure 28
29 and 30 are diagrams showing other embodiments of the scanning pulse generation circuit of the present invention. φ ₁ , φ ₂ ... Synchronous pulse (terminal), 41, 42, 4
3, 44...MOS type transistor, 45, 46...
Load, C ₁ , C ₂ , C ₃ , C ₄ ...parasitic capacitance.

Claims (1)

[Claims] 1. At least six electrodes each having first and second electrodes serving as a source or drain, and a gate electrode.
1st, 2nd, 3rd, 4th, 5th, 6th
The gate electrode of the first transistor is connected to the output terminal of the basic circuit in the previous stage, and the first electrode of the first transistor is connected to the second basic circuit. a first electrode of the transistor; a second electrode of the second transistor is connected to a gate electrode of the third transistor; a first electrode of the third transistor is connected to a first electrode of the fourth transistor; The second electrode of the fourth transistor is connected to the input terminal of the basic circuit at the subsequent stage, and the first terminals of the fifth and sixth transistors are connected to either the first or second electrode of the second and fourth transistors, respectively. connected to one of the fifth and sixth
The second electrodes of the transistors are each grounded, the gate electrodes of the fifth and sixth transistors are respectively connected to the first electrode or the gate electrode of the first and third transistors in the subsequent stage, and the gates of the first and third transistors A capacitive element is provided between the electrode and the first electrode, and a capacitive element is provided between the second electrode and the first electrode.
A first synchronization pulse is applied to the electrode and the gate electrode of the second transistor, and a second synchronization pulse is applied to the second electrode of the third transistor and the gate electrode of the fourth transistor,
A semiconductor device characterized in that a scanning pulse output is output from at least one of the first electrodes of the first and third transistors. 2 At least 6 electrodes each having first and second electrodes serving as a source or drain and a gate electrode.
1st, 2nd, 3rd, 4th, 5th, 6th
The gate electrode of the first transistor is connected to the output terminal of the basic circuit in the previous stage, and the first electrode of the first transistor is connected to the second basic circuit. a first electrode of the second transistor is connected to a gate electrode of the third transistor, a first electrode of the third transistor is connected to a gate electrode of the fourth transistor, and a first electrode of the second transistor is connected to a gate electrode of the fourth transistor; 1st of 4 transistors
The electrode is connected to the input end of the above basic circuit in the subsequent stage,
First terminals of the fifth and sixth transistors are connected to first electrodes of the second and fourth transistors, respectively;
The electrodes are respectively grounded, the gate electrodes of the fifth and sixth transistors are connected to the first electrodes or gate electrodes of the subsequent second and fourth transistors, respectively, and the gate electrodes of the first and third transistors and the first A capacitive element is provided between the electrode and
A first synchronization pulse is applied to a second electrode of the first transistor, and a second synchronization pulse of the third transistor is applied to a second electrode of the first transistor.
A second synchronization pulse is applied to the electrode, and the second synchronization pulse is applied to the electrode.
A semiconductor device, wherein a power supply voltage is applied to the second electrode of the fourth transistor, and a scanning pulse output is output from at least one of the first electrodes of the first and third transistors. 3 At least 6 electrodes each having first and second electrodes serving as a source or drain and a gate electrode.
1st, 2nd, 3rd, 4th, 5th, 6th
The gate electrode of the first transistor is connected to the output terminal of the basic circuit in the previous stage, and the first electrode of the first transistor is connected to the second basic circuit. The second electrode of the second transistor is connected to the gate electrode of the third transistor, and the first electrode of the third transistor is connected to the first electrode of the fourth transistor and the gate electrode of the fourth transistor. The second electrode of the fourth transistor is connected to the input terminal of the basic circuit at the subsequent stage, and the first terminals of the fifth and sixth transistors are connected to the second and fourth transistors, respectively.
The second electrodes of the fifth and sixth transistors are respectively grounded, and the gate electrodes of the fifth and sixth transistors are connected to the second electrodes of the subsequent second and fourth transistors, respectively. A capacitive element is connected to the gate electrode and is provided between the gate electrode and the first electrode of the first and third transistors, and a first synchronization pulse is applied to the second electrode of the first transistor. , wherein a second synchronizing pulse is applied to the second electrode of the third transistor, and a scanning pulse output is output from at least one of the first electrodes of the first and third transistors. Device. 4. In claim 3, the first electrodes of the seventh and eighth transistors are connected to the first electrodes of the first and third transistors, respectively, and the second electrodes of the seventh and eighth transistors are connected to the first electrodes of the first and third transistors, respectively. A semiconductor device that is grounded, wherein the second synchronizing pulse is applied to the gate electrode of the seventh transistor, and the first synchronizing pulse is applied to the gate electrode of the eighth transistor. 5 In claim 3, a termination circuit including ninth, tenth, eleventh, twelfth, and thirteenth MOS field effect transistors is further connected to the final stage of the basic circuit, and The gate electrode is connected to the second electrode of the fourth transistor in the previous stage, the first electrode of the ninth transistor is connected to the first electrode of the tenth transistor and the gate electrode of the fifth transistor in the previous stage, and the first electrode of the ninth transistor is connected to the first electrode of the tenth transistor and the gate electrode of the fifth transistor in the previous stage. The first synchronization pulse is applied to the second electrode, the second electrode of the tenth transistor is grounded, the second synchronization pulse is applied to the gate electrode of the tenth transistor, and the gate of the eleventh transistor is applied to the second electrode. The second synchronous pulse is applied to the electrode and the second electrode, and the first electrode of the eleventh transistor is applied to the first electrode of the twelfth transistor, and the first electrode of the thirteenth transistor is applied to the first electrode of the eleventh transistor.
The gate electrode of the 12th transistor is connected to the first electrode of the transistor and the gate electrode of the 6th transistor in the previous stage, and the gate electrode of the 13th transistor is connected to the gate electrode of the 6th transistor in the previous stage. 1. A semiconductor device, wherein one synchronizing pulse is applied, and second electrodes of the tenth, twelfth, and thirteenth transistors are each grounded.