JPH0155460B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a thin display device in which transistors are arranged in a matrix array and used as a drive circuit.

[Technical background of the invention]

2. Description of the Related Art In recent years, thin display devices in which switching transistors are arranged in a matrix array and used as a driving circuit have been attracting attention. In this method, image information is accumulated in each dot of a switching transistor matrix provided on a substrate, and this image information is applied to each dot of a liquid crystal layer, EL layer, or EC layer provided on a matrix array. This method attempts to obtain the desired image by displaying the image at the desired position, and in principle, it is possible to realize a display device that is much thinner than the method using CRT, which was the mainstream of conventional display devices. In addition, the CRT's display principle is that a high-energy electron beam collides with a fluorescent material to emit light, so the entire screen is not always displayed, and the CRT utilizes the afterimage phenomenon of the human eye.
There was a problem with visibility due to Fritzker noise.
On the other hand, a display device using a transistor matrix array displays almost the entire time and can provide a more natural screen than a CRT. Furthermore, CRT
Compared to , it has the following characteristics: it can provide a flat screen, it does not require a high-voltage power supply, it does not require a vacuum area, and because it is an all-solid-state device, it is small and lightweight and has sufficient strength.

FIG. 1 is a schematic diagram showing the basic configuration of a transistor matrix array. The display screen is vertical.
It is divided into a matrix of n horizontal lines, and is divided into m·n unit pixels in total. At the intersections C ₁₁ , C ₁₂ ...C _ij ...C _no of each matrix, a pixel circuit with a memory function is constructed using a switching transistor, and the image information of each pixel is stored here, and the matrix array is processed according to this information. Display is realized in areas corresponding to each pixel of the liquid crystal, EL, or EC layer provided above.

A specific pixel circuit having a simple configuration as shown in FIG. 2 or 3 is used. This is because in order to obtain a high-definition display screen, the matrix size m·n becomes extremely large, and in order to create a matrix array with a high yield, a simpler circuit is desired. FIG. 2 shows a pixel circuit used to drive a liquid crystal when the display is substantially driven by direct current, and FIG. 3 shows an EL display, which is a circuit often used when performing an alternating current drive display. In FIG. 2, 21 is a switching transistor, 22 is a liquid crystal layer, and 23 is a capacitor for storing image signals. The gate of the transistor 21 is the i-th
It is connected to the jth address line X _i and its source electrode is connected to the jth data line Y _j .
The address line X _i and the data line Y _j are connected to power supplies of V(X _i ) and V(Y _j ), respectively. When a signal that turns on the transistor 21 is input to the address line X _i , the channel of the transistor 21 becomes conductive, and at this time, the image signal prepared for the data line Y _j is accumulated in the capacitor 23, and the date voltage V(X _i ) while the signal is stored in _Cs .
The liquid crystal 22 is driven in accordance with this accumulated image signal. Note that all other transistors on the address line X _i are also turned on at the same time, and the image signals V(Y ₁ ), V(Y ₂ )...V(Y _o ) prepared on each data line at that time are respectively turned on. is each pixel circuit
C _i1 , C _i2 ... are accumulated in C _io . Similarly, X _i+1 ,
Image signals are accumulated one _after another by sequentially driving each address line in this way, and signals for the entire screen are written.

Figure 3 shows two switching transistors 31.
A and 31b are used, and the image signal is stored in the capacitor 33 by switching the transistor 31a based on the same principle as shown in FIG. The operation timing of the pixel C _ij is the same as in the case of FIG. 2, when the power _supplies V (X _{i )} and V
(Y _j ). In the case of FIG. 3, the image signal controls the switching of the second transistor 31b to drive the display layer 32, such as an EL layer. In Fig. 3, unlike Fig. 2, the display layer 3
Since an alternating current voltage can be used as the voltage V _c applied to one end of 2, the EL layer can be driven.

The above is the operating principle of the thin display device using the transistor matrix array shown in FIG.

FIG. 4 is a diagram showing a cross-sectional structure of a liquid crystal display device using a conventional transistor matrix array. A ground conductor film 42 is provided on the entire surface of an insulating substrate 41, an insulating film 43 is further formed, and an address line 4 which also serves as a gate electrode of a transistor is formed thereon.
4 (44 ₁ , 44 ₂ , . . . ) are provided. Furthermore, a semiconductor thin film 46 (46 ₁ , 46 ₂ ,...) is formed in each pixel region via an insulating film 45 serving as a gate insulating film, and a source connected to a Y address line (not shown) is formed on each pixel region. Electrode 47 (47 ₁ , 47
₂ ,...), and display electrodes 48 ( ₄₈₁ , ₄₈₂ ,...) which serve as drain electrodes and storage capacitor electrodes are provided.
Further, the surface of this substrate is covered with an insulating film 49 having holes in the display pixel area. As mentioned above, the storage capacitor uses the display electrode 48 as one terminal electrode,
It is constructed using the ground conductor film 42 as the other terminal electrode and the insulating films 43 and 45 sandwiched therebetween. A liquid crystal display device is constructed by sandwiching a liquid crystal 52 between the transistor matrix array constructed in this way and a glass substrate 50 on which a transparent electrode 51 is formed.

In such a transistor matrix array, the process is relatively simple because the ground conductor film 42 is uniformly provided on the substrate. However, as shown in the figure, it often happens that the address line 44 ₁ or the display electrode 48 ₁ is short-circuited to the ground conductor film 42 through pinholes 53a, 53b, etc. in the insulating layer. Since the pinhole 53b causes only one pixel defect, the defect can be improved in proportion to the pinhole density of the insulating layer. However, the defect caused by the pinhole 53a appears as a line defect because all the pixel circuits driven by the address line 44 ₁ stop operating. Even if the pinhole density is improved, it is extremely difficult to completely eliminate such fatal line defects in large-scale matrix arrays.

FIG. 5 shows an example using a transistor matrix array that can eliminate defects caused by such pinholes. The difference from FIG. 4 is that the ground conductor films 42 (42 ₁ , 42 ₂ , . . . ) are arranged in a linear pattern parallel to the address lines 44 on the same plane. Of course, the ground conductor film 42 is used with the entire edge of the substrate biased to the ground potential.

However, in this structure, the address line 44
Since it is formed by patterning the same conductive film as the ground conductor film 42, the desired pattern may not be formed sufficiently due to mud from the mask for pattern formation, dust during exposure etching, etc. Some things happen.

This is because the address line 44 and the ground conductor film 44
This means that if the separation area becomes narrower, reliable separation becomes difficult.

Then, the address line 44 and the ground conductor film 42
If there is only one short-circuit location, this will appear as a line defect, similar to the defect caused by the pinhole 53a described above.

A short circuit between the address line and the ground electrode as described above can occur with an extremely high probability in a large-screen display device, a large-scale matrix array, or a high-definition matrix array. On the other hand, in a display device, even one fatal line defect cannot be allowed to occur, so it is difficult to realize a large-screen, high-definition display device with the conventional transistor matrix array structure. Ta.

[Purpose of the invention]

In view of the above points, it is an object of the present invention to provide a thin display device using a transistor matrix array structure that does not cause line defects on the display screen.

[Summary of the invention]

An overview of the present invention will be explained with reference to FIG. FIG. 5A is a plan view showing the structure of the address line and ground conductor film portion of a transistor matrix array according to the present invention, and FIG.
That is, in the present invention, first, a plurality of ground conductor films 62 (62 ₁ , 62 ₂ , . . . ) are disposed in a strip pattern on an insulating substrate 61, and then the ground conductor films 62 and 62 are disposed on the insulating substrate 61 via an insulating film 63. Address lines 64 (64 ₁ , 64 ₂ , . . . ) are arranged in parallel so as not to overlap.

Incidentally, since some deviation in the patterning position may actually occur, it is desirable to provide a gap 67 in advance so that the ground conductor film 62 and the address line 64 do not overlap even if there is a mask misalignment. The size of the gap 67 may be determined by considering the allowable amount of pattern alignment by the exposure device. For example, if the length from address lines X ₁ to X _n in FIG. 1 is approximately 10 cm or less, the gap 6
7 is about 2 μm, and for 10 cm or more, it is about 2 times the length.
Approximately 10 ^-5 times (for example, about 4 μm for 20 cm) is appropriate. However, this value naturally depends on the exposure device. In short, the presence of even a small gap 67 significantly increases the effects of the present invention. Further, in order to maintain complete insulation at the patterned end of the ground conductor film 62 of the insulating film 63, it is desirable that the thickness of the insulating film 63 be greater than the thickness of the ground conductor film 62.

〔Effect of the invention〕

In the present invention, contact between the address line and the ground conductor film is almost completely eliminated, and a thin display panel without line defects can be realized with high yield. In the structure of the present invention, contact between the address line and the ground conductor occurs when the pinhole 65 of the insulating film 63 overlaps the incomplete pattern area 66 of the ground conductor film 62, as shown in FIG. It's hot,
In recent IC manufacturing processes, the probability that both defects occur in the same location is extremely low.
It's hardly a problem.

[Embodiments of the invention]

FIGS. 7a and 7b are a projected plan view and a sectional view taken along the line BB' of a liquid crystal display device according to an embodiment of the present invention.
The size of the transistor matrix array is 220 address lines and 240 data lines, the pitch of the address lines is 200 μm, and the pitch of the data lines is 220.
250μm, total display area is 44 x 60mm, total 56400
It consists of several pixel circuits. Figures 7a and 7b show a part of it. To explain the manufacturing process, first, a plurality of ground conductive films 72 (72 ₁ , 72 ₂ , . . . ) are patterned using a transparent conductive film on a glass substrate 71 . Next, approximately 1500
A SiO ₂ film 73 with a thickness of Å is deposited, and address lines 74 (74 ₁ , 74 ₂ ,...) are formed on it with a thickness of
Formed with a 900Å Mo film. The ground conductor film 72 and the address line 74 are parallel to each other, and the gap 75 therebetween is 5 μm. Thereafter, a SiO ₂ film 76, which will become a gate oxide film, is deposited to a thickness of approximately 2500 Å using the CVD method, and then a transparent conductive film 77 77 (77 1 , 77 ₁ ,
77 ₂ , . . . ), and an amorphous silicon film 78 ( 78 ₁ , 78 ₂ , . . . ) is deposited to a thickness of 1500 Å and patterned to a desired size by exposure etching. And 5000 Å thick Al
The film serves as a source electrode and data line 79 (79 ₁ ,
79 ₂ ,...) and the drain electrode 80 (80 ₁ , 8
0 ₂ ,...). Then, a sputtered SiO ₂ film 81 with a thickness of 6000 Å is deposited on the display electrode 77.
The SiO ₂ film is removed by etching to complete the matrix array. The entire process is completed by placing a glass substrate 83 on which a transparent electrode 82 is formed to face the matrix array to form a display panel, and holding a liquid crystal 84 therebetween.

In order to examine the effects of this embodiment, a transistor matrix array of the conventional structure shown in FIGS. 4 and 5 was also prototyped. In each conventional array, the material, thickness, pattern size, and formation conditions of each electrode and insulating film are the same as in the embodiment shown in FIG. As a result, in the structure shown in Figure 4, 220
Approximately 5% of the book's address lines were short-circuited to the ground electrode, resulting in line defects. In addition, the temperature in Figure 5 was about 20%. On the other hand, in the case of this example, there was no such short circuit at all, and its effect was verified.

Note that the present invention is not limited to the above embodiments. For example, the ground conductor film is not limited to a transparent conductive film, and may be any metal material that can be patterned, such as Al or Mo, and the address line is not limited to Mo. Further, the insulating film is not limited to the SiO ₂ film, and its manufacture can also be performed using CVD, sputtering, coating, anodizing, or the like. In addition, thin film transistors are not limited to those using amorphous Si, but also polycrystalline Si,
Any material can be used as long as sufficient switching characteristics can be obtained, such as CdSe, CdS, Te, etc. The display material is not limited to liquid crystal, but may also be EL, EC, etc., and the unit pixel circuit configuration may be as shown in FIG. 3, for example.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a transistor matrix array, FIGS. 2 and 3 are diagrams showing an example of the configuration of a pixel circuit, and FIGS. 4 and 5 are diagrams of a liquid crystal display device using a conventional transistor matrix array. 6a and 6b are plan views showing the configuration of essential parts of a transistor matrix array according to the present invention, and its AA' cross-sectional view, and FIGS. 7a and 7b are a liquid crystal display device according to an embodiment of the present invention. FIG. 2 is a projected plan view and a cross-sectional view taken along line BB'. 61... Insulating substrate, 62 (62 ₁ , 62 ₂ ,
...)...Grounding conductor film, 63...Insulating film, 64 (6
4 ₁ , 64 ₂ ,...)...address line, 71...
Glass substrate, 72 (71 ₁ , 72 ₂ ,...)... Ground conductor film, 73... SiO ₂ film, 74 (74 ₁ , 74 ₂ ,
...) ... Address line, 76 ... SiO ₂ film, 7
7 (77 ₁ , 77 ₂ ,...)...Display electrode, 78 (7
8 ₁ , 78 ₂ ,...)...Amorphous Si film, 79
(79 ₁ , 79 ₂ ,...)... Source electrode/data line, 80 (80 ₁ , 80 ₂ ,...)... Drain electrode, 81... SiO ₂ film, 82... Transparent electrode, 83
...Glass substrate, 84...Liquid crystal.

Claims (1)

[Claims] 1. An insulating film is formed on an insulating substrate via a grounded conductor film, and on this insulating film, a plurality of address lines are arranged parallel to each other, and a plurality of address lines are arranged orthogonally to these address lines. A plurality of data lines arranged parallel to each other, a plurality of switching transistors arranged at each intersection of these data lines and address lines, and whose sources and gates are connected to the data lines and the address lines, respectively; In a thin display device that drives a display element using a transistor matrix array formed by integrating a storage capacitor having one end connected to the drain of a switching transistor and the other end connected to the ground conductor film, the ground conductor film are arranged in a plurality of strip-like patterns parallel to the address lines and not overlapping with the address lines. 2. The thin display device according to claim 1, wherein the display element is a liquid crystal, and the switching transistor is a thin film transistor.