JPH0157342B2 - - Google Patents
Info
- Publication number
- JPH0157342B2 JPH0157342B2 JP56017708A JP1770881A JPH0157342B2 JP H0157342 B2 JPH0157342 B2 JP H0157342B2 JP 56017708 A JP56017708 A JP 56017708A JP 1770881 A JP1770881 A JP 1770881A JP H0157342 B2 JPH0157342 B2 JP H0157342B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- group
- recording needle
- timing
- recording
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/385—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective supply of electric current or selective application of magnetism to a printing or impression-transfer material
- B41J2/41—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective supply of electric current or selective application of magnetism to a printing or impression-transfer material for electrostatic printing
Landscapes
- Dot-Matrix Printers And Others (AREA)
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
- Electrophotography Using Other Than Carlson'S Method (AREA)
Description
【発明の詳細な説明】
本発明は、静電記録装置の改良に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in electrostatic recording devices.
画像記録方式の中に静電記録方式があり、この
方法は、静電記録紙を使い、記録針電極には、記
録針電極Ｎ本を１グループとして複数のグループ
に分け、交互に画信号に合せた甲種の電圧を印
加、制御電極には主走査方向に順に乙種の電圧を
印加して甲、乙の合成電圧の所に電荷をチヤージ
させて記録を行なうものである。この記録方式は
高速性に優れ、高電圧を使うが電流は少なくてす
むという利点がある一方、大電圧小電流の為、近
傍する記録電極間の静電誘導によつて起きる原稿
にはない画像（画像ゴースト）が発生しうるとい
う問題点を持つている。 Among the image recording methods, there is an electrostatic recording method. This method uses electrostatic recording paper, and the recording needle electrodes are divided into a plurality of groups each consisting of N recording needle electrodes, and the recording needle electrodes are divided into a plurality of groups, and the recording needle electrodes are alternately applied to image signals. A combined voltage of type A is applied, and a voltage of type B is applied to the control electrode in order in the main scanning direction to charge a charge at the combined voltage of A and B to perform recording. This recording method has the advantage of high speed and uses a high voltage but requires a small amount of current. However, because the high voltage and small current are used, images that are not present in the original are generated due to electrostatic induction between nearby recording electrodes. This method has the problem that (image ghost) may occur.
以上のことを図に従つて説明する。 The above will be explained according to the figures.
第１図のごとく記録針電極R1〜R24は直線状に
配置され、制御電極C1〜C5，C1′〜C5′が記録針電
極をはさむ様に対向配置されている。 As shown in FIG. 1, the recording needle electrodes R 1 to R 24 are arranged in a straight line, and the control electrodes C 1 to C 5 and C 1 ' to C 5 ' are arranged opposite to each other so as to sandwich the recording needle electrodes.
そして、記録針電極は例えば６本を１グループ
として、Ａ、B2つのグループにわけられ、Ａグ
ループには第２図ｂに示す様に、Ｂグループには
第２図ｃに示す様に交互に負の電圧パルスが印加
される。 Then, the recording needle electrodes are divided into two groups, A and B, with six recording needle electrodes in one group. A negative voltage pulse is applied.
又制御電極には第２図ａに示す様に、記録針電
極への印加タイミングに同期して正の電圧パルス
ガ印加される。 Further, as shown in FIG. 2a, a positive voltage pulse is applied to the control electrode in synchronization with the timing of application to the recording needle electrode.
具体的には、記録針電極側のＡグループ（R1
〜R6，R13〜R18）に負の電圧を印加、次にＢグ
ループ（R7〜R12，R19〜R24）に印加、又、制御
電極側はC1〜C1′及びC2〜C2′、次にC2〜′C2′及び
C3〜C3′という様に正の電圧を印加していく。 Specifically, group A (R 1
~ R6 , R13 ~ R18 ), then applied to group B ( R7 ~ R12 , R19 ~ R24 ), and the control electrode side is applied to C1 ~ C1 ' and C 2 ~C 2 ′, then C 2 ~′C 2 ′ and
Positive voltages are applied in the order of C 3 to C 3 ′.
この正・負電圧パルスの両方が印加された所で
記録紙に電荷がチヤージされ、画像が形成され
る。 Electric charges are charged to the recording paper where both the positive and negative voltage pulses are applied, and an image is formed.
ここで、従来は記録針電極電極への電圧パルス
の印加タイミングはあるグループに印加した後直
ちに他のグループに印加する様になつており、且
つ記録針電極への電圧パルスと制御電極への電圧
パルスのタイミングが一致していると、例えばＡ
グループに電圧を印加した後Ｂグループへ電圧パ
ルスを印加する場合Ａグループの電圧パルスが−
XL（Ｖ）からOV向つて上昇していくと中で、Ｂ
グループに電圧パルスが加わるので、静電誘導に
よりＡグループの電圧が再び−XL（Ｖ）の方向へ
引きもどされる。 Here, conventionally, the timing of applying the voltage pulse to the recording needle electrode is such that it is applied to a certain group and then immediately applied to another group, and the voltage pulse to the recording needle electrode and the voltage to the control electrode are If the timing of the pulses matches, for example, A
When applying a voltage pulse to group B after applying voltage to group, the voltage pulse of group A is -
As it rises from XL (V) towards OV, B
Since a voltage pulse is applied to the group, the voltage of the A group is pulled back in the direction of -XL (V) due to electrostatic induction.
もしこの静電誘導により、第２図ｂのA′、
A″の様に、Ａグループの電圧が−XL（Ｖ）まで
低下すると、このときＡグループに対向する制御
電極に正の電圧パルスが印加されているので、画
像ゴーストが発生する。 If this electrostatic induction causes A' in Figure 2b,
When the voltage of the A group drops to -XL (V) as shown in A'', an image ghost occurs because a positive voltage pulse is applied to the control electrode facing the A group at this time.
Ｂグループにおいてもの同様な現象が生じる。 A similar phenomenon occurs in group B.
本発明は、この様な欠点を除去することを目的
とし、この様な目的は、複数本の記録針電極に対
向して制御電極を設け、該記録針電極にはＮ本を
１グループとして、各グループ毎に異なるタイミ
ングで電圧パルスを印加するとともに、該制御電
極には該記録針電極への電圧パルスの印加タイミ
ングに同期して、主走査方向に順次電圧パルスを
印加し、潜像形成媒体に静電潜像を形成する様に
した静電記録装置において、該記録針電極へ電圧
パルス印加するタイミングを各グループ間で重ね
るとともに、該制御電極には、該記録針電極への
電圧パルスの中間で、かつ前記記録針電極のグル
ープ間での印加電圧パルスの重なりが存在しない
タイミングで電圧パルスを印加する様にしたこと
を特徴とする静電記録装置によつて達成される。 The purpose of the present invention is to eliminate such drawbacks.The purpose of the present invention is to provide a control electrode facing a plurality of recording needle electrodes, and to form a group of N recording needle electrodes on the recording needle electrodes. Voltage pulses are applied to each group at different timings, and voltage pulses are sequentially applied to the control electrode in the main scanning direction in synchronization with the timing of applying voltage pulses to the recording needle electrode. In an electrostatic recording device configured to form an electrostatic latent image on the recording needle electrode, the timing of applying voltage pulses to the recording needle electrode is overlapped between each group, and the timing of applying the voltage pulse to the recording needle electrode is overlapped between the groups. This is achieved by an electrostatic recording apparatus characterized in that a voltage pulse is applied at an intermediate timing and at a timing where there is no overlap of applied voltage pulses between groups of recording needle electrodes.
以下本発明を実施例に基づいて詳細に説明す
る。 The present invention will be described in detail below based on examples.
第３図は、本発明による記録針電極と制御電極
への電圧パルスの印加タイミングを示すタイムチ
ヤートである。 FIG. 3 is a time chart showing the timing of applying voltage pulses to the recording needle electrode and control electrode according to the present invention.
図中ａはＡグループの記録針電極への電圧印加
タイミング、ｃはＢグループの記録針電極への電
圧印加タイミング、ｂ，ｄは、Ａグループ、Ｂグ
ループへの電圧印加タイミングに対する制御電極
への電圧印加タイミングをそれぞれ示す。 In the figure, a is the timing of voltage application to the recording needle electrode of group A, c is the timing of voltage application to the recording needle electrode of group B, and b and d are the timing of voltage application to the control electrode with respect to the timing of voltage application to group A and group B. The voltage application timings are shown respectively.
第３図から明らかな様に、本発明によれば、Ａ
グループ、Ｂグループへの電圧印加タイミングを
それぞれ時間ｔだけ重ね、かつ、制御電極への電
圧印加は、各グループへの電圧印加タイミングの
中央部近傍で行う様にした。 As is clear from FIG. 3, according to the present invention, A
The voltage application timings to the group and the B group were overlapped by a time t, and the voltage application to the control electrode was performed near the center of the voltage application timing to each group.
これにより、記録針電極、制御電極における電
圧波形は第４図に示す様になる。 As a result, the voltage waveforms at the recording needle electrode and the control electrode become as shown in FIG.
図において、ａは制御電極への電圧パルス、ｂ
はＡグループへ印加される電圧パルス、ｃはＢグ
ループへ印加される電圧パルスをそれぞれ示す。 In the figure, a is the voltage pulse to the control electrode, b
indicates a voltage pulse applied to the A group, and c indicates a voltage pulse applied to the B group.
図の様に例えばＡグループへの電圧パルスは、
Ｂグループへの電圧印加後ｔ時間後に立上がりは
じまる。 As shown in the figure, for example, the voltage pulse to group A is
The voltage starts to rise after t time after the voltage is applied to the B group.
従つて、Ｂグループへの電圧印加Ａグループの
記録針電極のインピーダンスは十分底くなつてお
り、従来の様に立上がりの途中で、静電誘導はに
よる−XL（Ｖ）方向への引き戻しがなくなる。 Therefore, when voltage is applied to group B, the impedance of the recording needle electrode of group A has sufficiently bottomed out, and there is no longer a pullback in the -XL (V) direction due to electrostatic induction in the middle of the rise as in the conventional case. .
このことはＢグループについても同様なことが
言える。 The same can be said about Group B.
又、記録針電極側の電圧パルスがオーバーラツ
プしている為、制御電極の電圧パルスタイミング
を、記録針電極へのパルスの中央近傍に印加する
ようにして、Ａ、Ｂオーバーラツプした所には、
制御電極側の電圧がかからないようにする。 Also, since the voltage pulses on the recording needle electrode side overlap, the voltage pulse timing of the control electrode is applied near the center of the pulses to the recording needle electrode, so that the overlap between A and B is as follows.
Make sure that voltage is not applied to the control electrode side.
以上の工夫により、静電誘導によるゴーストの
問題を防ぐことができる。 The above measures can prevent the problem of ghosts caused by electrostatic induction.
次に以上のことを実施するための回路を第５
図、第６図により説明する。 Next, we will create a fifth circuit to implement the above.
This will be explained with reference to FIG.
第５図において、INTは外部インターフエク
ス回路、cou１，cou２はカウンタ、SETはセツ
ト回路、RESETはリセツト回路、SFTはシフト
レジスタ、RA，RBはレジスタ、DVA，DVBは
Ａグループ及びＢグループの記録針電極の駆動回
路、CDCは制御電極駆動タイミング回路、
DVCDは制御電極駆動路である。 In Figure 5, INT is an external interface circuit, cou1 and cou2 are counters, SET is a set circuit, RESET is a reset circuit, SFT is a shift register, RA and RB are registers, and DVA and DVB are records of A group and B group. Needle electrode drive circuit, CDC is control electrode drive timing circuit,
DVCD is the control electrode drive path.
回路動作を第６図を用いて説明する。 The circuit operation will be explained using FIG. 6.
まず外部インターフエクス回路INTに信号が
入力し、クロツクはカウンタcou１，cou２へ、
画信号はｘビツトのシフトレジスタへ入力する。 First, a signal is input to the external interface circuit INT, and the clock is sent to counters cou1 and cou2.
The image signal is input to an x-bit shift register.
カウンタcou１はｘビツトの容量を持つカウン
タで、“ｘ”だけカウントするごとにキヤリー信
号がセツト回路SETに入力され、これによりシ
フトレジスタSFT内の画信号がレジスタRA，
RBに交互に入力される。 The counter cou1 is a counter with a capacity of x bits, and every time it counts by "x", a carry signal is input to the set circuit SET, and thereby the image signal in the shift register SFT is transferred to the register RA,
Alternately input to RB.
すなわち、第５図ａに示す様にｘカウント毎に
ｃ，ｄの如くセツト回路SETからセツト信号が
レジスタRA，RBに交互に入力し、シフトレジ
スタSFT内のＡグループ、Ｂグループのデータ
が交互に入力される。 That is, as shown in Fig. 5a, set signals from the set circuit SET are input alternately to the registers RA and RB as indicated by c and d every x counts, and the data of groups A and B in the shift register SFT are input alternately. is input.
レジスタRA，RB内のデータはｅ及びｆに示
す様に、リセツト回路RESETからのリセツト信
号（ｇ，ｈ）が入力されるまで保持される。リセ
ツト回路RESETはセツト回路SETからのセツト
信号を受けてからカウンタcou２のカウント値が
一定値になる毎にリセツト信号ｇ，ｈを出力す
る。記録針電極の駆動回路DVA，DVBは、レジ
スタRA，RBにデータが保持されている間電圧
パルスを記録針電極へ印加するものである。 The data in registers RA and RB are held as shown at e and f until reset signals (g, h) from the reset circuit RESET are input. After receiving the set signal from the set circuit SET, the reset circuit RESET outputs reset signals g and h every time the count value of the counter cou2 reaches a constant value. The recording needle electrode drive circuits DVA and DVB apply voltage pulses to the recording needle electrode while data is held in the registers RA and RB.
一方制御電極駆動タイミング回路CDCはセツ
ト回路SETからのセツト信号が入力されてから
一定時間後にｉの如くタイミング信号を制御電極
駆動回路DVCDへ入力して、起動をかけ、ｊの
タイミングで制御電極に電圧を印加する。 On the other hand, the control electrode drive timing circuit CDC inputs a timing signal such as i to the control electrode drive circuit DVCD after a certain period of time after the set signal from the set circuit SET is input, starts it up, and starts the control electrode at timing j. Apply voltage.
これにより主走査方向に順次静電記録が行なわ
れる。 As a result, electrostatic recording is performed sequentially in the main scanning direction.
以上述べた様に本発明によれば記録針電極への
電圧パルスの印加タイミングを重ね合せ、制御電
極へは、記録針電極への電圧印加タイミングの中
央部付近で印加するので、画像ゴーストの発生を
防止することが可能となる。 As described above, according to the present invention, the timing of applying voltage pulses to the recording needle electrode is overlapped, and the voltage pulse is applied to the control electrode near the center of the timing of voltage application to the recording needle electrode, so that image ghosting occurs. This makes it possible to prevent
尚本発明は以上述べた回路に限定されるもので
はない。 Note that the present invention is not limited to the circuit described above.
第１図は記録針電極と制御電極の配置を示す
図、第２図は従来の電圧パルス印加タイミング及
び電圧波形を示すタイムチヤート第３図は本発明
による電圧パルス印加タイミングを示すタイムチ
ヤート第４図は本発明の印加タイミングによる電
圧波形を示すタイムチヤート第５図は本発明に用
いる回路を示す図、第６図は第５図の動作タイム
チヤートである。
図中C1〜C5，C1′〜C5′は制御電極、R1〜R24は
記録針電極、INTは外部インターフエクス回路、
cou１，cou２はカウンタ、SETはセツト回路、
RESETはリセツト回路、CDCは制御電極駆動タ
イミング回路、DVCDは制御電極駆動回路、
SFTはシフトレジスタ、RA，RBはレジスタ、
DVA，DVBはＡグループ、Ｂグループの記録針
電極駆動回路である。
FIG. 1 is a diagram showing the arrangement of recording needle electrodes and control electrodes. FIG. 2 is a time chart showing the conventional voltage pulse application timing and voltage waveform. FIG. 3 is a time chart showing the voltage pulse application timing according to the present invention. FIG. 5 is a diagram showing a circuit used in the present invention, and FIG. 6 is an operation time chart of FIG. 5. In the figure, C 1 to C 5 and C 1 ′ to C 5 ′ are control electrodes, R 1 to R 24 are recording needle electrodes, INT is an external interface circuit,
cou1 and cou2 are counters, SET is a set circuit,
RESET is the reset circuit, CDC is the control electrode drive timing circuit, DVCD is the control electrode drive circuit,
SFT is a shift register, RA, RB are registers,
DVA and DVB are recording needle electrode drive circuits for A group and B group.
Claims (1)
け、該記録針電極にはＮ本を１グループとして、
複数の各グループ毎に異なるタイミングで電圧パ
ルスを印加するとともに、該制御電極には該記録
針電極への電圧パルスの印加タイミングに同期し
て、主走査方向に順次電圧パルスを印加し、潜像
形成媒体に静電潜像を形成する様にした静電記録
装置において、該記録針電極へ電圧パルス印加す
るタイミングを各グループ間で重ねるとともに、
該制御電極には、該記録針電極への電圧パルスの
中間部で、かつ前記記録針電極のグループ間での
印加電圧パルスの重なりが存在しないタイミング
で電圧パルスを印加する様にしたことを特徴とす
る静電記録装置。1. A control electrode is provided opposite to a plurality of recording needle electrodes, and the recording needle electrodes have N electrodes in one group.
A voltage pulse is applied to each of the plurality of groups at different timings, and voltage pulses are sequentially applied to the control electrode in the main scanning direction in synchronization with the timing of applying the voltage pulse to the recording needle electrode, thereby forming a latent image. In an electrostatic recording device that forms an electrostatic latent image on a forming medium, the timing of applying voltage pulses to the recording needle electrode is overlapped between each group, and
A voltage pulse is applied to the control electrode at a middle portion of the voltage pulse applied to the recording needle electrode and at a timing where there is no overlap of applied voltage pulses between groups of the recording needle electrode. An electrostatic recording device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1770881A JPS57132167A (en) | 1981-02-09 | 1981-02-09 | Electrostatic recorder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1770881A JPS57132167A (en) | 1981-02-09 | 1981-02-09 | Electrostatic recorder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57132167A JPS57132167A (en) | 1982-08-16 |
| JPH0157342B2 true JPH0157342B2 (en) | 1989-12-05 |
Family
ID=11951260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1770881A Granted JPS57132167A (en) | 1981-02-09 | 1981-02-09 | Electrostatic recorder |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57132167A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5255533A (en) * | 1975-10-31 | 1977-05-07 | Hitachi Denshi Ltd | Electrostatic recording device |
-
1981
- 1981-02-09 JP JP1770881A patent/JPS57132167A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57132167A (en) | 1982-08-16 |
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