JPH0158898B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock pulse generation circuit used for extracting each information bit of information sent by packet transmission, and in particular to a clock pulse generation circuit that is automatically phase-aligned with each information bit of packet transmission information. The present invention relates to a clock pulse generation circuit that generates clock pulses.

Packet transmission improves transmission accuracy and transmission efficiency by transmitting various types of information in blocks, and is used, for example, to transmit character signals in character information transmission television systems. In this case, the text information transmission television system multiplexes text signals (including graphics) onto multiple lines during the vertical retrace period of the television signal and transmits the packets. Character signals sent through transmission are sequentially written into a memory, and the memory information is read out and displayed on the television screen at a cycle synchronized with the horizontal and vertical scanning cycles of the television. Therefore, in a color television signal on which character information is multiplexed, for example, as shown in one horizontal scanning period in FIG. 1, a 296-bit character signal CS is transmitted following a horizontal synchronizing signal HS and a color burst signal CB. It is configured so that it can be accessed. This character signal CS consists of a running reference signal RI and information data ID, and the running reference signal RI is composed of a 2.86MHz 16-bit pulse, as shown in an enlarged view in Figure 2, and is composed of information data. ID is 5.73M synchronized with the pulse period in the running reference signal RI
It is a signal expressed by the non-return-to-zero method (MRZ) with a bit rate of Hz.

Therefore, when receiving a character signal CS configured as described above, a clock pulse generation circuit is provided inside the character information receiver to generate a clock pulse whose phase and rate match each bit of the received character signal CS. Each information bit of the information data ID is extracted by sampling the received character signal CS using a clock pulse.
In this case, the clock pulse generation circuit performs pull-in oscillation by inputting the 2.86MHz run-in reference signal RI extracted separately from the received character signal CS, thereby creating an oscillation circuit that maintains oscillation for approximately one horizontal scanning period. This is used to match the phase and rate of the clock pulses generated with each bit of the received character signal CS.

However, the clock pulse generation circuit with the above configuration uses an oscillation circuit that continues to oscillate by being drawn in by the running reference signal RI sent only at the beginning of the received character CS. The period and phase of the generated clock pulse are determined by the temporary running reference signal RI.
It will be uniquely determined by. As a result, if the phase of the character signal CS changes for some reason, the phase of the sampling clock pulse for each bit of the character signal CS will shift, making it impossible to perform accurate signal processing.

Therefore, an object of the present invention is to provide a clock pulse generation circuit that can always obtain phase-synchronized clock pulses even if the phase of the information bits of the information signal sent by packet transmission varies for some reason. It is.

In order to achieve this object, the clock pulse generation circuit according to the present invention is configured to automatically adjust the phase of the clock pulse generated in accordance with the phase of each information bit of the information signal sent by bucket transmission. It is something. Hereinafter, a clock pulse generation circuit according to the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a circuit diagram showing an embodiment of the clock pulse generation circuit according to the present invention, and particularly shows the case where the clock pulse generation circuit is applied to a text information transmission television receiver. In the figure, 1 inputs a character signal CS as an information signal sent by packet transmission, and this character signal
This is an edge detection circuit that detects the edges of each bit signal of CS, that is, the leading edge and the trailing edge, and generates a sampling pulse SP with a constant pulse width. a second differentiating circuit 8 consisting of a capacitor 6 and a resistor 7 for differentiating the character signal CS inverted by the inverter 5;
The OR gate 9 receives the outputs of the differentiating circuits 4 and 8 as inputs, respectively. Reference numeral 10 denotes a D-type flip-flop circuit constituting a phase discrimination circuit, which inputs a clock pulse CP output from a clock pulse selection circuit 17 to be described later.
In addition, the sampling signal SP is used as the clock input CK, and a phase discrimination output is generated in which the output Q is set to "H" when the clock pulse CP lags with respect to the sampling pulse SP, and the output is set to "H" when the clock pulse CP is ahead. do. 11 is a sampling pulse SP generated from the edge detection circuit 1.
This is a 5-bit up-down counter with clock input CK, and flip-flop circuit 10.
The output Q is used as the control input DO for the down mode, and the output is used as the control input UP for the up mode. In addition, this up-down counter 11
inputs to its preset input PR the horizontal synchronizing signal HS as a transmission start signal in packet transmission, which is extracted separately from the television signal.
Each time this horizontal synchronizing signal HS is supplied, it is preset to a predetermined value, and here it is set to "15" which is approximately 1/2 of the full count value "32". 12 is the output terminal of up-down counter 11
Input the binary count value output from Q _A ~ Q _E a ~
Decoder that decodes as e, 13 is 28.6MHz
14 is a D-type flip-flop circuit which uses character signal CS as clock input CK and horizontal synchronization signal HS as clear input CLR; 15 is generated from oscillator 13;
By inputting a 28.6MHz signal and dividing the frequency by 5, it matches the basic bit rate of the character signal CS.
This is a frequency divider that generates an original clock pulse CP' of 5.73 MHz, and uses the signal sent from the output terminal Q of the flip-flop circuit 14 as a clear input CLR. A delay line 16 constitutes a delay circuit having a plurality of delay output terminals, and has the same number of output terminals O ₁ to O ₃₁ as the number of output terminals of the decoder 12, and is supplied from the frequency divider 15. While sequentially delaying the original clock pulse CP', each output terminal _O0 ~
It is configured to output sequentially from _O31 . 1
7 selects the output generated from the output end of the delay line 16 corresponding to the output of the decoder 12,
This is a clock pulse selection circuit that sends out a clock pulse CP that is phase-synchronized with each bit of a character signal CS, and is connected to a decoder 12 and a delay line 1.
The AND gates 18 ₁ to 18 ₃₂ determine the coincidence of the signals generated from the corresponding output terminals of the AND gates 18 1 to 18 32 , and the OR gate 19 receives the outputs of the AND gates 18 ₁ to 18 ₃₂ as inputs.

In the clock pulse generation circuit configured in this manner, the oscillator 13 continues to send out an oscillation output of 28.6MHz. When the horizontal synchronizing signal HS as a transmission start signal shown in FIG. 4c is supplied prior to the packet transmission of the character signal CS shown in FIG. 4a, the flip-flop circuit 14 is cleared and the signal at the output terminal Q is is “L” as shown in Figure 4d.
becomes. And this flip-flop circuit 14
The signal sent out from the output Q of is applied as a clear signal to the clear input CLR of the frequency divider 15, so that the frequency divider 15 remains inactive as shown in FIG. 4f.

Next, when the character signal CS is supplied, the flip-flop circuit 14 is set so that its output Q becomes "H" as shown in FIG. is canceled. When the clear input is released, the frequency divider 15
28.6M output from the oscillator 13 as shown in Figure 4e
The oscillation output of Hz is divided by 5 to 5.73M as shown in Figure 4 f.
An original clock signal CP' of Hz is generated, and this original clock pulse CP' corresponds to the basic bit rate of the character signal CS. Therefore, the original clock pulse
The start of generation of CP' is always synchronized with the rising edge of the character signal CS and is supplied to the delay line 16, so that each output terminal of the delay line 16
Original clock pulses sequentially delayed from O ₀ to O ₃₁
CP′ will be output.

On the other hand, the up-down counter 11 is set to a preset value of "15", which is approximately 1/2 of the predetermined full count value, each time the horizontal synchronizing signal HS obtained by separating the television signal is supplied. , when the character signal CS is not supplied, the preset output of the up-down counter 11 is decoded by the decoder 12, and the output is sent from the output terminal _O15 . Then, the original clock pulse generated from the frequency divider 15
CP' is sequentially delayed in the delay line 16, and each time an output is generated from the output terminal _O15 , a coincidence output is sent only from the AND gate ₁₈₁₅ . Then, the output of this AND gate ₁₈₁₅ , that is, the original clock pulse CP, is sent to the delay line 16 with a delay time of 6 ns x 15 = 1 tap.
The signal delayed by 90 ns will be sent out as the clock pulse CP shown in FIG. 4g. In other words, the clock pulse selection circuit 17
This means that the delayed output of the delay line 16 is selected in accordance with the output of 2, and the phase of the clock pulse CP is accordingly adjusted.

On the other hand, when the edge detection circuit 1 is also supplied with the character signal CS shown in FIG.
differentiates the character signal CS, and the capacitor 6 and resistor 7 forming the second differentiating circuit 8 differentiate the inverted signal of the character signal CS supplied via the inverter 5. The thus differentiated output signals of the first and second differentiating circuits 4 and 8 are taken out via the OR gate 9, so that only the positive polarity output is output from the fourth differentiating circuit.
As shown in FIG. b, it is sent out as a sampling signal SP with a constant pulse width synchronized with the edge portion of each bit of the character signal CS.

The sampling pulse generated in this way
SP is a clock pulse selection circuit 16 in the flip-flop circuit 10 constituting the phase discrimination circuit.
The phase relationship with the clock pulse CP output from the clock pulse CP is determined. In other words, the most suitable phase of the clock pulse CP for sampling each bit signal of the character signal CS is when its leading edge is located in the center of each bit constituting the character signal CS, as shown in Figure 4g. be. In this case, the clock pulse CP is 1/1/2 of the basic bit period of the character signal CS.
2, in order to position the leading edge of the clock pulse CP approximately in the center of each bit of the character signal CS, the leading edge of the sampling pulse SP must be phase synchronized to match the trailing edge of the clock pulse CP. That would be a good thing. sampling pulse
D-type flip-flop circuit 10 with SP as clock input and clock pulse CP as input D
is in an unstable state when the clock pulse CP is synchronized with the character signal CS as described above, and one of the outputs Q becomes "H". For example, when the output becomes "H",
The up-down counter 11 is set to the up mode, counts the sampling pulse SP, and the count value increases from the preset value "15" to "16". As a result, the decoder 12 generates an output from the output terminal _O16 , and accordingly, the AND gate ₁₈₁₆ outputs the output terminal of the delay line 16.
In order to select and take out the output of O ₁₆ , the clock pulse CP output from the OR gate 19 is set to delay line 1 with respect to the previous clock pulse CP.
It is delayed by 6 ns, which is the one-tap delay time of 6.

When the next sampling pulse SP is supplied, the flip-flop circuit 10 determines its phase relationship with the clock pulse CP. In this case, since the clock pulse CP is delayed by 6 ns, the sampling pulse SP is generated during the "H" period of the clock pulse CP, and the output Q becomes "H" and the output Q goes up. Down counter 11 is set to down mode. Therefore, the up-down counter 11 is counted down to "15" again by the sampling pulse SP. In this way, when the leading edge of the sampling pulse and the trailing edge of the clock pulse CP match in phase, the up-down counter 11 alternately performs one-count up and down operations. As a result, the phase of the clock pulse CP becomes a signal that fluctuates by one tap delay of the delay line 16. However, since the one tap delay time in this case is extremely short at 6 ns, there is no problem, and the sampling pulse SP, that is, the clock pulse CP whose phase is aligned with the character input signal CS as an external input signal. .

Next, if the phase of the character signal CS advances for some reason and the phase of the clock pulse CP is significantly delayed, the sampling pulse SP and the clock pulse
Flip-flop circuit 10 to match CP
The output Q of the up-down counter 11 becomes "H" and the up-down counter 11 is set to the down mode. As a result, the up-down counter 11 is sequentially down-counted every time the sampling pulse SP is supplied, and each time the count value decreases by one count, the output generation end of the decoder 12 is moved downward one by one. It turns out. Therefore, the output selection end of the clock pulse selection circuit 17 for the delay line 16 is also shifted to the lower direction, and accordingly, the phase of the clock pulse CP is advanced by 6 ns every time the sampling pulse SP is generated.

Next, if for some reason the phase of the character signal CS is delayed and the phase of the clock pulse CP is greatly advanced, the sampling pulse SP and clock pulse CP
do not match, and accordingly, the output of the flip-flop circuit 10 becomes "H" and the up-down counter 11 is set to the up mode. As a result, the up-down counter 11 is sequentially incremented every time the sampling pulse CP is generated, and each time the count value increases by one count, the output generation end of the decoder 12 is moved upward one by one. Become. Therefore, delay line 1 in clock pulse selection circuit 17
The output selection terminal for 6 is also shifted to the upper direction, and along with this, every time the sampling pulse SP is generated,
The phase of the clock pulse CP is delayed by 6 ns. A sampling pulse that operates like this
By performing this every time SP occurs, the phase of the clock pulse CP is successively delayed to match the phase of the character signal CS.

Each time the horizontal synchronizing signal HS is generated, the up-down counter 11 is preset again and this operation is repeated in sequence, and along with this, the sampling pulse, that is, the character signal CS as an external input signal is automatically This results in a clock pulse CP whose phase is adjusted exactly.
In this case, the clear control is applied to the frequency divider 15 at the same time as the horizontal synchronizing signal HS is generated, and the clear control is canceled at the same time as the character signal CS is supplied. Character signal CS of original clock pulse CP' output from frequency generator 15
The phase relationship between the clock pulses CP and CP is substantially constant, and accordingly, the phase adjustment range of the clock pulse CP can be made relatively narrow.

In the above embodiment, a case has been described in which a delay line is used as a delay circuit having a plurality of output terminals that generate sequentially delayed outputs, but the present invention is not limited to this. ,
Needless to say, a shift register that sequentially shifts input signals using shift pulses may be used.

As explained above, the clock pulse generation circuit according to the present invention generates information bits by dividing the output of an oscillation circuit that oscillates a signal having a frequency that is a positive multiple of the frequency of information bits sent by packet transmission. This generates an original clock pulse with a period corresponding to the fundamental bit rate of the clock. Since this frequency divider starts the frequency dividing operation at the leading edge of the information bit supplied following the transmission start signal of packet transmission, the original clock pulse to be generated is transmitted by packet transmission. The amount of phase control required when controlling the phase of the original clock pulse to obtain a clock pulse that matches the phase of the information bits is reduced, and as a result, phase transmission control and This has the excellent effect of simplifying circuit configuration.

[Brief explanation of drawings]

Fig. 1 is a waveform diagram showing a television signal in which packet-transmitted character signals are multiplexed, Fig. 2 is an enlarged waveform diagram of the character signal shown in Fig. 1, and Fig. 3 is a circuit diagram of a clock pulse generation circuit according to the present invention. Figure, Figure 4a
-g are operation waveform diagrams of each part in FIG. 3. 1... Edge detection circuit, 10, 14... Flip-flop circuit, 11... Up/down counter, 12... Decoder, 13... Oscillator, 15...
...Frequency divider, 16...Delay line, 17...Clock pulse selection circuit.

Claims (1)

[Claims] 1. In a clock pulse generation circuit that generates a clock pulse used for extracting each information bit of an information signal sent with a transmission start signal indicating the start of packet transmission, the edge of each information bit of the information signal is detected. an edge detection circuit that generates a sampling pulse based on the transmission start signal; an up-down counter that is preset to a predetermined value determined in advance by the transmission start signal and uses the sampling pulse as a count input; an oscillator that generates an original clock pulse having a period; a flip-flop circuit that is cleared by the transmission start signal and set by the information signal; and a flip-flop circuit that is cleared by the clear output of the flip-flop circuit and has a set output. a frequency divider that divides the original clock signal output from the oscillator by N to output a clock pulse having a period matching the basic bit rate of the information signal; and a clock pulse output from the frequency divider. a delay circuit that receives as input and sequentially outputs delayed signals from a plurality of output terminals; and a clock pulse selection circuit that selects and sends out clock pulses output from each output terminal of the delay circuit according to the output of the up-down counter. Then, it is determined whether the phase of the trailing edge portion of the clock pulse outputted from this clock pulse selection circuit leads or lags the leading edge of the sampling pulse, and if the clock pulse is in the lag phase, the up-down counter is turned down. and a phase discrimination circuit for controlling the up-down counter to the down mode when the clock pulse is in an advanced phase, so that the clock pulse output from the clock pulse selection circuit is always sent by the packet transmission. A clock pulse generating circuit is characterized in that the clock pulse generating circuit matches the phase of each information bit of an incoming information signal.