JPH0161613U - - Google Patents
Info
- Publication number
- JPH0161613U JPH0161613U JP15715387U JP15715387U JPH0161613U JP H0161613 U JPH0161613 U JP H0161613U JP 15715387 U JP15715387 U JP 15715387U JP 15715387 U JP15715387 U JP 15715387U JP H0161613 U JPH0161613 U JP H0161613U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- input terminal
- inputs
- digital
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 1
Landscapes
- Transmission And Conversion Of Sensor Element Output (AREA)
Description
第1図はこの考案の一実施例を示す図、第2図
は従来のR/D変換装置を示す図である。
図において1は象限選択回路、2は余弦乗算器
、3は正弦乗算器、4は引き算器、5はアナログ
・デイジタル変換器、6は符号反転器、7は加算
器、8はレジスタ、9は符号判定器、10は位相
検波器、11は電圧制御発振器、12は可逆カウ
ンタ、13は選択器である。なお、各図中同一符
号は同一、又は相当部分を示す。
FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional R/D conversion device. In the figure, 1 is a quadrant selection circuit, 2 is a cosine multiplier, 3 is a sine multiplier, 4 is a subtracter, 5 is an analog-to-digital converter, 6 is a sign inverter, 7 is an adder, 8 is a register, and 9 is a 10 is a phase detector, 11 is a voltage controlled oscillator, 12 is a reversible counter, and 13 is a selector. Note that the same reference numerals in each figure indicate the same or equivalent parts.
Claims (1)
、デイジタルの角度の正弦の値をアナログ信号に
掛け算する正弦乗算器と、アナログの信号とデイ
ジタルの角度信号を入力し、デイジタルの角度の
余弦の値をアナログ信号に掛け算する余弦乗算器
と、2つの信号を引き算する引き算器と、アナロ
グの信号を入力しデイジタルの信号に変換するア
ナログ・デイジタル変換器と、デイジタルの信号
を入力しその符号を反転する符号反転器と、2つ
のデイジタル信号を入力しその一方を選択出力す
る選択器と、2つの信号を加え合わせる加算器と
、デイジタル値を一時保持するレジスタとアナロ
グの信号を入力しその符号を判定する符号判定器
とを備えたトラツキング型レゾルバ・デイジタル
変換器において、第1の入力端にレゾルバ信号の
一方の正弦波の信号を入力し、第2の入力端に前
記レジスタのデイジタル信号を入力しデイジタル
信号の角度の余弦の値を正弦波の信号に掛け算す
る余弦乗算器と、第1の入力端にレゾルバ信号の
一方の余弦波の信号を入力し、第2の入力端に前
記レジスタのデイジタル信号を入力しデイジタル
信号の角度の正弦の値を余弦波の信号に掛け算す
る正弦乗算器と、第1の入力端に前記余弦乗算器
の出力を入力し、第2の入力端に前記正弦乗算器
の出力を入力し、2つの信号を引き算する引き算
器と、入力端に前記引き算器の出力を入力し、デ
イジタル信号に変換するアナログ・デイジタル変
換器と、入力端に基準信号を入力し、その符号を
判定する符号判定器と、入力端に前記アナログ・
デイジタル変換器の出力を入力し符号を反転する
符号反転器を、第1の入力端に前記アナログ・デ
イジタル変換器の出力を入力し、第2の入力端に
前記符号反転器の出力を入力し、第3の入力端に
前記符号判定器の出力を入力し、第3の入力端に
与えられた信号により第1の入力端に与えられた
信号又は第2の入力端に与えられた信号を選び出
力する選択器と、第1の入力端に前記選択器の出
力を入力し、第2の入力端に前記レジスタのデイ
ジタル信号を入力し加え合わせる加算器と、第1
の入力端にクロツクを入力し、第2の入力端に上
記加算器の出力を入力し第1の入力端に与えられ
た信号で第2の入力端に与えられた信号を一時保
持するレジスタとを備えたことを特徴とするレゾ
ルバ・デイジタル変換装置。 A sine multiplier that inputs an analog signal and a digital angle signal and multiplies the analog signal by the sine value of the digital angle; and a sine multiplier that inputs an analog signal and a digital angle signal and multiplies the digital angle cosine value by the analog signal. A cosine multiplier that multiplies a signal, a subtracter that subtracts two signals, an analog-to-digital converter that inputs an analog signal and converts it to a digital signal, and a code that inputs a digital signal and inverts its sign. An inverter, a selector that inputs two digital signals and selects and outputs one of them, an adder that adds the two signals, a register that temporarily holds the digital value, and an analog signal that inputs and determines its sign. In a tracking type resolver-digital converter equipped with a sign determiner, one sine wave signal of the resolver signal is inputted to the first input terminal, and the digital signal of the register is inputted to the second input terminal. A cosine multiplier that multiplies a sine wave signal by the value of the cosine of the angle of the signal, a cosine wave signal of one of the resolver signals is input to a first input terminal, and a digital signal of the register is input to a second input terminal. a sine multiplier that inputs the value of the sine of the angle of the digital signal and multiplies the cosine wave signal; a sine multiplier that inputs the output of the cosine multiplier to a first input terminal, and inputs the output of the cosine multiplier to a second input terminal; a subtracter that inputs the output of the subtracter and subtracts two signals; an analog-to-digital converter that inputs the output of the subtracter to the input terminal and converts it into a digital signal; A sign determiner for determining the sign, and the analog signal at the input end.
A sign inverter that inputs the output of a digital converter and inverts its sign is connected to a first input terminal of which the output of the analog-to-digital converter is input, and a second input terminal of which the output of the sign inverter is input. , the output of the sign determiner is input to the third input terminal, and the signal given to the first input terminal or the signal given to the second input terminal is determined by the signal given to the third input terminal. a selector that selects and outputs; an adder that inputs the output of the selector to a first input terminal, inputs the digital signal of the register to a second input terminal, and adds the digital signal;
A register that inputs a clock to the input terminal of the register, inputs the output of the adder to the second input terminal, and temporarily holds the signal given to the second input terminal with the signal given to the first input terminal. A resolver digital conversion device characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15715387U JPH0161613U (en) | 1987-10-14 | 1987-10-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15715387U JPH0161613U (en) | 1987-10-14 | 1987-10-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0161613U true JPH0161613U (en) | 1989-04-19 |
Family
ID=31436348
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15715387U Pending JPH0161613U (en) | 1987-10-14 | 1987-10-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0161613U (en) |
-
1987
- 1987-10-14 JP JP15715387U patent/JPH0161613U/ja active Pending
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