JPH0164752U - - Google Patents

Info

Publication number
JPH0164752U
JPH0164752U JP1987159976U JP15997687U JPH0164752U JP H0164752 U JPH0164752 U JP H0164752U JP 1987159976 U JP1987159976 U JP 1987159976U JP 15997687 U JP15997687 U JP 15997687U JP H0164752 U JPH0164752 U JP H0164752U
Authority
JP
Japan
Prior art keywords
processing unit
central processing
register file
received data
performs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987159976U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987159976U priority Critical patent/JPH0164752U/ja
Publication of JPH0164752U publication Critical patent/JPH0164752U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案実施例の構成の一例を示すブロ
ツク図、第２図は第１の従来例の構成例を示すブ
ロツク図、第３図は第２の従来例の構成例を示す
ブロツク図である。 １，２，２′，２″，３，３′……ＣＰＵ、４
……伝送回路、５……入力接点、６……リレー、
７……レジスタフアイル、８……デユアルポート
ＲＡＭ、９……入力インタフエース、１０……出
力インタフエース。 Fig. 1 is a block diagram showing an example of the configuration of the embodiment of the present invention, Fig. 2 is a block diagram showing an example of the configuration of the first conventional example, and Fig. 3 is a block diagram showing an example of the configuration of the second conventional example. It is. 1, 2, 2', 2'', 3, 3'...CPU, 4
...Transmission circuit, 5...Input contact, 6...Relay,
7...Register file, 8...Dual port RAM, 9...Input interface, 10...Output interface.

Claims (1)

【実用新案登録請求の範囲】 受信データの伝送処理を行う第１の中央演算処
理装置と、 該第１の中央演算処理装置により処理された受
信データを記憶するための書込み読み出しが非同
期に同時に行えるレジスタフアイルと、 該レジスタフアイルに記憶されたデータに基い
てシーケンス処理を行う第２の中央演算処理装置
と を具えたことを特徴とする信号伝送装置。[Claims for Utility Model Registration] A first central processing unit that performs transmission processing of received data, and writing and reading for storing the received data processed by the first central processing unit can be performed simultaneously and asynchronously. A signal transmission device comprising: a register file; and a second central processing unit that performs sequence processing based on data stored in the register file.
JP1987159976U 1987-10-21 1987-10-21 Pending JPH0164752U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987159976U JPH0164752U (en) 1987-10-21 1987-10-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987159976U JPH0164752U (en) 1987-10-21 1987-10-21

Publications (1)

Publication Number Publication Date
JPH0164752U true JPH0164752U (en) 1989-04-25

Family

ID=31441653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987159976U Pending JPH0164752U (en) 1987-10-21 1987-10-21

Country Status (1)

Country Link
JP (1) JPH0164752U (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5553720A (en) * 1978-10-18 1980-04-19 Hitachi Denshi Ltd Data transfer control system
JPS55153027A (en) * 1979-05-15 1980-11-28 Matsushita Electric Ind Co Ltd Interface circuit
JPS576954A (en) * 1980-06-13 1982-01-13 Nec Corp Multiprocessor system
JPS5983235A (en) * 1982-11-05 1984-05-14 Nec Corp Interface system between processors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5553720A (en) * 1978-10-18 1980-04-19 Hitachi Denshi Ltd Data transfer control system
JPS55153027A (en) * 1979-05-15 1980-11-28 Matsushita Electric Ind Co Ltd Interface circuit
JPS576954A (en) * 1980-06-13 1982-01-13 Nec Corp Multiprocessor system
JPS5983235A (en) * 1982-11-05 1984-05-14 Nec Corp Interface system between processors

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