JPH0165573U - - Google Patents
Info
- Publication number
- JPH0165573U JPH0165573U JP1987160242U JP16024287U JPH0165573U JP H0165573 U JPH0165573 U JP H0165573U JP 1987160242 U JP1987160242 U JP 1987160242U JP 16024287 U JP16024287 U JP 16024287U JP H0165573 U JPH0165573 U JP H0165573U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- circuit
- counter circuit
- counting
- video
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002131 composite material Substances 0.000 claims 1
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Television Signal Processing For Recording (AREA)
Description
第1図はこの考案の映像有無判定装置の1実施
例のブロツク図、第2図a〜fは第1図の動作説
明用のタイミングチヤートである。
3……カウンタ回路、7……ラツチ回路、8…
…比較回路、9……動作パルス発生回路。
FIG. 1 is a block diagram of one embodiment of the video presence/absence determining device of this invention, and FIGS. 2 a to 2 f are timing charts for explaining the operation of FIG. 1. 3...Counter circuit, 7...Latch circuit, 8...
...Comparison circuit, 9...Operation pulse generation circuit.
Claims (1)
設けられ、映像信号の入力の有無を判定する映像
有無判定装置において、 前記映像機器の入力信号を同期分離して得られ
た複合同期信号の垂直同期パルスが存在する期間
のパルス数をデジタル計数するカウンタ回路と、 前記カウンタ回路の計数データを1フイールド
遅延保持するラツチ回路と、 前記所定期間に計数される正規パルス数の基準
データと前記計数データとをフイールド毎に比較
し、判定結果の信号を出力する比較回路と、 前記カウンタ回路の計数終了毎にレベル反転す
る前記カウンタ回路のパルスと水平同期パルスの
周期の自走クロツクを計数して得られた前記カウ
ンタ回路の計数終了より少し遅れたタイミングの
パルスとの排他論理ゲートパルスを前記ラツチ回
路の動作パルスとして出力する動作パルス発生回
路と を備えた映像有無判定装置。[Claims for Utility Model Registration] In a video presence/absence determination device that is installed in a video device such as a playback device for an electronic still camera and determines whether or not a video signal is input, the device is provided with a video signal that is obtained by synchronously separating input signals of the video device. a counter circuit that digitally counts the number of pulses during the period in which the vertical synchronization pulse of the composite synchronization signal exists; a latch circuit that holds the count data of the counter circuit with a one-field delay; A comparator circuit that compares reference data and the counting data field by field and outputs a judgment result signal, and a free-running cycle of the pulse and horizontal synchronizing pulse of the counter circuit whose level is inverted every time the counter circuit finishes counting. and an operation pulse generation circuit that outputs an exclusive logic gate pulse, which is obtained by counting clocks and whose timing is slightly delayed from the end of counting of the counter circuit, as an operation pulse of the latch circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987160242U JPH0165573U (en) | 1987-10-20 | 1987-10-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987160242U JPH0165573U (en) | 1987-10-20 | 1987-10-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0165573U true JPH0165573U (en) | 1989-04-26 |
Family
ID=31442136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987160242U Pending JPH0165573U (en) | 1987-10-20 | 1987-10-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0165573U (en) |
-
1987
- 1987-10-20 JP JP1987160242U patent/JPH0165573U/ja active Pending
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