JPH0167585U

JPH0167585U -

Info

Publication number: JPH0167585U
Application number: JP1987163389U
Authority: JP
Priority date: 1987-10-26
Filing date: 1987-10-26
Publication date: 1989-05-01

Description

[Brief explanation of the drawing]

第１図は本考案実施例の指向方向制御装置の構
成図、第２図は本考案実施例の指向方向制御装置
の作用説明図である。１……可変電圧設定器、２……Ａ／Ｄ変換器、
３……ＲＯＭ、４……基準クロツク発生回路、５
……タイミング回路、６……分周回路、７……デ
コーダ、８―１〜８―ｉ〜８―ｎ……データラツ
チフリツプフロツプ、９―１〜９―ｉ〜９―ｎ…
…プリセツタブルカウンタ、１２……方向アドレ
ス信号、１４……基準クロツク信号、１６……振
動子アドレス信号、１９……分周クロツク信号、
２０―１〜２０―ｉ〜２０―ｎ……データラツチ
信号、２１……データロード信号、２３……位相
データ、３０―１〜３０―ｉ〜３０―ｎ……位相
制御信号、Ｔ（ｊ），ｔ（ｊ）……ｊ番目の位相
制御信号形成開始時点、Ｔ（Ｊ＋１），ｔ（ｊ＋
１）……ｊ＋１番目の位相制御信号形成開始時点
、ｔｏ……コントロールタイム、ｔｐ……プリセ
ツトタイム、φｉ（ｊ）……初期位相。 FIG. 1 is a block diagram of a pointing direction control device according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of the pointing direction control device according to an embodiment of the present invention. 1...Variable voltage setting device, 2...A/D converter,
3...ROM, 4...Reference clock generation circuit, 5
...Timing circuit, 6...Frequency dividing circuit, 7...Decoder, 8-1 to 8-i to 8-n...Data latch flip-flop, 9-1 to 9-i to 9-n...
... Presettable counter, 12 ... Direction address signal, 14 ... Reference clock signal, 16 ... Vibrator address signal, 19 ... Frequency division clock signal,
20-1 to 20-i to 20-n...data latch signal, 21...data load signal, 23...phase data, 30-1 to 30-i to 30-n...phase control signal, T(j) , t(j)...J-th phase control signal formation start point, T(J+1), t(j+
1)...j+1st phase control signal formation start point, to...control time, tp...preset time, φi(j)...initial phase.

Claims

[Scope of utility model registration request]

In a pointing direction control device for controlling the pointing direction of a transmitting/receiving beam of a transducer having a plurality of transducers arranged, a storage means for storing phase data for each transducer in each desired pointing direction; and specifying each pointing direction. direction specifying means for forming a direction address signal to sequentially specify each of the plurality of transducers and transmitting it to the storage means; a frequency dividing circuit which divides the frequency of the reference clock signal and outputs a frequency-divided clock signal; receives the frequency-divided clock signal and forms a data latch signal and a data load signal; a decoder which outputs the data load signal in synchronization with the transducer address signal and outputs the data load signal after outputting all the data latch signals in a desired orientation direction; a data latch circuit that receives the frequency-divided clock signal and the data latch signal and latches the phase data read out from the storage means; a presettable counter that receives a load signal, loads the phase data latched in the data latch circuit, and forms and outputs a phase control signal having an initial phase corresponding to the phase data; A pointing direction control device characterized by: