JPH0168546U - - Google Patents
Info
- Publication number
- JPH0168546U JPH0168546U JP1987164167U JP16416787U JPH0168546U JP H0168546 U JPH0168546 U JP H0168546U JP 1987164167 U JP1987164167 U JP 1987164167U JP 16416787 U JP16416787 U JP 16416787U JP H0168546 U JPH0168546 U JP H0168546U
- Authority
- JP
- Japan
- Prior art keywords
- error
- register
- host computer
- data
- sent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図はこの考案の一実施例を説明するための
ブロツク図、第２図はこの考案の変形実施例を示
すブロツク図、第３図はこの考案を適用すること
ができる端末装置の概要を説明するためのブロツ
ク図、第４図は従来の技術を説明するためのブロ
ツク図である。
１００Ａ〜１００Ｎ：端末装置、１０２：イン
ターフエース、１０３：出力データレジスタ、１
０４：ゲート、１０５：バスコントロール信号、
１０７：セレクタ、１０８：エラーステータスレ
ジスタ、１０９：エラー検出回路、１１０：識別
符号設定器、１１１：エラー発生レジスタ、１１
２：バスコントロール回路、１１３：割込信号発
生回路。
Fig. 1 is a block diagram for explaining an embodiment of this invention, Fig. 2 is a block diagram showing a modified embodiment of this invention, and Fig. 3 shows an outline of a terminal device to which this invention can be applied. FIG. 4 is a block diagram for explaining the conventional technology. 100A to 100N: Terminal device, 102: Interface, 103: Output data register, 1
04: Gate, 105: Bus control signal,
107: Selector, 108: Error status register, 109: Error detection circuit, 110: Identification code setter, 111: Error occurrence register, 11
2: Bus control circuit, 113: Interrupt signal generation circuit.
Claims (1)
する出力データレジスタと、 Ｂ エラーの発生によりエラーの内容がセツトさ
れるエラーステータスレジスタと、 Ｃ これら出力データレジスタとエラーステータ
スレジスタにセツトされたエラーデータの何れを
ホストコンピユータに送出するかを選択するセレ
クタと、 Ｄ エラーの発生によつてセツトされるエラー発
生検出レジスタと、 Ｅ このエラー発生検出レジスタがセツトされた
とき、バスラインに上記エラーデータを強制的に
出力させるバスコントロール回路と、 Ｆ エラー発生レジスタがセツトされたことを上
記ホストコンピユータに伝える割込信号発生回路
と、 を具備してなる端末装置。[Scope of Claim for Utility Model Registration] A. An output data register that holds data to be sent to a host computer; B. An error status register in which error contents are set when an error occurs; C. These output data registers and error status registers. A selector for selecting which of the set error data is to be sent to the host computer, D. An error occurrence detection register that is set when an error occurs, and E. When this error occurrence detection register is set, the bus line A terminal device comprising: a bus control circuit that forcibly outputs the error data to the host computer; and an interrupt signal generation circuit that notifies the host computer that the F error occurrence register has been set.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987164167U JPH0168546U (en) | 1987-10-26 | 1987-10-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987164167U JPH0168546U (en) | 1987-10-26 | 1987-10-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0168546U true JPH0168546U (en) | 1989-05-02 |
Family
ID=31449541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987164167U Pending JPH0168546U (en) | 1987-10-26 | 1987-10-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0168546U (en) |
-
1987
- 1987-10-26 JP JP1987164167U patent/JPH0168546U/ja active Pending
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