JPH0170427U - - Google Patents
Info
- Publication number
- JPH0170427U JPH0170427U JP1987165947U JP16594787U JPH0170427U JP H0170427 U JPH0170427 U JP H0170427U JP 1987165947 U JP1987165947 U JP 1987165947U JP 16594787 U JP16594787 U JP 16594787U JP H0170427 U JPH0170427 U JP H0170427U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- comparison
- signal
- comparator
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は、本考案の一実施例によるクロツク回
路の構成を示す回路図、および、第２図は、第１
図のクロツク回路の動作を説明するための信号波
形図である。
図面において、１０……水晶発振子、１２……
増幅器、１４……発振回路、１６……コンパレー
タ、２０……抵抗、２２……コンデンサ、２４…
…積分回路、２６……比較回路、２８……ボリユ
ーム回路、３０……抵抗、３２……コンデンサ、
３４……積分回路。
FIG. 1 is a circuit diagram showing the configuration of a clock circuit according to an embodiment of the present invention, and FIG.
FIG. 3 is a signal waveform diagram for explaining the operation of the clock circuit shown in the figure. In the drawings, 10...crystal oscillator, 12...
Amplifier, 14...Oscillation circuit, 16...Comparator, 20...Resistor, 22...Capacitor, 24...
... Integration circuit, 26 ... Comparison circuit, 28 ... Volume circuit, 30 ... Resistor, 32 ... Capacitor,
34...Integrator circuit.
Claims (1)
振回路と、 所望のデユーテイ比に対応した基準電圧を発生
するデユーテイ比基準電圧発生回路と、 前記アナログ信号と比較信号を入力してそれら
のレベル間の高低関係に応じた二値レベルをもつ
矩形波のクロツクパルスを出力するコンパレータ
と、 前記クロツクパルスを積分する積分回路と、 前記積分回路の出力信号を前記基準電圧と比較
してその比較誤差に応じた誤差信号を前記比較信
号として前記コンパレータに与える比較回路と、
を具備することを特徴とするクロツク回路。[Claims for Utility Model Registration] An oscillation circuit that generates an analog signal with a constant frequency, a duty ratio reference voltage generation circuit that generates a reference voltage corresponding to a desired duty ratio, and inputs the analog signal and a comparison signal. a comparator that outputs a rectangular clock pulse having binary levels corresponding to the high-low relationship between the levels; an integrating circuit that integrates the clock pulse; and a comparator that compares the output signal of the integrating circuit with the reference voltage. a comparison circuit that supplies an error signal corresponding to the comparison error to the comparator as the comparison signal;
A clock circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987165947U JPH0170427U (en) | 1987-10-29 | 1987-10-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987165947U JPH0170427U (en) | 1987-10-29 | 1987-10-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0170427U true JPH0170427U (en) | 1989-05-10 |
Family
ID=31452893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987165947U Pending JPH0170427U (en) | 1987-10-29 | 1987-10-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0170427U (en) |
-
1987
- 1987-10-29 JP JP1987165947U patent/JPH0170427U/ja active Pending