JPH01767A - thin film transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to thin film transistors such as field effect type transistors, particularly,
The present invention relates to a thin film transistor having a structure suitable for having a crystalline semiconductor layer.

[Prior Art] In recent years, scanning circuit sections of image reading devices such as long-dimensional photo sensors and large-area two-dimensional photo sensors for image reading, liquid crystal (abbreviated as LC), and electrochromic The driving circuit section of an image display device using an electroluminescent material (abbreviated as EC) or an electroluminescent material (abbreviated as EL) is formed on a predetermined substrate in line with the increase in the area of these display sections. It has been proposed to form a field effect thin film transistor using an f4 film as a material.

Thin film transistors for this purpose are required to be capable of high-speed operation and to have a simple manufacturing process. The ability to create clean scenes and the ability to create at low temperatures. In conventional semiconductor processes, the active layer of a transistor is made polycrystalline to enable high-speed operation. However, even the self-line method using high-temperature processes and ion implantation has the drawbacks of high cost and a large number of masks. Additionally, the conventional process has the disadvantage that the interface between the semiconductor layer and the insulating layer is exposed to the etching solution.

That is, thin film transistors on insulating substrates have been manufactured with a lower gate stagger type structure as shown in FIG.

First, a gate electrode 302 is made of metal on the substrate 301, an insulating layer is formed, a semiconductor layer 304 and a contact layer 105 are formed, an upper electrode is deposited, and an element is formed using photography. . First, after leaving only the main part of the semiconductor layer, the contact layer corresponding to the channel part (for example, N middle layer, P middle layer, etc.) is removed together with the upper contact metal layer, and the source and drain electrodes 308 are removed.
．． 309 is formed. This process has the advantage of being able to form an insulating layer, a semiconductor layer, and a contact layer in succession, resulting in a stable interface and good characteristics, and is often used in amorphous silicon thin film transistors.

However, this process is inappropriate when using crystalline semiconductor layers. This is because, in the case of most crystalline thin films, the crystallinity improves as the film grows, so the crystallinity of the semiconductor layer near the interface with the insulating layer, which corresponds to the channel part of a thin film transistor, is poor and insufficient. characteristics cannot be demonstrated. Therefore, when forming a thin film transistor using a crystalline semiconductor layer such as polycrystalline semiconductor layer, a -F gate coplanar type 413 structure as shown in FIG. 4 is used. The manufacturing process of this thin film transistor includes first depositing a semiconductor layer polysilicon 402 on a substrate 401, then depositing a contact layer 403 (for example, an n-layer),
After depositing metal layer 404, the contact layer for channel portion 405 is removed. Next, after depositing an insulating layer 406, contact holes 407 and 4 for source and drain are deposited.
Form 08. Finally, source, gate, and drain electrodes 410, 411, and 412 are formed using photolithography and etching based on the upper electrode metal. This process has the disadvantage that the channel surface 405 is exposed to an etching atmosphere during channel formation. Therefore, the interface 409 between the insulating layer 406 and the semiconductor layer 402 cannot always be formed in the same state, resulting in variations in characteristics and deterioration.

[Problems to be Solved by the Invention] The present invention solves the conventional problems and provides a thin film transistor that can operate at high speed, has a simple manufacturing process, can easily create a clean interface, and can be manufactured at low temperatures. This was done as intended.

Furthermore, the present invention has been made to provide a thin film transistor particularly suitable for constructing a high-performance polycrystalline thin film transistor, and particularly to provide a large-area semiconductor device using such a polycrystalline thin film transistor as an element.

[Means for Solving the Problems] The thin film transistor provided by the present invention has a structure in which the contact layer connecting the semiconductor layer and the source and drain electrodes is deposited only in the contact holes at a body temperature of 400°C or less. It is characterized by a layer of

The thin film transistor of the present invention is mainly composed of Si, 5i-G
The constituent atoms are elements of group Ⅰ of the periodic table such as e-alloy, Ge, and C. It can be preferably applied when the method has a semiconductor layer.

However, within the scope of application of the present invention, the present invention is not limited to group Ⅰ elements, but can also be applied to ①-③ group, m-V group compound semiconductor layers, etc.

[Example] The present invention will be described below regarding a case where Sl is used as a constituent atom of a semiconductor layer.

The steps for manufacturing the thin film transistor of the present invention will be explained with reference to FIGS. 1(a) to 1(d).

First, a semiconductor layer 102 is deposited on a substrate 101 . Next, after depositing an insulating layer 103, contact hole portions IQ4 and 105 for burying the source and drain are formed by photolithography.

Next, the contact layer 106 (source part) is formed by the CV[) method.
, 107 (drain part) to the contact hole part 104,
105. In this case, no film is deposited at locations other than the contact hole portions (for example, 108).

Next, the insulating layer 109 is deposited again, and the contact hole 110 is
(source part) and 111 (drain part) are formed, and after metal is deposited on the entire surface, a source electrode 112, a gate electrode 113, and a drain electrode 114 are formed by photolithography to complete a thin film transistor.

The insulating layer of the present invention is SiN, which has a good selectivity during deposition with Si or doped Si layer which is a contact layer.

SiO2, or 5i-N-0, Al203, CaF
2, aF2 membrane, etc. is used.

The contact layer used in the present invention is mainly made of amorphous Si or polycrystalline S1, and is p-type or n-type depending on the conductivity type of the lower semiconductor layer and the operation method (accumulation type, inversion type) of the thin film transistor. doping elements (P, B, Sb, As, etc.) are introduced.

Polycrystalline Si is particularly preferably used as the semiconductor layer used in the present invention.

In this example, the raw material for depositing the contact layer can be selected from various conventionally known raw materials, but is produced from a compound containing silicon and halogen in a space different from the film forming space (hereinafter referred to as the decomposition space). It is advantageous to deposit the active species by associative reaction between the active species produced by H and the active species produced by H. As a compound,
A compound in which some or all of the hydrogen atoms of a chain or cyclic silane compound are replaced with jδ by a halogen atom is used, specifically, for example, 5iuY2u+2 (u is an integer of 1 or more, Y
is F CI Br or I), cyclic silicon halide represented by 5ivY2ma (V is an integer of 3 or more, Y has the above-mentioned meaning), 5iuHxYma ( U and Y have the meanings given above.

Examples include chain or cyclic compounds represented by x+Y=2U or 2u+2.

Specifically, SiF, , (SiF 2 ) 5 , (S
iF2 ) 6 , 5i2F 6 , 5i3F B ,
5iHF 3 , SiH2F 2.5iCI a , (
SiC17) 5 , 5iHCl 3 , SiH2C1
2, SiH3CI, 5iC16, 5iBr4, etc., which are in a gaseous state or can be easily gasified.

In order to generate active species, in addition to the above-mentioned compound containing silicon and halogen, silicon compounds such as simple silicon, hydrogen, halogen compounds, inert elements, etc. can be used in combination.

The active species generated from H2 used in the present invention can also be generated by mixing an inert element.

The contact layer in the present invention can be deposited as a desired film at a substrate temperature of 400° C. or less, but at this time the active species are generated in advance in a space different from the film formation space.

As a method for generating active species in the decomposition space according to the present invention, excitation energy such as discharge energy, thermal energy, light energy, etc. is used in consideration of each condition and device.

As an example of the present invention, a case will be described in which a Si film is deposited using discharge energy and thermal energy as shown in FIG.

First, a heating substrate holder 219 is placed inside a T-shaped reaction quartz tube 218, and a 2×10
After drawing a vacuum below Torr, first connect the mass flow meters 205 and 2 from the inlet of 223 to the ribbons 201 and 202.
06, SiF using stop valve 209.210
6. Ar gas is introduced and decomposed in an electric furnace 217, and active species SiF 2 is introduced into the quartz tube intersection part 225. The temperature range of the electric furnace is preferably 6000 to 800°C, more preferably 6500 to 750°C.

Next, cylinder 203.204, mass flow meter 207
, 208, H7 using stop pulp 211° 212
, Ar gas are introduced from the inlet 224, respectively.

Using discharge energy supplied from a microwave 2.45 GHz power source 214, Ar and H2 are applied to the applicator 4.
Activate at 13. Discharge energy power and shite is 50
W ~600W is suitable, and 100W ~ 400W is selected as the optimum value.

After gas is introduced from both input ports 223 and 224 and becomes stable, the pressure inside the pipe is kept constant using a valve 226.

The preferred value for the pressure is 0.001 to 1OT.

The range is rr. The substrate 220 is installed at 219 and maintained at a constant temperature. A suitable value for the substrate temperature is 4000°C or less, and an optimum value is 300°C to 100°C. No. 1 (The deposition of Si film on the body is Si, SiO2 from l plate, stone%)
By adjusting the gas pressure, it is possible to select conditions that deposit on Si but not on Si02, SiN, etc. by adjusting the gas pressure. Flow of hydrogen gas H2 and Si2F6 gas -
The optimum range for the 1 ratio is selected to be 10 to 0.5.

In the present invention, it is possible to dope with an impurity element when forming a contact layer or the like. Suitable impurity elements to be used include elements of group 1 of the periodic table, such as B, AI, Ga, and In, as pear-shaped impurities. N-type impurities include elements of group V of the periodic table, such as P,
As, Sb, Bi, etc. are suitable. Particularly optimal ones include B, AI, P, As, and Sb. The number of impurities to be doped is determined as appropriate depending on the desired electrical and optical characteristics.

As a compound containing such impurities as a component, it is preferable to select a compound that is in a gaseous state at normal temperature and normal pressure, or at least under the conditions for forming a deposited film, and that can be easily vaporized using an appropriate vaporizing device. Such compounds include PH3, P2H4, PF3, PFc, , Pil
l:13, AsH3, SbF5, BF3, BC
l3, BBr3, B7 H6, B4 H10, B5
Examples include HQ, AlCl3, and the like. One type of compound containing an impurity element may be used or two or more types may be used in combination.

In order to introduce a compound containing an impurity element as a component into the film forming space, it can be mixed with the silicon compound etc. in advance, or it can be introduced individually using a plurality of independent gas supply sources. be able to.

The thin film transistor of the present invention will be further explained below by giving specific examples.

(Example 1) First, the substrate toi (Corning #705
9) A polysilicon film 102 was deposited thereon using the apparatus shown in FIG. Place the board on the board holder 219, 2 x 1
After creating a vacuum of 0 Torr, the substrate temperature was increased to 250°C.
5i7Ff, mass flow 2 from Ponbe 2ol
05. Through the stop valve 209, the quartz 'i? 218
Nigas Ff, 30% SCCM was introduced. During this circulation, Ar gas is supplied from the pump 202 through the mass flow meter 406 and the stop valve 210 at a gas flow rate of 205.
It was introduced with CCH. At this time, the temperature of the electric furnace was maintained at 700°C.

Next, B2 and Ar gas are introduced from cylinders 203 and 204 through mass flow 207 and 208 and stop valves 211 and 212, and the pressure is maintained at 0.3 Torr.
4, 200 W of 2.45 GHz microwave energy was applied.

H2 and Ar flow rate 5osccM, 5°S
CCM. A polysilicon film of 0.8 islands was deposited in 30 minutes. Thereafter, the carrier vacuum was broken and the sample was taken out into the atmosphere, and 5iNllQ was deposited again using the glow discharge method. The substrate temperature was kept at 250°C and NH3 = 20 SCCM.

SiH4 10%/H2 dilution 5 SCCM, 13.5MH
z (1) Discharge power 5W (substrate holder 2ooffi
ff+φ) to form a 50OA SiN film.

Next, holes 104 and 105 for source and drain contacts were formed using photolithography.

A contact layer was deposited in the contact hole using the apparatus shown in FIG. 2 again.

Under the same substrate temperature, gas flow rate, and pressure as when depositing the polysilicon film, 11,000 pp of phosphine was added in an argon-based gas cylinder 22 in Si7F6 gas.
Mass flow 229 from 7, 5S through valve 230
CCM gas was simultaneously introduced.

Microwave discharge time is 1o o oA p in 20 minutes.
A layer of doped n-type polysilicon was deposited. At this time, the polysilicon layer is not deposited on the 5i-N film 108J, but is deposited only on the contact hole, and the contact layer 1
06.107. The specific resistance was 0.1 Ωcm. Next, using the glow discharge method again, under the same conditions as above, the
A total of 3000 SiN films were deposited to form a total of 3000 gate insulating films. Next, holes for source and drain contacts were made using photolithography. Finally, after evaporating AI by resistive heating at 1500 nm, source, gate, and drain electrodes 112, 113, and 114 were formed by photoetching to complete the transistor.

Table 1 shows a comparison of the characteristics when using the process for manufacturing the upper gate thin film transistor shown in Figure 2, and it was found that the characteristics were greatly improved, indicating that this process is useful. I found out something.

(Example 2) Polysilicon was deposited using the apparatus shown in FIG. 2 in the same manner as in Example 1. At this time, Si2 F 6 and 82) 161000
A B-doped P-type polysilicon layer 500A was deposited using a flow of 59 CCM of ppm/argon based gas. Deposition was carried out under the same conditions as in the example,
A thin film transistor having the structure shown in FIG. 1 was fabricated. L
The specific resistance of the p-type polysilicon layer was 0.1 film cm. The n-type polysilicon 7 layer 106, which is a contact layer, and the p
The rectification with the mold polysilicon layer 102 was good, and the n value was l.

The mobility of the obtained TPT was 56 cm2/v, sec
The threshold voltage is 1.5 V and does not change over time, and the variation in the movement of 10 transistors in a lam-square chip is within ±1.The threshold voltage is 0.5 V.
It was within 0.05V.

(Example 3) Polysilicon was deposited using the apparatus shown in FIG. 2 in the same manner as in Example 1. As silicon-based gas, SiF was used instead of Si7F6, and like argon gas, it was introduced at a flow rate of 30 SCC and 5 SCCM, respectively, and the energy of the microwave power source was discharged with a 4-15 applicator to excite it. Species S iF7 was generated. The pressure is 0.1 T
orr, substrate temperature is 300℃, microwave power is 20
It was set to 0W. The H2 and Ar gas conditions were the same as in Example 1, and 0.85 g of polysilicon film was deposited in 20 minutes.

Next, using the glow discharge method, N20 = 3 at a substrate temperature of 250'C.
0900M, SiH4 10%/H2 dilution, IOSCC
A SiO 2 film of 500 μm was formed at a discharge power of 10 W (substrate holder 20 ff 1 mφ) at 13.5 Ei MHz.

Next, in the same manner as in Example 1, a thin film transistor as shown in FIG. 1 was fabricated.

In this case, as in Example 1, the n-type polysilicon layer is
It was not deposited on the Si02 film 108, but was deposited only in the contact hole, and a good contact layer was obtained. The characteristics of the thin film transistor are that the mobility is 25.6 and the threshold voltage is 8. OV,log(IO,,,/'tY-
, :) was 5.5, and stable characteristics with little variation were obtained.

[Effects of the Invention] The present invention provides a stable thin film transistor with good characteristics and little variation. Further, according to the present invention, the contact layer can be selectively deposited at a clean interface and at a low substrate temperature, thereby simplifying and stabilizing the manufacturing process. In particular, the present invention can be suitably utilized as a high-performance polycrystalline thin film transistor, particularly as a large-area semiconductor device.

[Brief explanation of the drawing]

FIGS. 1(a) to (direct) are cross-sectional views for explaining the manufacturing process of the thin film transistor of the present invention. FIG. 2 is a schematic diagram for explaining the outline of a deposited film forming apparatus used for manufacturing the thin film transistor of the present invention. FIG. 3 is a cross-sectional view for explaining the manufacturing process of a conventional lower gate stagger type F4 film transistor. FIG. 4 is a cross-sectional view for explaining the manufacturing process of a conventional upper gate coplanar type thin film transistor. DESCRIPTION OF SYMBOLS 101... ノ, Ii board, 102... Semiconductor layer, 103... Insulating layer, 104... Contact hole, 105... Contact hole 106... Contact layer, 107... Contact i. Layer, 109... Insulating layer, 110... Contact hole 111... Contact hole, 112... Source electrode, 113... Gate electrode, 114... Drain electrode, 201-204... Cylinder , 205-208...Mass flow meter 209-21
2... Valve 213-215... Applicator 214-216... Power supply, 217... Electric furnace 218... Quartz tube, 219... Substrate holder, 220... Substrate, 221... Exhaust pump 223, 224...Gas inlet, 225...Cross section, 226...Pressure adjustment pulse 301...Substrate, 302...Gate electrode, 303...Insulating layer, 304...Semiconductor Layer 305...Contact layer, 308...Source electrode, 309...Drain electrode, 401...Substrate, 402...Semiconductor layer, 403...Contact layer 404...Metal layer, 405 ...Channel portion 406...Insulating layer 407...Contact hole, 408...Contact hole 409...Interface, 410...Source electrode, 411...Gate electrode, 412...Drain electrode . rri* of drawings 1 Figure +06 107 108 No. 3 N: 2 Ward No. 4 Amendment to Drawing Procedures (Radio) August 20, 1985 Kunio Ogawa, Commissioner of the Japan Patent Office Patent application for indications of 1 and 21S 1986-73620 No. 2, Name of the invention Thin film transistor 3, Relationship with the amended case Patent applicant name (Zoo) Canon Co., Ltd. 4 Agent address 40 Mori, Toranomon, 5-13-1 Toranomon, Minato-ku, Tokyo Bill's name (6538) Patent attorney Tsuki Yamashita 1,110 Submit the detailed statement, detailed drawings, and power of attorney on the first attached sheet.

Claims (1)

[Claims] A thin film transistor characterized in that a contact layer connecting a semiconductor layer and source and drain electrodes is a layer deposited only in a contact hole portion at a substrate temperature of 400° C. or less.